CN115865146A - System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture - Google Patents
System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture Download PDFInfo
- Publication number
- CN115865146A CN115865146A CN202211579561.2A CN202211579561A CN115865146A CN 115865146 A CN115865146 A CN 115865146A CN 202211579561 A CN202211579561 A CN 202211579561A CN 115865146 A CN115865146 A CN 115865146A
- Authority
- CN
- China
- Prior art keywords
- digital
- frequency
- receiving
- adc
- clock source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Radio Transmission System (AREA)
Abstract
The invention relates to a system for realizing MIMO synchronous data receiving based on a digital direct acquisition architecture, which comprises N receiving systems, wherein each receiving system comprises N receiving channels and 1 clock source, each receiving channel comprises an amplifier AMP, an adjustable attenuator and an analog-to-digital converter (ADC), the amplifiers AMP, the adjustable attenuator and the analog-to-digital converters (ADC) in the receiving channels are sequentially connected, the output end of the clock source is connected with the analog-to-digital converters (ADC) of each receiving channel, and the analog-to-digital converters (ADC) of each receiving system receive a synchronous clock output by the clock source. The system for realizing MIMO synchronous data receiving based on the digital direct sampling architecture adopts the digital direct sampling architecture, and the data phase error in the MIMO multichannel data receiving system is converged.
Description
Technical Field
The invention relates to the technical field of wireless communication receiving, in particular to the field of multichannel large-bandwidth data receiving of an MIMO (multiple input multiple output) system, and specifically relates to a system for realizing MIMO synchronous data receiving based on a digital direct acquisition architecture.
Background
With the popularization of wireless mobile communication, people have higher and higher use requirements on wireless internet. According to channel capacity formula
It can be seen that the system capacity of the wireless communication network can be effectively increased by increasing the number of channels and the signal bandwidth, and therefore the enabling technology of mobile communication includes Multiple-Input Multiple-Output MIMO (Multiple-Input Multiple-Output) and a large bandwidth of 100MHz of 5G communication.
The MIMO system increases the number of channels of the system, and increases the total capacity of the system, but also brings new challenges: the consistency of phases among a plurality of channels must be ensured, so that the reciprocity of uplink and downlink in 5G communication can be realized, and the reliability of communication is ensured. In general, the MIMO system ensures data phase synchronization among multiple channels by phase alignment among multiple channels of the receiver. The calibration mode does not distinguish whether the phase error source is baseband data or local oscillation or a radio frequency channel, so the phase error is random and uncontrollable. Any link has a problem, and the phases are randomly distributed from 0 to 360 degrees, so that the MIMO system cannot work normally.
The currently commonly used receiver architecture mainly includes superheterodyne and zero intermediate frequency, and although the superheterodyne architecture is most commonly used, the superheterodyne architecture has complex circuits, requires a large number of devices, and has a higher cost particularly for MIMO multiple channels, so that the superheterodyne architecture is used in a general MIMO system less. The zero intermediate frequency architecture has the advantages of wide frequency band, large bandwidth and simple circuit, and is a common architecture in the current MIMO system. But the zero intermediate frequency architecture has inherent problems of local oscillator leakage and image rejection. In the zero intermediate frequency architecture, the local oscillator and the image signal are both in the signal band, and cannot be filtered by the filter at all, and the problem becomes more prominent as the frequency increases.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a system for realizing MIMO synchronous data reception based on a digital direct acquisition architecture, which has the advantages of large bandwidth, simple circuit and high phase consistency.
In order to achieve the above object, the system for implementing MIMO synchronous data reception based on digital direct sampling architecture of the present invention is as follows:
the system for realizing MIMO synchronous data reception based on the digital direct acquisition architecture is mainly characterized in that the system comprises N receiving systems, each receiving system comprises N receiving channels and 1 clock source, each receiving channel comprises an amplifier AMP, an adjustable attenuator and an analog-digital converter (ADC), the amplifiers AMP, the adjustable attenuator and the analog-digital converters (ADC) in the receiving channels are sequentially connected, the output end of the clock source is connected with the analog-digital converters (ADC) of each receiving channel, the analog-digital converters (ADC) of each receiving system receive synchronous clocks output by the clock sources, and the amplifiers AMP and the adjustable attenuator are used for adjusting the power amplitude of radio frequency receiving signals so that the signal power input into the analog-digital converters (ADC) is kept at a proper power level.
Preferably, each receiving system includes a reference Ref interface and a synchronization trigger SYNC signal interface, both the reference Ref interface and the synchronization trigger SYNC signal interface are connected to the input end of the clock source, the clock source receives a homologous reference signal Ref through the reference Ref interface to achieve synchronization of the phase-locked loops in each clock source, and the clock source receives homologous synchronization trigger SYNC signals through the synchronization trigger SYNC signal interface to achieve synchronization of the outputs of the N × N frequency dividers of the N clock sources.
Preferably, the ADC comprises a digital sampling moduleThe digital sampling module and the NCO frequency shifting module are both connected with the clock source, and the digital sampling module is provided by f provided by the clock source clk Frequency multiplication output sampling rate f s Carrying out digital direct sampling, wherein the NCO frequency shifting module provides f through a clock source clk F via digital phase-locked loop output NCO The analog-digital converter ADC is used for shifting the frequency of the received radio frequency analog signal according to a sampling rate f s And (4) carrying out digital direct acquisition, converting the analog signal into a digital signal, and moving the frequency to a frequency which can be processed by a rear-stage circuit through an NCO frequency moving module.
Preferably, the clock source includes a phase-locked loop and n frequency dividers, an output end of the phase-locked loop is connected to the n frequency dividers, the phase-locked loop uses a reference signal Ref to perform phase locking, and n synchronous clock signals f are output after passing through the n frequency dividers clk Said n synchronized clock signals f clk Respectively connected to n analog-to-digital converters (ADC) to obtain n synchronous sampling rates s And n synchronous digital phase-locked frequencies f NCO 。
Preferably, the phase-locked loop enables the n frequency dividers to divide frequency at the same time by synchronously triggering the SYNC signal interface, so as to enable the n clock signals f clk Are all synchronous clock signals.
Preferably, the N receiving systems are connected by equal length lines, and the phase difference of the N rf channels of the N receiving systems is controlled by the equal length lines.
The system for realizing MIMO synchronous data receiving based on the digital direct sampling architecture adopts the digital direct sampling architecture, and the data phase error in the MIMO multichannel data receiving system is converged.
Drawings
Fig. 1 is a circuit block diagram of a system for implementing MIMO synchronous data reception based on a digital direct sampling architecture according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The system for realizing MIMO synchronous data reception based on a digital direct acquisition architecture comprises N receiving systems, wherein each receiving system comprises N receiving channels and 1 clock source, each receiving channel comprises an amplifier AMP, an adjustable attenuator and an analog-digital converter (ADC), the amplifiers AMP, the adjustable attenuator and the ADC in the receiving channels are sequentially connected, the output end of the clock source is connected with the analog-digital converters (ADC) of each receiving channel, the analog-digital converters (ADC) of each receiving system receive synchronous clocks output by the clock source, and the amplifiers AMP and the adjustable attenuator are used for adjusting the power amplitude of radio frequency receiving signals so that the signal power input into the analog-digital converters (ADC) is kept at a proper power level.
As a preferred embodiment of the present invention, each receiving system includes a reference Ref interface and a synchronization trigger SYNC signal interface, both the reference Ref interface and the synchronization trigger SYNC signal interface are connected to an input end of a clock source, the clock source receives a homologous reference signal Ref through the reference Ref interface to achieve phase-locked loop synchronization inside each clock source, and the clock source receives a homologous synchronization trigger SYNC signal through the synchronization trigger SYNC signal interface to achieve output synchronization of N × N frequency dividers of N clock sources.
As a preferred embodiment of the present invention, the ADC includes a digital sampling module and an NCO frequency shifting module, both of which are connected to a clock source, and the digital sampling module is provided with an F provided by the clock source clk Frequency multiplication output sampling rate F s Carrying out digital direct sampling, wherein the NCO frequency shifting module provides F through a clock source clk F via digital phase-locked loop output MCO The analog-digital converter ADC is used for shifting the frequency of the received radio frequency analog signal according to a sampling rate f s Performing digital direct sampling, converting analog signal into digital signal, and connectingAnd the NCO frequency shifting module is used for shifting the frequency to the frequency which can be processed by a rear-stage circuit.
As a preferred embodiment of the present invention, the clock source includes a phase-locked loop and n frequency dividers, an output end of the phase-locked loop is connected to the n frequency dividers, the phase-locked loop uses a reference signal Ref to perform phase locking, and n synchronous clock signals f are output after passing through the n frequency dividers clk Said n synchronized clock signals f clk Respectively connected to n analog-to-digital converters (ADC) to obtain n synchronous sampling rates f s And n synchronous digital phase-locked frequencies f NCO 。
In a preferred embodiment of the present invention, the phase-locked loop divides the frequency of n frequency dividers at the same time by synchronously triggering the SYNC signal interface, and further divides the frequency of n clock signals f clk Are all synchronous clock signals.
As a preferred embodiment of the present invention, the N receiving systems are connected by equal length lines, and the phase differences of the N rf channels of the N receiving systems are controlled by the equal length lines.
In the specific implementation manner of the present invention, the problems of random distribution and non-convergence of data phase errors in the MIMO multichannel data receiving system need to be solved, and the problems of local oscillator leakage and image rejection in the zero architecture of the conventional receiver need to be solved. The scheme emphasizes synchronization of large-scale MIMO, the number of channels is more, not only a plurality of ADCs in the same layer are synchronized, but also clock synchronization among multiple layers is included, and further ADCs among the multiple layers are also synchronized, and the scheme is greatly different from the prior art.
The invention provides a MIMO (multiple input multiple output) large-bandwidth synchronous data receiving system based on a digital direct acquisition architecture, which has the advantages of wide frequency band, large bandwidth, simple circuit, high phase consistency and the like.
The system comprises a plurality of analog-digital converters, a plurality of clock sources and synchronous trigger signals, and can realize the synchronous data receiving of multi-channel broadband. The specific implementation scheme is as follows:
as shown in schematic block diagram 1, a total of N receiving systems are included, and each system includes N receiving channels and 1 clock source. Each receiving channel comprises an amplifier AMP, an adjustable attenuator and an analog-to-digital converter ADC. The clock source splits off multiple synchronous clocks to the n ADCs in each system. The N receiving systems use the reference signal Ref of the same source and the synchronous trigger SYNC signal of the same source to carry out output clock synchronization of N clock sources.
And the receiving channels use a digital direct sampling receiver architecture, and each receiving channel comprises a plurality of amplifiers, a plurality of adjustable attenuators and one analog-digital converter (ADC).
The amplifier and the adjustable attenuator are used for adjusting the power amplitude of the radio frequency receiving signal, so that the signal power entering the ADC is kept at a reasonable power level. Too large a signal level may cause saturation of the signal entering the ADC to cause distortion, and too small a signal level may cause a reduction in the signal-to-noise ratio, SNR, of the signal entering the ADC.
The ADC is mainly internally provided with two parts, namely digital sampling and NCO frequency shifting. F provided by clock source inside ADC clk Multiple frequency output sampling rate f s For digital direct sampling. Digital phase locked loop NCO inside ADC using f provided by clock source clk F output after digital phase-locked loop NCO The frequency is shifted. After the signal passes through the power adjusting circuit, the broadband radio frequency ADC is used for receiving the radio frequency analog signal according to the sampling rate f s And performing digital direct acquisition, converting the analog signal into a digital signal, moving the frequency to a frequency which can be processed by a rear-stage circuit through a digital phase-locked loop NCO, and finally transmitting the digital signal with the moved frequency to the rear-stage circuit for further processing.
The clock source in a single receiving system internally comprises a phase-locked loop and n frequency dividers. The phase-locked loop uses the reference signal Ref to perform phase locking, and then outputs n clock signals f after passing through n frequency dividers clk If the trigger SYNC is used, it can ensure that n frequency dividers divide frequency at the same time, and n clock signals f clk Are all synchronous clock signals. n synchronous clock signals f clk The output is connected to n ADCs, so that n synchronous sampling rates f can be obtained s And n synchronous digital phase-locked frequencies f NCO 。
n ADCs using synchronized sampling rate f s The data synchronization after digital direct sampling can be regarded as the aforementioned baseband data synchronization. Using n synchronized digital phase-locked frequencies f NCO The frequency shifting may be considered as the local oscillator synchronization mentioned above. Namely, in a single receiving system, the baseband data is synchronous, and the local oscillators are synchronous.
Connecting the reference signals Ref of the same source to clock sources on the N receiving systems among the N receiving systems, and synchronizing phase-locked loops in each clock source; the synchronization trigger SYNC signal of the same source is used to ensure the output synchronization of N × N frequency dividers of N clock sources, i.e., N × N clock signals f clk Are all synchronous clock signals, thereby N × N sampling rates f s And Nxn digital phase-locked frequencies f NCo Are all synchronization signals.
And the synchronization of baseband data and local oscillation of Nxn receiving channels is ensured by the homologous reference signal Ref and the homologous synchronization trigger SYNC signal.
The phase consistency among multiple receive channels in a MIMO system also includes the phase error of each rf channel. The error is not further processed synchronously, although the error exists in phase, the consistency of general radio frequency circuits is better, and although the error exists among multiple channels, the distribution of the phase error is converged. That is, the calibration data of a certain channel is erroneous, and the phase of the channel is also in a controllable range, so that the MIMO system cannot work normally.
In summary, the scheme of the present invention is to use a digital direct sampling architecture, which can realize direct sampling transmission of MIMO multi-channel radio frequency signals, and has no local oscillator and image problem, and the baseband data and local oscillator phases between multiple channels are synchronous, and the phase consistency of the whole MIMO system is relatively high.
The specific implementation circuit of the invention is described as follows:
the MIMO synchronous receiving system of the invention, the frequency supports DC-6 GHz, have included 2 receiving systems altogether, each receiving system has included 32 receiving channels.
For a single receiving system, 32 radio frequency receiving channels, 4 8-channel ADCs, one clock source, one reference Ref interface and one synchronous trigger SYNC signal interface are included.
The radio frequency channel adjusts the received DC-6 GHz radio frequency signal to a proper level, about-10 dBm is transmitted to the ADC, the ADC carries out digital direct sampling, and the frequency is shifted to be near zero frequency.
After the clock source internal phase-locked loop is locked to 2.4576GHz, the clock 122.88MHz signal which is divided into 4 paths of equal phases through the frequency divider and the synchronous trigger signal is output to 4 8-channel ADCs. After the 4 8-channel ADCs receive the clock signal, the internal frequency multiplication is the high-frequency sampling rate f s Sampling is carried out, and f is adjusted by the digital phase-locked loop according to the radio frequency received on the radio frequency channel NCO The frequency is such that the rf signal is shifted to a digital signal with a frequency of about zero that the baseband can process.
Between 2 receiving systems, a reference signal Ref is used to divide into two paths, and a synchronous trigger signal SYNC is divided into two paths and respectively transmitted to clock sources of two receiving systems to ensure 122.88MHz synchronization of 8 clock signals of the two receiving systems; and further, the synchronization of baseband data sampled by 64 ADCs and the synchronization of a digital phase-locked loop are ensured.
The phase difference of the radio frequency channels among the 2 receiving systems is controlled by an equal-length line, the radio frequency signal lines are subjected to equal-length processing, the inherent radio frequency error is eliminated theoretically, and finally, the errors caused by the consistency error of a chip and the processing precision are very small phase errors and only account for a very small part in the range of 360 degrees.
By the method, the direct sampling receiving of 64 radio frequency channels is realized, the problems of local oscillation and mirror image do not exist, digital phase-locked loops and baseband digital errors are eliminated, the radio frequency channel errors are optimized, and the phase errors of the 64 radio frequency channels are smaller on the whole.
For a specific implementation scheme of this embodiment, reference may be made to relevant descriptions in the foregoing embodiments, which are not described herein again.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The system for realizing MIMO synchronous data receiving based on the digital direct sampling architecture adopts the digital direct sampling architecture, and the data phase error in the MIMO multichannel data receiving system is converged.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. A system for realizing MIMO synchronous data reception based on a digital direct acquisition architecture is characterized in that the system comprises N receiving systems, each receiving system comprises N receiving channels and 1 clock source, each receiving channel comprises an amplifier AMP, an adjustable attenuator and an analog-digital converter (ADC), the amplifiers AMP, the adjustable attenuator and the ADC in the receiving channels are sequentially connected, the output end of the clock source is connected with the analog-digital converters (ADC) of each receiving channel, the analog-digital converters (ADC) of each receiving system receive synchronous clocks output by the clock source, and the amplifiers AMP and the adjustable attenuator are used for adjusting the power amplitude of radio frequency receiving signals so that the signal power input into the analog-digital converters (ADC) is kept at a proper power level.
2. The system according to claim 1, wherein each receiving system includes a reference Ref interface and a synchronization trigger SYNC signal interface, both the reference Ref interface and the synchronization trigger SYNC signal interface are connected to an input end of the clock source, the clock source receives a homologous reference signal Ref through the reference Ref interface to achieve synchronization of a phase-locked loop in each clock source, and the clock source receives a homologous synchronization trigger SYNC signal through the synchronization trigger SYNC signal interface to achieve synchronization of output of N × N frequency dividers of N clock sources.
3. The system according to claim 1, wherein the ADC comprises a digital sampling module and an NCO frequency shift module, both of which are connected to a clock source, and the digital sampling module is provided with f via the clock source clk Frequency multiplication output sampling rate f s Carrying out digital direct sampling, wherein the NCO frequency shifting module provides f through a clock source clk F via digital phase-locked loop output NCO The analog-to-digital converter ADC is used for shifting the frequency of the received radio frequency analog signal according to a sampling rate f s And (4) carrying out digital direct acquisition, converting the analog signal into a digital signal, and moving the frequency to a frequency which can be processed by a rear-stage circuit through an NCO frequency moving module.
4. The system according to claim 1, wherein the clock source comprises a phase-locked loop and n frequency dividers, and the phase-locked loop is configured to receive the MIMO synchronization dataThe output end of the loop is connected with n frequency dividers, the phase-locked loop uses a reference signal Ref to carry out phase locking, and n synchronous clock signals f are output after passing through the n frequency dividers clk Said n synchronized clock signals f clk Respectively connected to n analog-to-digital converters (ADC) to obtain n synchronous sampling rates f s And n synchronous digital phase-locked frequencies f NCO 。
5. The system according to claim 4, wherein the PLL synchronously triggers the SYNC signal interface to divide the frequency of n frequency dividers at the same time, thereby enabling n clock signals f clk Are all synchronous clock signals.
6. The system according to claim 1, wherein the N receiving systems are connected by equal length lines, and the phase difference of the N rf channels of the N receiving systems is controlled by the equal length lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211579561.2A CN115865146A (en) | 2022-12-09 | 2022-12-09 | System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211579561.2A CN115865146A (en) | 2022-12-09 | 2022-12-09 | System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115865146A true CN115865146A (en) | 2023-03-28 |
Family
ID=85671494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211579561.2A Pending CN115865146A (en) | 2022-12-09 | 2022-12-09 | System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115865146A (en) |
-
2022
- 2022-12-09 CN CN202211579561.2A patent/CN115865146A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9900065B2 (en) | System and method for high-speed analog beamforming | |
| US10396845B2 (en) | Split microwave backhaul transceiver architecture with coaxial interconnect | |
| CN204068947U (en) | Adjustable mean frequency wireless receiver and bluetooth module | |
| FI111422B (en) | Transmitter, transmission method and receiver | |
| CN108631809B (en) | Multichannel digital TR assembly | |
| US11736131B2 (en) | Segmented receiver for wireless communications | |
| US11206163B2 (en) | Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver | |
| CN111245472B (en) | Radio frequency transceiver chip, and synchronization system and method for radio frequency transceiver chip | |
| US9998138B1 (en) | Time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits for multi-channel receivers | |
| US7227920B2 (en) | Circuit and method for correcting clock duty cycle | |
| US10979089B2 (en) | Method and device for measuring antenna reflection coefficient | |
| CN110492964B (en) | CLOCK source synchronization device and method based on CLOCK BUFF | |
| CN218633941U (en) | System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture | |
| JPWO2016174805A1 (en) | Wireless access system and control method thereof | |
| CN115865146A (en) | System for realizing MIMO synchronous data receiving based on digital direct acquisition architecture | |
| CN112242876A (en) | Method for obtaining clock signal provided by external clock source and wireless communication device | |
| US7346136B1 (en) | Rake receiver | |
| US11929767B2 (en) | Method for transferring signals via transmission interface and communications apparatus utilizing the same | |
| CN114124278B (en) | Digital synchronization circuit and method for digital simultaneous multi-beam transmission | |
| CN114157292A (en) | Ultra-low phase noise frequency synthesizer | |
| US7068745B2 (en) | Feedforward amplitude cancellation topology for multi-carrier applications | |
| Wang et al. | A 3.8 mW sub-sampling direct RF-to-digital converter for polar receiver achieving 1.94 Gb/s data rate with 1024-APSK modulation | |
| Shao et al. | Design and Implementation of a Four-Channel Broadband High-Speed RF Receiver for 5G Communication System | |
| CN116112011B (en) | SYSREF-free distributed clock architecture for software-definable SOC chip | |
| Wang et al. | Broadband High-SFDR Digital-IF Module for 5G Millimeter-wave Transmitters |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |