CN115865017A - High-precision low-noise low-power consumption programmable gain amplifier applied to audio system - Google Patents

Abstract

The invention discloses a high-precision low-noise low-power consumption programmable gain amplifier applied to an audio system, which comprises two high-precision low-noise controllable power consumption single-ended output operational amplifiers, an adjustable resistor array, a low-frequency anti-aliasing filter and a digital control module. After an external preset working mode, generating a system internal control logic signal through a digital control module, and inputting the system internal control logic signal into an operational amplifier to adjust the current of an operational amplifier output stage; after the amplification factor is preset outside, a system internal control logic signal is generated through a digital control module and input into an adjustable resistor array to adjust the resistance ratio between different nodes, the signal is amplified to a target gain in cooperation with a high-precision low-noise low-power-consumption single-ended output operational amplifier, and the signal is filtered by a low-frequency anti-aliasing filter and then output. The invention has the advantages of high precision, low noise, low power consumption, real-time amplification factor change and the like.

Description

High-precision low-noise low-power consumption programmable gain amplifier applied to audio system

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-precision low-noise low-power consumption programmable gain amplifier applied to an audio system.

Background

For integrated circuit systems, analog front-end circuits are very important building blocks in order to achieve interaction between the real world and smart devices. In the real world, there are various continuous analog signals such as sound, temperature, light signal, voltage, various pressures, etc.; although humans can directly perceive these analog signals, it is difficult for smart devices to be directly processed. Therefore, there is a need to convert a continuous analog signal into a discrete digital signal that can be recognized and processed by a smart device through a certain means.

In the actual use process, the acceleration sensors with different structures are required to be selected for designing aiming at different application scenes, so that in order to increase certain universality, the same type of sampling chip can be applied to more sensor structures, the adjustable gain function is required to be added at the front end of the simulation, and the acceleration sensors with different sensitivities and bandwidths are met.

The programmable gain amplifier is one of the core components in the analog front-end module, and can amplify signals to different multiples by manual selection according to the size of input signals, so that the dynamic range of the system is improved.

With the development and maturity of technology, the most important development trend of integrated circuits is integration and miniaturization, as an important module of a signal system, the performance of a programmable gain amplifier has an important influence on the system, and the integration of the programmable gain amplifier into a system chip is a mainstream development trend. An audio system has two characteristics of relatively small input signal frequency to be processed and high requirement on signal processing performance, so that a programmable gain amplifier with high precision, low noise and low power consumption is indispensable.

Chinese patent publication No. CN112968684A proposes a wideband programmable gain amplifier based on transconductance switching technology, which implements amplification of different gains by changing transconductance of MOS transistors of an operational amplifier input stage, and the technology is limited by manufacturing process variations and mismatch between MOS transistors, cannot implement very precise expected amplification, and is a relatively coarse programmable gain amplifier. Chinese patent publication No. CN113328711A proposes a constant transconductance full-swing input programmable gain amplifier, which achieves high precision performance by adjusting the proportional relationship of load resistors, but does not process system noise, which results in that the output signal is greatly influenced by noise.

Therefore, in the prior art, high-precision processing is mainly performed, a small part of the prior art refers to realization of low noise, and a programmable gain amplifier which can achieve ultrahigh precision and low noise is lacked; the input stage or the gain stage is usually redesigned only for high-precision processing, and no scheme design for realizing ultra-high-precision dB linear characteristic is realized by the combined design of the input stage and the gain stage.

Disclosure of Invention

In view of the above, the present invention provides a high-precision low-noise low-power consumption programmable gain amplifier applied to an audio system, which provides high and low frequency gains by using a novel high transconductance input stage and a gain stage with an auxiliary operational amplifier, so as to achieve high precision in the signal amplification process, and simultaneously, the CHOP of the CHOP switch is multiplexed to shift and filter the frequency spectrum of the low-frequency noise part of the circuit, so as to achieve the purpose of low-noise amplification.

A high-precision low-noise low-power consumption programmable gain amplifier applied to an audio system comprises two single-ended OUTPUT operational amplifiers A1 and A2, an adjustable resistor array, a digital control module and a low-frequency anti-aliasing filter, wherein the in-phase INPUT ends of the A1 and the A2 are respectively connected with differential INPUT signals INPUT _ A and INPUT _ B, the anti-phase INPUT ends of the A1 and the A2 are connected with the adjustable resistor array, the OUTPUT ends of the A1 and the A2 are connected with the adjustable resistor array and the low-frequency anti-aliasing filter, and the amplified INPUT _ A and INPUT _ B are finally filtered by the low-frequency anti-aliasing filter to obtain differential OUTPUT signals OUTPUT _ A and OUTPUT _ B;

the digital control module receives an externally input clock signal, so that a pair of reciprocal clock signals are generated and provided for A1 and A2; meanwhile, the digital control module receives an externally input enable signal for controlling the current of the operational amplifier output stage, so that two pairs of mutually inverted enable signals are generated and supplied to A1 and A2; in addition, the digital control module also receives an externally input digital logic signal for controlling the amplification factor, so that six pairs of reciprocal digital logic signals are generated and transmitted to the adjustable resistor array;

the adjustable resistor array enables the gain amplifier to achieve multiple amplification factors by changing the proportional relation of the operational amplifier load resistors.

Further, the adjustable resistor array comprises six high linear double-throw switches SW 1-SW 6 and six pairs of resistors R1a and R1B, R2a and R2B, R3a and R3B, R4a and R4B, R5a and R5B, and R6a and R6B, the two resistors of each pair have the same resistance value, wherein one end of R6a is connected with VOUTa end of SW6 and is used as PORT _ A PORT of the adjustable resistor array, the other end of R6a is connected with one end of R5a and VOUTa end of SW5, the other end of R5a is connected with one end of R4a and VOUTa end of SW4, the other end of R4a is connected with one end of R3a and VOUTa end of SW3, the other end of R3a is connected with one end of R2a and VOUTa end of SW2, the other end of R2a is connected with one end of R1a and VOUTa end of SW1, the other end of R1a is connected with one end of SW 1B, the other end of R1B is connected with one end of R2B and VOUTb end of SW1, the other end of R2B is connected with one end of R3B and VOUTb end of SW2, the other end of R3B is connected with one end of R4B and VOUTb end of SW3, the other end of R4B is connected with one end of R5B and VOUTb end of SW4, the other end of R5B is connected with one end of R6B and VOUTb end of SW5, the other end of R6B is connected with VOUTb end of SW6 and used as PORT _ B PORT of adjustable resistor array, the VINA ends of SW 1-SW 6 are connected together and used as PORT _ C PORT of adjustable resistor array, the VINB ends of SW 1-SW 6 are connected together and used as PORT _ D PORT of adjustable resistor array, the disconnection of SW 1-SW 6 is controlled by six pairs of digital logic signals provided by digital control module;

the PORT _ A PORT of the adjustable resistor array is connected with the output end of A1, the PORT _ B PORT is connected with the output end of A2, the PORT _ C PORT is connected with the inverting input end of A1, and the PORT _ D PORT is connected with the inverting input end of A2.

Further, the high linear double throw switches SW1 to SW6 have the same structure and include 8 PMOS transistors P1a, P2a, P3a, P4a, P1b, P2b, P3b, P4b and 8 NMOS transistors P5a, P6a, P7a, P8a, P5b, P6b, P7b, P8b, wherein the source of P1a is connected to the source of P1b and connected to the supply voltage VDD, the gate of P1a is connected to the gate of P8a, the gate of P7a, the gate of P6a, the gate of P1b is connected to the gate of P8b, the gate of P7b and the gate of P6b and connected to RS +, the gate of P2a is connected to the gate of P2b, the gate of P3a, the gate of P3b, the gate of P4a, the gate of P4b, the gate of P5a and the gate of P5b are connected to the drain of P1a + and the drain of P2a, the drain of P8a is connected to the source of P2a, the substrate of P3b, the drain of P2b and the drain of P2b, the source of P8a is connected with the drain of P2a, the drain of P7a and the source of P3a and serves as a VINA end of the double-throw switch, the source of P8b is connected with the drain of P2b, the drain of P7b and the source of P3b and serves as a VINB end of the double-throw switch, the source of P7a is connected with the drain of P3a, the drain of P6a and the source of P4a and serves as a VOUTa end of the double-throw switch, the source of P7b is connected with the drain of P3b, the drain of P6b and the source of P4b and serves as a VOUTb end of the double-throw switch, the source of P6a is connected with the drain of P4a, the drain of P5a and the substrate of P7a, the source of P6b is connected with the drain of P4b, the drain of P5b and the substrate of P7b, the source of P5a is connected with the source of P5b in parallel with a power ground, and RS + and RS-VSS provide a pair of digital control signals for the digital control module.

Further, the operational amplifiers A1 and A2 have the same structure, and are formed by sequentially connecting a high transconductance input stage, a gain amplification stage, and a Class-AB adjustable current output stage, wherein:

the high transconductance input stage improves the transconductance of the operational amplifier input stage, improves the low-frequency gain of the operational amplifier as a whole and improves the unit gain bandwidth of the extended operational amplifier as a whole by carrying out proportional splitting and cross coupling on the input geminate transistors and NMOS tail current transistors in the folded cascode structure, thereby realizing the high precision of the gain amplifier and meeting the frequency range capable of processing input signals;

the gain amplification stage provides gain amplification for input signals through a folded cascode structure with an auxiliary operational amplifier, wherein a CHOP switch is used as a secondary spectrum shifting switch of the operational amplifier and is also used as a primary spectrum shifting switch of the auxiliary operational amplifier, so that a multiplexing function is realized;

the Class-AB adjustable current output stage realizes the control of the current of the operational amplifier output stage through the floating gate voltage feedforward control and the switch structure, and realizes the controllable power consumption of the operational amplifier.

Further, the high transconductance input stage includes a CHOP switch CHOPPER _ B, five PMOS transistors M0, M1a, M1B, M2a, M2B and four NMOS transistors M3a, M3B, M4a, M4B, wherein input ports IN _ a and IN _ B of CHOPPER _ B are respectively a non-inverting input terminal and an inverting input terminal of the operational amplifier, an output port OUT _ a of CHOPPER _ B is connected to the gate of M1a and the gate of M1B, an output port OUT _ B of CHOPPER _ B is connected to the gate of M2a and the gate of M2B, the source of M0 is connected to a power supply voltage VDD, the gate of M0 is connected to a fixed bias voltage VBP3, the drain of M0 is connected to the source of M1a, the source of M1B, the source of M2a and the source of M2B, the drain of M1a is connected to the drain of M3a and the non-inverting output terminal of the high transconductance input stage, the drain of M2a is connected to VSS, the drain of M4a is connected to the drain of M3a, the transconductance input stage, the drain of M4B is connected to the drain of M3B, and the drain of the transconductance input stage, the drain of M4B, the transconductance input stage, the drain of M4B is connected to the transconductance input stage, and the drain of M4B, the input stage, the transconductance input stage, the drain of M4B is connected to the transconductance switch.

Further, the gain amplifying stage comprises two auxiliary operational amplifiers GBP and GBN, two CHOPPER _ P and CHOPPER _ N, four PMOS transistors M7-M10 and two NMOS transistors M5 and M6, wherein the source of M9 is connected to the source of M10 and to the supply voltage VDD, the gate of M9 is connected to the gate of M10, the drain of M7 and the drain of M5, the drain of M9 is connected to the non-inverting input terminal of GBN and the input port IN _ A of CHOPPER _ P, the drain of M10 is connected to the inverting input terminal of GBN and the input port IN _ B of CHOPPER _ P, the output port OUT _ A of CHOPPER _ P is connected to the source of M7, the output port OUT _ B of CHOPPER _ P is connected to the source of M8, the non-inverting output terminal of GBN is connected with the grid of M7, the inverting output terminal of GBN is connected with the grid of M8, the drain of M8 is connected with the drain of M6, the source of M5 is connected with the input port IN _ A of CHOPPER _ N, the source of M6 is connected with the input port IN _ B of CHOPPER _ N, the non-inverting input terminal of GBP is connected with the output port OUT _ A of CHOPPER _ N and the non-inverting output terminal of the high transconductance input stage, the inverting input terminal of GBP is connected with the output port OUT _ B of CHOPPER _ N and the inverting output terminal of the high transconductance input stage, the non-inverting output terminal of GBP is connected with the grid of M5, and the inverting output terminal of GBP is connected with the grid of M6.

Further, the auxiliary operational amplifier GBP comprises eight PMOS tubes PM0, PM1, PM2, PM3, PM8, PM9, PM10, and PM11, four NMOS tubes PM4, PM5, PM6, and PM7, and two CHOP switches CHOPPER _ P1 and CHOPPER _ N1, wherein the source of PM0 is connected to the source of PM10, the source of PM11, and the source of PM1 and is connected to the supply voltage VDD, the gate of PM0 is connected to the gate of PM1 and is connected to the fixed bias voltage VBP3, the drain of PM0 is connected to the source of PM2, the drain of PM1 is connected to the source of PM3, the gate of PM2 and the gate of PM3 serve as a non-inverting input terminal and an non-inverting input terminal of the auxiliary operational amplifier GBP, the gate of PM10 is connected to the gate of PM11 and is connected to the fixed bias voltage VBP1, the drain of PM10 is connected to the input port _ A of CHOPPER _ P1, the drain of PM11 is connected to the input port B _ B of the auxiliary operational amplifier GBP 1, and the source of the output port of PM8 is connected to the CHOPPER _ P _ OUT, the source of PM9 is connected to output port OUT _ B of CHOPPER _ P1, the gate of PM8 is connected to the gate of PM9 and holds the bias voltage VBP2, the drain of PM8 is connected to the drain of PM6 and serves as the non-inverting output terminal of the auxiliary operational amplifier GBP, the drain of PM9 is connected to the drain of PM7 and serves as the inverting output terminal of the auxiliary operational amplifier GBP, the gate of PM6 is connected to the gate of PM7 and holds the bias voltage VBN2, the source of PM6 is connected to input port IN _ A of CHOPPER _ N1, the source of PM7 is connected to input port IN _ B of CHOPPER _ N1, the drain of PM2 is connected to the drain of PM4 and output port OUT _ A of CHOPPER _ N1, the drain of PM3 is connected to the drain of PM5 and output port OUT _ B of CHOPPER _ N1, the gate of PM4 is connected to the gate of PM5 and holds the bias voltage VBN1, and the source of PM4 is connected to the source of PM5 and holds the power supply VSS.

Further, the auxiliary operational amplifier GBN includes eight NMOS transistors NM0, NM1, NM2, NM3, NM4, NM5, NM6 and NM7, four PMOS transistors NM8, NM9, NM10, NM11, and two CHOPPER _ P2 and CHOPPER _ N2 switches, wherein a source of NM0 is connected to a source of NM1, a source of NM4, and a source of NM5 and connected to a ground VSS, a gate of NM0 is connected to a gate of NM1 and connected to a fixed bias voltage VBN3, a drain of NM0 is connected to a source of NM2, a drain of NM1 is connected to a source of NM3, a gate of NM2 and a gate of NM3 respectively serve as a non-inverting input terminal and an inverting input terminal of the auxiliary operational amplifier GBN, a gate of NM4 is connected to a gate of NM5 and connected to a fixed bias voltage VBN1, a drain of NM5 is connected to an output port OUT _ A of CHOPPER 2, a source of the auxiliary operational amplifier GBN 7 is connected to an input port of CHOPPER _ A, the source of NM6 is connected to the input port IN _ B of CHOPPER _ N2, the gate of NM6 is connected to the gate of NM7 and connected to a fixed bias voltage VBN2, the drain of NM7 is connected to the drain of NM9 and serves as the non-inverting output terminal of the auxiliary operational amplifier GBN, the drain of NM6 is connected to the drain of NM8 and serves as the inverting output terminal of the auxiliary operational amplifier GBN, the gate of NM8 is connected to the gate of NM9 and connected to a fixed bias voltage VBP2, the source of NM9 is connected to the output port OUT _ a of CHOPPER _ P2, the source of NM8 is connected to the output port OUT _ B of CHOPPER _ P2, the drain of NM11 is connected to the drain of NM2 and the input port IN _ a of CHOPPER _ P2, the drain of NM10 is connected to the drain of NM3 and the input port IN _ B of CHOPPER _ P2, the gate of NM10 is connected to the gate of NM11 and connected to a fixed bias voltage VBP1, the source of NM11 and connected to the power supply voltage VDD.

Furthermore, the CHOP switches CHOPPER _ B, CHOPPER _ P, CHOPPER _ N, CHOPPER _ P1, CHOPPER _ P2, CHOPPER _ N1, and CHOPPER _ N2 have the same structure, and include four switch modules K1 to K4, where the input end of K1 is connected to the input end of K2 and serves as the input port IN _ a of the CHOP switch, the output end of K1 is connected to the output end of K3 and serves as the output port OUT _ a of the CHOP switch, the input end of K3 is connected to the input end of K4 and serves as the input port IN _ B of the CHOP switch, and the output end of K2 is connected to the output end of K4 and serves as the output port OUT _ B of the CHOP switch; the switch modules K1-K4 in the CHOPPER _ P, CHOPPER _ P1 and CHOPPER _ P2 adopt PMOS tubes, the switch modules K1-K4 in the CHOPPER _ N, CHOPPER _ N1 and CHOPPER _ N2 adopt NMOS tubes, and the switch modules K1-K4 in the CHOPPER _ B adopt Bootstrap switches.

Further, the Bootstrap switch comprises a capacitor C1, four PMOS tubes SM1, SM2, SM3, SM6 and seven NMOS tubes SM4, SM5, SM7, SM8, SM9, SM10, SM11, wherein the drain electrode of SM1 is connected with the source electrode of SM6, the gate electrode of SM4 and the source electrode of SM2 and is connected with the power supply voltage VDD, the gate electrode of SM1 is connected with the drain electrode of SM3, the drain electrode of SM4, the gate electrode of SM8, the gate electrode of SM9 and the gate electrode of SM10, the source electrode of SM1 is connected with one end of C1 and the source electrode of SM3, the other end of C1 is connected with the drain electrode of SM11, the source electrode of SM7, the source electrode of SM8 and the drain electrode of SM9, the source electrode of the SM11 is connected with a power ground VSS, the grid electrode of the SM11 is connected with the CLK1, the grid electrode of the SM6 is connected with the grid electrode of the SM7 and connected with the CLK2 in parallel, the drain electrode of the SM6 is connected with the drain electrode of the SM7, the grid electrode of the SM3 and the drain electrode of the SM8, the drain electrode of the SM2 is connected with the source electrode of the SM4 and the drain electrode of the SM5, the grid electrode of the SM2 is connected with the grid electrode of the SM5 and connected with the CLK1 in parallel, the source electrode of the SM5 is connected with the VSS, the source electrode of the SM9 is connected with the drain electrode of the SM10 and serves as the input end of the switch module, the source electrode of the SM10 serves as the output end of the switch module, and the CLK1 and the CLK2 provide a pair of clock signals which are opposite to each other for the digital control module.

Based on the technical scheme, the invention has the following beneficial technical effects:

1. the invention adopts differential input and differential output, and can realize larger input and output swing amplitude.

2. The invention can provide extremely high low-frequency gain, so that the system has high precision when amplifying signals.

3. The invention can filter the low-frequency noise, so that the system noise is extremely low and a high signal-to-noise ratio output signal is provided.

4. The invention can provide controllable output current, thereby providing optional driving capability, directly providing output signals to the back-end circuit module and effectively controlling the overall power consumption of the system.

5. The invention can be applied to the amplification of audio signals, provides low harmonic distortion and keeps the signal performance.

Drawings

Fig. 1 is a schematic structural diagram of a high-precision low-noise low-power consumption programmable gain amplifier according to the present invention.

Fig. 2 is a schematic structural diagram of an adjustable resistor array.

Fig. 3 is a schematic diagram of a double throw switch.

Fig. 4 is a schematic structural diagram of the digital control module.

FIG. 5 is a schematic diagram of an operational amplifier according to the present invention.

Fig. 6 is a schematic structural diagram of the novel high transconductance input stage and the gain amplifier stage according to the present invention.

Fig. 7 is a schematic structural diagram of an auxiliary operational amplifier GBP.

Fig. 8 is a schematic structural diagram of an auxiliary operational amplifier GBN.

Fig. 9 is a schematic diagram of the CHOP switch.

Fig. 10 is a schematic structural diagram of the novel gate voltage bootstrapped switch boottrap.

Fig. 11 (a) is a schematic diagram of a simulation waveform of an operational amplifier using a novel high transconductance input gain stage according to the present invention.

Fig. 11 (b) is a schematic diagram showing the noise comparison before and after chopping using the multiplexed CHOP switch.

Detailed Description

In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and the specific embodiments.

As shown in fig. 1, the high-precision low-noise low-power consumption programmable gain amplifier applied to differential INPUT and differential output of an audio processing system of the present invention includes an adjustable resistor array including 6 pairs of resistors R1 to R6 with different resistance values and a plurality of switches, two single-ended output operational amplifiers A1 and A2, a digital control module, and a low-frequency anti-aliasing filter, wherein the in-phase INPUT terminals of A1 and A2 are connected to differential INPUT signals INPUT _ a and INPUT _ B; the output end of A1 is connected with one end of PORT _ A in the adjustable resistor array, the inverting input end of A1 is connected with one end of PORT _ C in the adjustable resistor array, the output end of A2 is connected with one end of PORT _ B in the adjustable resistor array, and the inverting input end of A2 is connected with one end of PORT _ D in the adjustable resistor array; the digital control module receives a CLOCK signal CLOCK input from the outside, generates a pair of CLK (CLK 1, CLK 2) signals which are opposite to each other and transmits the signals to the operational amplifier, receives two ENABLE signals ENABLE _ A and ENABLE _ B which are input from the outside and control the current of an output stage of the operational amplifier, generates two pairs of ENABLE signals ENA and ENB which are opposite to each other and transmits the ENABLE signals ENA and ENB to the operational amplifier, and receives three digital logic signals which are input from the outside and control the amplification factors, generates a group of digital logic signals GAIN _ CTRL which comprise six pairs of opposite to each other and transmits the digital logic signals GAIN _ CTRL to the adjustable resistor array; a1 and A2 OUTPUT amplified differential signals are transmitted to two input ends VIN1 and VIN2 of an anti-aliasing filter, and differential OUTPUT signals OUTPUT _ A and OUTPUT _ B of a system are OUTPUT through two OUTPUT ends VOUT1 and VOUT2 after filtering processing is carried out; VDD and VSS provide power and ground for the entire system.

As shown in fig. 2, the adjustable resistor array is formed by connecting six sets of circuit units of switches and resistors in series, each circuit unit is composed of a high linearity double throw switch SW and a pair of resistors with the same resistance value, a VOUT end of the switch is connected with one end of the resistor, a VIN end of the switch is connected with a VIN end of another circuit unit, and the other end of the resistor is connected with the resistor of the other circuit unit and the VOUT end of the switch. The double-throw switch is set to have two states of being simultaneously turned on or simultaneously turned off, and the proportional relation of the six pairs of resistance values of R1-R6 is 1.

As shown in fig. 3, the high linearity double throw switch SW includes two groups of MOS switches with symmetrical structures, each group of switches includes 8 MOS transistors M1 to M8, wherein the substrate voltages of the MOS transistors except M3 and M7 are connected to VDD by PMOS transistor, and the NMOS transistor is grounded; the source of M1 is connected with a power voltage VDD, the drain of M1 is connected with the source of M2, the drain of M8 and the substrate of M3, the gate of M1 is connected with the gate of M8, the gate of M7 and the gate of M6 and is connected with a switching signal RS-, the gate of M2 is connected with the gate of M3, the gate of M4 and the gate of M5 and is connected with a switching signal RS +, the drain of M2 is connected with the source of M8, the source of M3 and the drain of M7 and is connected with an input signal VIN, the drain of M3 is connected with the source of M7, the drain of M6 and the source of M4 and is connected with an output signal VOUT, the drain of M5 is connected with the source of M6, the drain of M4 and the substrate of M7, and the source of M5 is grounded. M1-M4 are PMOS tubes, and M5-M8 are NMOS tubes.

As shown in fig. 4, the digital control module is composed of eighteen not gates, six three-input and gates and a delay module, the externally input CLOCK signal passes through one not gate and one delay module to obtain a CLK2 signal, and passes through two not gates to obtain a CLK1 signal; an ENEN signal is obtained by an ENABLE-A signal input from the outside through a NOT gate, and an ENAP signal is obtained by two NOT gates; an ENBN signal is obtained by an ENABLE _ B signal input from the outside through a NOT gate, and an ENBP signal is obtained through two NOT gates; the externally input GAIN _ CTRL _ A, GAIN _ CTRL _ B and GAIN _ CTRL _ C signals pass through a three-line six-line decoder consisting of six NOT gates and six three-input AND gates to obtain six signals of RS6+, RS5+, RS4+, RS3+, RS2+ and RS1+, and then pass through the six NOT gates to generate six signals of RS6-, RS5-, RS4-, RS3-, RS 2-and RS 1-respectively, and the six pairs of inverted GAIN _ CTRL signals are respectively connected to corresponding control ends of six switches in the adjustable resistor array.

As shown in fig. 5, the operational amplifiers A1 and A2 include:

the novel high transconductance input stage improves the transconductance of the operational amplifier input stage by carrying out proportional splitting and cross coupling on an input geminate transistor and an NMOS tail current tube in a folded cascode structure, thereby improving the integral low-frequency gain of the operational amplifier and extending the integral unit gain bandwidth of the operational amplifier, realizing the high precision of the amplifier and meeting the frequency range capable of processing input signals.

The gain amplification stage provides gain amplification for input signals through a folded cascode structure with an auxiliary operational amplifier, wherein the CHOP switch is used as a secondary frequency spectrum moving switch of the operational amplifier and is also used as a primary frequency spectrum moving switch of the auxiliary operational amplifier, thereby realizing a multiplexing function, saving circuit area and improving transient performance of a circuit.

The Class-AB adjustable current output stage realizes the control of the magnitude of the quiescent current of the circuit output stage through the floating gate voltage feedforward control and the switch structure, and realizes the controllable power consumption of the operational amplifier.

As shown in fig. 6, the novel high transconductance input stage and gain amplifier stage includes 15 MOS transistors M0-M10, 2 auxiliary operational amplifiers and 3 CHOP switches, wherein the source of M0 is connected to the power voltage VDD, the gate of M0 is connected to a fixed bias VBP3 as a fixed current source, the drain of M0 is connected to the sources of M1a, M1B, M2a, M2B, the input signals VIN _ a and VIN _ B are respectively connected to the gates of M1a and M1B and the gates of M2a and M2B through a CHOP switch, the sources of M9 and M10 are connected to the power voltage VDD, the gates of M9 and M10 are connected to the drain of M7 and the drain of M5, the drain of M9 and the drain of M10 are respectively connected to the source of M7 and the source of M8 through a CHOP switch, the auxiliary operational amplifier GBN input end is connected with an M9 drain electrode and an M10 drain electrode respectively, the auxiliary operational amplifier GBN output end is connected with an M7 grid electrode and an M8 grid electrode respectively, the M8 drain electrode is connected with an M6 drain electrode, the M5 source electrode and the M6 source electrode are connected with an M3a drain electrode and an M4a drain electrode respectively through a CHOP switch, the M3a source electrode M3B source electrode M4a source electrode M4B source electrode is connected with ground VSS, the M1a drain electrode is connected with an M3a drain electrode, the M1B drain electrode is connected with an M4B drain electrode, the M2a drain electrode is connected with an M4a drain electrode, the M2B drain electrode is connected with an M3B drain electrode, the M3a grid electrode and the M3B drain electrode are connected with an M4B drain electrode, the auxiliary operational amplifier GBP input end is connected with an M3a drain electrode and an M4a drain electrode respectively, and the auxiliary operational amplifier GBP output end is connected with an M5 grid electrode and an M6 grid electrode respectively.

As shown in FIG. 7, the GBP comprises 12 MOS transistors PM 0-PM 11 and two CHOP switches, wherein the sources of PM0 and PM1 are connected to a power supply voltage VDD, the gates of PM0 and PM1 are connected to a fixed bias VBP3, the drain of PM0 is connected to the source of PM2, the drain of PM1 is connected to the source of PM3, the gates of PM2 and PM3 are respectively used as the input terminals of the GBP, the sources of PM10 and PM11 are connected to the power supply voltage VDD, the gates of PM10 and PM11 are connected to a fixed bias VBP1, the drains of PM10 and PM11 are respectively connected to the source of PM8 and the source of PM9 through one CHOP switch, the gates of PM8 and PM9 are connected to a fixed bias VBP2, the drains of PM8 and PM6 are connected to the drain of PM6 and are used as the output terminals of GBP, the drains of PM9 and PM7 are connected to another output terminal of GBP, the gates of PM6 and PM7 are connected to a fixed bias VBN2, the sources of PM6 and the sources of PM7 are respectively connected to the drain of PM4 and PM5 through one CHOP switch, the drain of PM4 is connected to the ground, the drain of PM4 and the PM3 is connected to the drain of PM 5.

As shown in fig. 8, the auxiliary operational amplifier GBN includes 12 MOS transistors NM0 to NM11 and two CHOP switches, where NM0 and NM1 sources are connected to ground VSS, NM0 and NM1 gates are connected to a fixed bias VBN3, NM0 drain is connected to NM2 source, NM1 drain is connected to NM3 source, NM2 and NM3 gates are respectively used as input terminals of GBN, NM10 and NM11 sources are connected to a power supply voltage VDD, NM10 and NM11 gates are connected to a fixed bias VBP1, NM10 and NM11 drains are respectively connected to NM8 source NPM9 source through a CHOP switch, NM8 and NM9 gates are connected to a fixed bias VBP2, NM8 drain and NM6 drain are connected to a fixed bias VBN output terminal, NM9 drain and NM7 drain are connected to a GBN other output terminal, NM6 and NM7 gates are connected to a fixed bias VBN2, NM6 source and NM7 source are connected to a fixed bias VBN 4 drain and NM5 drain through a CHOP switch, NM4 and NM5 sources are connected to ground, NM2 drain is connected to NM3 drain, and drain is connected to ground.

As shown IN fig. 9, the CHOP switch includes four switch modules K1 to K4, where the left end of K1 and the left end of K2 are connected to IN _ a, the left end of K3 and the left end of K4 are connected to IN _ B, the right end of K1 and the right end of K3 are connected to OUT _ a, and the right end of K2 and the right end of K4 are connected to OUT _ B. Three kinds of CHOP switches are CHOP _ P, CHOP _ N and CHOP _ Bootstrap respectively, wherein CHOP _ P is to replace a switch module by a simple PMOS transistor, CHOP _ N is to replace the switch module by a simple NMOS transistor, and CHOP _ Bootstrap is to use a Bootstrap switch as the switch module.

As shown IN fig. 10, the boottrap switch includes 11 MOS transistors SM1 to SM11 and a capacitor C1, where an SM1 drain, an SM2 source, an SM4 gate and an SM6 source are connected to a power supply voltage, an SM1 gate, an SM3 drain, an SM4 drain, an SM8 gate, an SM9 gate and an SM10 gate are connected, an SM2 drain, an SM4 source and an SM5 drain are connected, an SM2 gate and an SM5 gate are connected to CLK1, an SM5 source is connected to ground, an SM1 source, an SM3 source and a C1 upper plate are connected, an SM6 gate and an SM7 gate are connected to CLK2, an SM6 drain, an SM7 drain, an SM3 gate and an SM8 drain are connected, an SM7 source, an SM8 source, an SM9 drain, a C1 lower plate and an SM11 drain are connected, an SM11 gate is connected to CLK1, an SM11 source is connected to ground, an SM9 source and an SM10 drain are connected to a switch input terminal IN, and an SM10 source is used as a switch output OUT. SM1, SM2, SM3, SM6 are PMOS pipes, and SM4, SM5, SM7, SM8, SM9, SM10, SM11 are NMOS pipes.

As shown in FIG. 5, the Class-AB adjustable current OUTPUT stage comprises 16 MOS transistors M11-M26, two capacitors C1, C2 and two resistors R1, R2, wherein M11 and M12 gates are connected to a fixed bias VBP _ AB, M13 and M14 gates are connected to a fixed bias VBN _ AB, M11 source is connected to M13 drain, M11 drain is connected to M13 source, a small circuit unit composed of M11 and M13 is integrally inserted between input gain stages M7 and M5, M12 source is connected to M14 drain, M12 drain is connected to M14 source, a small circuit unit composed of M12 and M14 is integrally inserted between input gain stages M8 and M6, M12 source is connected to C1 upper stage plate, M15 gate and M16 gate, M14 source is connected to C2 upper stage plate, M17 gate and M18 gate, the lower plate of C1 is connected with one end of R1, the lower plate of C2 is connected with one end of R2, the source of M15 and the source of M16 are connected with a power supply voltage VDD, the drain of M15 is connected with the source of M19 and the drain of M20, the drain of M16 is connected with the source of M21 and the drain of M22, the source of M17 and the source of M18 are connected with the ground, the drain of M17 is connected with the drain of M23 and the source of M24, the drain of M18 is connected with the drain of M25 and the source of M26, the drain of M19, the source of M20, the drain of M21, the source of M22, the source of M18 are connected with the ground, the drain of M18 is connected with the drain of M23 and the source of M26, the drain of M19, the source of M20, the drain of M21, the source of M26, the other end of R1 is connected with the OUTPUT end of the operational amplifier, the gates of M19 and M23 are connected with ENUP, the gates are connected with the gates of ENBP.

The high-precision low-noise low-power consumption programmable gain amplifier applied to the differential input and differential output of the audio processing system adopts a double-operational amplifier instrument amplifier structure, and the change of the amplification factor is realized through an adjustable resistor array; the operational amplifier adopts a novel high transconductance input stage structure, and simultaneously adds an auxiliary operational amplifier and a CHOP switch on a circuit by using a gain improvement technology and a multiplexing CHOP switch chopping technology so that the system meets the requirements of high precision and low noise; the operational amplifier output stage adopts a floating grid voltage control Class-AB technology and an output current selection technology, so that large swing of output voltage can be realized, and the power consumption of a system is controlled.

The amplification factor of the system is determined by changing the resistance ratio among different nodes in the adjustable resistor array, four nodes PORT _ A, PORT _ B, PORT _ C and PORT _ D exist in the adjustable resistor array, only one of the six double-throw switches is conducted under each amplification factor, the resistance value of the resistance between PORT _ A and PORT _ B is determined and constant, and all the resistance values are all constantThe sum of the resistance values is recorded as R _tot After one double-throw switch is turned on, a path exists between PORT _ C and PORT _ D, the resistance value of the resistor on the path can be changed along with the turn-on of different switches, and the sum of the resistance values of the resistor is recorded as R _gain The system magnification thus determined is:

because PORT _ C and PORT _ D are respectively connected with the inverting input end of the operational amplifier to be extracted from the adjustable resistor array, the switch does not exist on the output end connecting branch of the two operational amplifiers A1 and A2, and therefore the change of the on-resistance of the switch along with the voltage does not influence the amplification factor and the amplification precision of the system.

The external input three logic signals GAIN _ CTRL _ A, GAIN _ CTRL _ B and GAIN _ CTRL _ C for controlling the amplification factor are coded by the digital control module to form GAIN _ CTRL signals for controlling the on-off of the switches in the adjustable resistance module, the control switches have high linearity, when all the transmission gates are switched off, the upper and lower current sources are switched on, so that a PMOS tube substrate of the transmission gate positioned in the middle and connected with the input and output is connected to a power supply voltage VDD, an NMOS tube substrate is connected to the ground, when all the transmission gates are switched on, the upper and lower current sources are switched off, so that the PMOS tube substrate of the transmission gate positioned in the middle and connected with the input and output is connected to the source electrode of the PMOS tube substrate, and the NMOS tube substrate is also connected to the source electrode of the NMOS tube substrate. Therefore, the influence of the MOS body effect on the on-resistance and nonlinearity of the switch can be reduced.

The input gain stage of the operational amplifier is a novel high transconductance input gain stage structure with an auxiliary operational amplifier for gain boosting and a CHOP switch for filtering. The sizes of four MOS tubes M1a, M1b, M2a and M2b are kept consistent, the current I passing through M0 is divided into four parts, the current going downwards from M9 and M10 is I/2, the size proportion of two groups of MOS tubes M3a, M3b, M4a and M4b is 2, the two groups of MOS tubes are in a current mirror copy structure, the current going downwards from M3a and M4b is I/4, the current going downwards from M3a and M3b is just the sum of the current going downwards from M1a and the current of an M9 branch, and M4a is the same as M4a in principle. The low-frequency gain and the unit gain bandwidth of the gain stage can be improved by designing the gain stage in such a way, and the cost is slightly reduced by the phase margin. The auxiliary operational amplifier is added, the output impedance seen by an output node of the input gain stage is improved, gain improvement is further carried out, and the low-frequency gain can be improved under the condition that the unit gain bandwidth of the original structure is not changed by reasonably setting the unit gain bandwidth of the auxiliary operational amplifier. CHOP _ P and CHOP _ N in the input gain stage are both CHOP switches placed in the folded cascode configuration among the input gain stages, and CHOP switches placed before the input pair transistors among the auxiliary operational amplifiers GBP and GBN. The CHOP switch can carry out spectrum shifting on the low-frequency noise of the circuit, and then filtering is carried out through a low-frequency anti-aliasing filter, so that the low noise is realized. The auxiliary operational amplifier adopts a completely symmetrical circuit structure to ensure the matching of the whole circuit. The novel high transconductance input stage clamps drain voltage and grid voltage of M3 and M4 through the current of four branches, and helps the auxiliary operational amplifier to finish self-adaptive bias without additionally providing bias voltage.

The operational amplifier output stage floating control grid voltage Class-AB technology meets the requirement that grid voltages of output MOS (metal oxide semiconductor) tubes M15-M18 are changed consistently when M10 branch current is slightly changed under a small signal, and controls the magnitude of output stage current through four switches formed by M19-M26 so as to control the power consumption of a system. The magnitude of the output stage current is mainly determined according to the driving capability required by the load, and the on and off of the switch are generated by enabling signals ENABLE _ A and ENABLE _ B fed from the outside through coding of the digital control module.

Fig. 11 (a) is an ac simulation result of the operational amplifier module of the programmable operational amplifier, where the low-frequency gain of the operational amplifier can reach 175dB, the unit gain bandwidth can reach 47MHz, and the corresponding phase margin is 64Deg, so as to ensure that the operational amplifier can achieve high-precision performance meeting the requirement, process the maximum allowable input signal frequency, and ensure the loop stability. FIG. 11 (b) is a comparison of noise simulation of whether the programmable op-amp uses the switched-multiplexed chopping technique, with the abscissa being the frequency and the corresponding ordinate being the power level of the noise at that frequency; the results show very directly that the low frequency noise part of the programmable gain amplifier is greatly suppressed after the switched-multiplexed chopping technique is used.

The foregoing description of the embodiments is provided to enable one of ordinary skill in the art to make and use the invention, and it is to be understood that other modifications of the embodiments, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty, as will be readily apparent to those skilled in the art. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.

Claims (10)

1. A high-precision low-noise low-power consumption programmable gain amplifier applied to an audio system is characterized in that: the single-ended OUTPUT operational amplifier comprises two single-ended OUTPUT operational amplifiers A1 and A2, an adjustable resistor array, a digital control module and a low-frequency anti-aliasing filter, wherein the non-inverting INPUT ends of the A1 and the A2 are respectively connected with differential INPUT signals INPUT _ A and INPUT _ B, the inverting INPUT ends of the A1 and the A2 are connected with the adjustable resistor array, the OUTPUT ends of the A1 and the A2 are connected with the adjustable resistor array and the low-frequency anti-aliasing filter, and the amplified INPUT _ A and INPUT _ B are finally filtered by the low-frequency anti-aliasing filter to obtain differential OUTPUT signals OUTPUT _ A and OUTPUT _ B;

the digital control module receives an externally input clock signal, so that a pair of reciprocal clock signals are generated and provided for A1 and A2; meanwhile, the digital control module receives an externally input enable signal for controlling the current of the output stage of the operational amplifier, so that two pairs of opposite enable signals are generated and supplied to A1 and A2; in addition, the digital control module also receives an externally input digital logic signal for controlling the amplification factor, so that six pairs of reciprocal digital logic signals are generated and transmitted to the adjustable resistor array;

the adjustable resistor array enables the gain amplifier to achieve multiple amplification factors by changing the proportional relation of the operational amplifier load resistors.

2. The high accuracy low noise low power consumption programmable gain amplifier of claim 1, wherein: the adjustable resistor array comprises six high-linearity double-throw switches SW 1-SW 6 and six pairs of resistors R1a, R1B, R2a, R2B, R3a, R3B, R4a, R4B, R5a, R5B, R6a and R6B, two resistors of each pair have the same resistance value, wherein one end of R6a is connected with VOUTa end of SW6 and is used as PORT _ A PORT of the adjustable resistor array, the other end of R6a is connected with one end of R5a and VOUTa end of SW5, the other end of R5a is connected with one end of R4a and VOUTa end of SW4, the other end of R4a is connected with one end of R3a and VOUTa end of SW3, the other end of R3a is connected with one end of R2a and VOUTa end of SW2, the other end of R2a is connected with one end of R1a and VOUTa end of SW1, the other end of R1a is connected with one end of SW 1B, the other end of R1B is connected with one end of R2B and VOUTb end of SW1, the other end of R2B is connected with one end of R3B and VOUTb end of SW2, the other end of R3B is connected with one end of R4B and VOUTb end of SW3, the other end of R4B is connected with one end of R5B and VOUTb end of SW4, the other end of R5B is connected with one end of R6B and VOUTb end of SW5, the other end of R6B is connected with VOUTb end of SW6 and used as PORT _ B PORT of adjustable resistor array, the VINA ends of SW 1-SW 6 are connected together and used as PORT _ C PORT of adjustable resistor array, the VINB ends of SW 1-SW 6 are connected together and used as PORT _ D PORT of adjustable resistor array, the disconnection of SW 1-SW 6 is controlled by six pairs of digital logic signals provided by digital control module;

the PORT _ A PORT of the adjustable resistor array is connected with the output end of the A1, the PORT _ B PORT is connected with the output end of the A2, the PORT _ C PORT is connected with the inverting input end of the A1, and the PORT _ D PORT is connected with the inverting input end of the A2.

3. A high accuracy, low noise, low power consumption programmable gain amplifier according to claim 2, wherein: the high-linearity double-throw switches SW1 to SW6 have the same structure and comprise 8 PMOS tubes P1a, P2a, P3a, P4a, P1b, P2b, P3b, P4b and 8 NMOS tubes P5a, P6a, P7a, P8a, P5b, P6b, P7b and P8b, wherein the source of P1a is connected with the source of P1b and connected with a power supply voltage VDD, the gate of P1a is connected with the gate of P8a, the gate of P7a, the gate of P6a, the gate of P1b is connected with the gate of P8b, the gate of P7b and the gate of P6b and connected with RS-, the gate of P2a is connected with the gate of P2b, the gate of P3a, the gate of P3b, the gate of P4a, the gate of P4b, the gate of P5a and the gate of P5b are connected with RS +, the drain of P1a is connected with the drain of P8a, the drain of P2a, the drain of P3b and the drain of P3a, the drain of P2b and the substrate of P2b, the source of P8a is connected with the drain of P2a, the drain of P7a and the source of P3a and serves as a VINA end of the double-throw switch, the source of P8b is connected with the drain of P2b, the drain of P7b and the source of P3b and serves as a VINB end of the double-throw switch, the source of P7a is connected with the drain of P3a, the drain of P6a and the source of P4a and serves as a VOUTa end of the double-throw switch, the source of P7b is connected with the drain of P3b, the drain of P6b and the source of P4b and serves as a VOUTb end of the double-throw switch, the source of P6a is connected with the drain of P4a, the drain of P5a and the substrate of P7a, the source of P6b is connected with the drain of P4b, the drain of P5b and the substrate of P7b, the source of P5a is connected with the source of P5b in parallel with a power ground, and RS + and RS-VSS provide a pair of digital control signals for the digital control module.

4. The high accuracy low noise low power consumption programmable gain amplifier of claim 1, wherein: the operational amplifiers A1 and A2 have the same structure and are formed by sequentially connecting a high transconductance input stage, a gain amplification stage and a Class-AB adjustable current output stage, wherein:

the high transconductance input stage improves the transconductance of the operational amplifier input stage, improves the low-frequency gain of the operational amplifier as a whole and improves the unit gain bandwidth of the extended operational amplifier as a whole by carrying out proportional splitting and cross coupling on the input geminate transistors and NMOS tail current transistors in the folded cascode structure, thereby realizing the high precision of the gain amplifier and meeting the frequency range capable of processing input signals;

the gain amplification stage provides gain amplification for input signals through a folded cascode structure with an auxiliary operational amplifier, wherein a CHOP switch is used as a secondary spectrum shifting switch of the operational amplifier and is also used as a primary spectrum shifting switch of the auxiliary operational amplifier, so that a multiplexing function is realized;

the Class-AB adjustable current output stage realizes the control of the current of the operational amplifier output stage through the floating gate voltage feedforward control and the switch structure, and realizes the controllable power consumption of the operational amplifier.

5. The high accuracy low noise low power consumption programmable gain amplifier according to claim 4, wherein: the high transconductance input stage comprises a CHOP switch CHOPPER _ B, five PMOS transistors M0, M1a, M1B, M2a, M2B and four NMOS transistors M3a, M3B, M4a, M4B, wherein input ports IN _ a and IN _ B of the CHOPPER _ B correspond to a non-inverting input terminal and an inverting input terminal of the operational amplifier, an output port OUT _ a of the CHOPPER _ B is connected with a gate of the PMOS transistor M1a and a gate of the PMOS transistor M1B, an output port OUT _ B of the CHOPPER _ B is connected with a gate of the PMOS transistor M2a and a gate of the PMOS transistor M2B, a source of the PMOS transistor M0 is connected with a power supply voltage VDD, a gate of the PMOS transistor M0 is connected with a fixed bias voltage VBP3, the drain of M0 is connected with the source of M1a, the source of M1B, the source of M2a and the source of M2B, the drain of M1a is connected with the drain of M3a and serves as the non-inverting output terminal of the high transconductance input stage, the drain of M2a is connected with the drain of M4a and serves as the inverting output terminal of the high transconductance input stage, the drain of M1B is connected with the drain of M4B, the gate of M4B and the gate of M4a, the drain of M2B is connected with the drain of M3B, the gate of M3B and the gate of M3a, and the source of M3a is connected with the source of M3B, the source of M4a and the source of M4B and connected with the power ground VSS.

6. The high accuracy low noise low power consumption programmable gain amplifier according to claim 5, wherein: the gain amplifier stage comprises two auxiliary operational amplifiers GBP and GBN, two CHOPPER _ P and CHOPPER _ N, four PMOS tubes M7-M10 and two NMOS tubes M5 and M6, wherein the source of M9 is connected to the source of M10 and to the supply voltage VDD, the gate of M9 is connected to the gate of M10, the drain of M7 and the drain of M5, the drain of M9 is connected to the non-inverting input terminal of GBN and to the input port IN _ A of CHOPPER _ P, the drain of M10 is connected to the inverting input terminal of GBN and to the input port IN _ B of CHOPPER _ P, the output port OUT _ A of CHOPPER _ P is connected to the source of M7, the output port OUT _ B of CHOPPER _ P is connected to the source of M8, the non-inverting output terminal of GBN is connected to the gate of M7, the inverting output terminal of GBN is connected to the gate of M8, the drain of M8 is connected to the drain of M6, the source of M5 is connected to the input port of CHOPPER _ P, the inverting input port of GBN is connected to the inverting input port of GBP, the input port of high transconductance output port of CHOPPER _ P, and the input port of the input stage.

7. The high accuracy low noise low power consumption programmable gain amplifier according to claim 6, wherein: the auxiliary operational amplifier GBP comprises eight PMOS tubes PM0, PM1, PM2, PM3, PM8, PM9, PM10 and PM11, four NMOS tubes PM4, PM5, PM6 and PM7 and two CHOP switches CHOPPER _ P1 and CHOPPER _ N1, wherein the source of PM0 is connected to the source of PM10, the source of PM11 and the source of PM1 and is connected to a power supply voltage VDD, the gate of PM0 is connected to the gate of PM1 and is connected to a fixed bias voltage VBP3, the drain of PM0 is connected to the source of PM2, the drain of PM1 is connected to the source of PM3, the gate of PM2 and the gate of PM3 serve as a non-inverting input terminal and an inverting input terminal of the auxiliary operational amplifier GBP, the gate of PM10 is connected to the gate of PM11 and is connected to a fixed bias voltage VBP1, the drain of PM10 is connected to the input port IN _ A of OPPER _ P1, the drain of PM10 is connected to an output port of the fixed bias voltage VBP1, the gate of PM2 is connected to an output port of the drain of PM1 and is connected to a drain of the output port of PM2, the drain of the PMP 2, the auxiliary amplifier GBP 2 is connected to a gate of the output port of the PMP 1, the drain of the PMP 2 and is connected to a fixed drain of the output port of the PM1, the drain of the PM1, the PMP 2, the output port of the PMP 2, the drain of the PM1, the PMP 2 is connected to the output port of the PMP 2 and is connected to the drain of the PMP 2, the drain of the output port of the PMP 2, the drain of the PMP 2.

8. The high accuracy low noise low power consumption programmable gain amplifier according to claim 6, wherein: the auxiliary operational amplifier GBN comprises eight NMOS tubes NM0, NM1, NM2, NM3, NM4, NM5, NM6 and NM7, four PMOS tubes NM8, NM9, NM10 and NM11 and two CHOP switches CHOPPER _ P2 and CHOPPER _ N2, wherein the source of NM0 is connected with the source of NM1, the source of NM4 and the source of NM5 and is connected with a power ground VSS, the gate of NM0 is connected with the gate of NM1 and is connected with a fixed bias voltage VBN3, the drain of NM0 is connected with the source of NM2, the drain of NM1 is connected with the source of NM3, the gate of NM2 and the gate of NM3 are respectively used as a non-inverting input terminal and an inverting input terminal of the auxiliary operational amplifier GBN, the gate of NM4 is connected with the gate of NM5 and is connected with a fixed bias voltage VBN1, the drain of NM5 is connected with an output port OUT _ A of OPCHOPPER 2, the drain of NM4 is connected with an input port OUT _ A of CHOPPER 2, the source of NM6 is connected to the input port IN _ B of CHOPPER _ N2, the gate of NM6 is connected to the gate of NM7 and connected to a fixed bias voltage VBN2, the drain of NM7 is connected to the drain of NM9 and serves as the non-inverting output terminal of the auxiliary operational amplifier GBN, the drain of NM6 is connected to the drain of NM8 and serves as the inverting output terminal of the auxiliary operational amplifier GBN, the gate of NM8 is connected to the gate of NM9 and connected to a fixed bias voltage VBP2, the source of NM9 is connected to the output port OUT _ a of CHOPPER _ P2, the source of NM8 is connected to the output port OUT _ B of CHOPPER _ P2, the drain of NM11 is connected to the drain of NM2 and the input port IN _ a of CHOPPER _ P2, the drain of NM10 is connected to the drain of NM3 and the input port IN _ B of CHOPPER _ P2, the gate of NM10 is connected to the gate of NM11 and connected to a fixed bias voltage VBP1, the source of NM11 and connected to the power supply voltage VDD.

9. A high accuracy, low noise, low power consumption programmable gain amplifier according to claim 7 or 8, wherein: the CHOPPER _ B, CHOPPER _ P, CHOPPER _ N, CHOPPER _ P1, CHOPPER _ P2, CHOPPER _ N1 and CHOPPER _ N2 have the same structure and comprise four switch modules K1-K4, wherein the input end of K1 is connected with the input end of K2 and is used as the input port IN _ A of the CHOPPER, the output end of K1 is connected with the output end of K3 and is used as the output port OUT _ A of the CHOPPER, the input end of K3 is connected with the input end of K4 and is used as the input port IN _ B of the CHOPPER, and the output end of K2 is connected with the output end of K4 and is used as the output port OUT _ B of the CHOPPER; switch modules K1-K4 in CHOPPER _ P, CHOPPER _ P1 and CHOPPER _ P2 adopt PMOS tubes, switch modules K1-K4 in CHOPPER _ N, CHOPPER _ N1 and CHOPPER _ N2 adopt NMOS tubes, and switch modules K1-K4 in CHOPPER _ B adopt Bootstrap switches.

10. The high accuracy low noise low power consumption programmable gain amplifier of claim 9, wherein: the Bootstrap switch comprises a capacitor C1, four PMOS tubes SM1, SM2, SM3, SM6 and seven NMOS tubes SM4, SM5, SM7, SM8, SM9, SM10 and SM11, wherein the drain of SM1 is connected with the source of SM6, the gate of SM4 and the source of SM2 and is connected with a power supply voltage VDD, the gate of SM1 is connected with the drain of SM3, the drain of SM4, the gate of SM8, the gate of SM9 and the gate of SM10, the source of SM1 is connected with one end of C1 and the source of SM3, the other end of C1 is connected with the drain of SM11, the source of SM7, the source of SM8 and the drain of SM9, the source of SM11 is connected with a power supply ground VSS, the gate of SM11 is connected with CLK1, the gate of SM6 is connected with the gate of SM7, the drain of SM6 is connected with the drain of SM7, the gate of SM3 and the drain of SM8, the drain of SM2 is connected with the source of SM4 and the drain of SM5, the gate of SM2 is connected with the gate of SM5, the gate of SM5 is connected with a clock module, the CLK1 and the source of the clock module, the clock module is connected with the output terminal of the CLK 10, and the clock module are connected with the output terminal of the clock module, and the clock module.

Images