CN115862524A

CN115862524A - Swept frequency signal driver and display device including the same

Info

Publication number: CN115862524A
Application number: CN202211180263.6A
Authority: CN
Inventors: 金玄俊; 黄定桓; 郑京薰; 郑浚琦
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2021-09-24
Filing date: 2022-09-26
Publication date: 2023-03-28
Also published as: US20230107775A1; KR20230044068A; US11869415B2

Abstract

The present disclosure provides a swept frequency signal driver and a display device including the swept frequency signal driver. The swept signal driver includes a kth stage for outputting a kth transmit signal to a kth transmit line and a kth swept signal to a kth swept signal line, the kth stage including: a first pull-up node, a second pull-up node and a third pull-up node; a node connection circuit between the first pull-up node and the second pull-up node and between the first pull-up node and the third pull-up node; a first output circuit for outputting a sweep clock signal of the sweep clock terminal to a first output terminal when the third pull-up node has a gate-on voltage, the first output terminal being connected to a kth scan signal line; and a second output circuit for outputting the gate-on voltage to a second output terminal when the second pull-up node has the gate-on voltage, the second output terminal being connected to the kth transmission line. The pulse of the k-th swept frequency signal changes linearly from the gate-off voltage to the gate-on voltage.

Description

Swept frequency signal driver and display device including the same

Cross Reference to Related Applications

This application claims priority and benefit to korean patent application No. 10-2021-0126468, filed on Korean Intellectual Property Office (KIPO) at 24/9/2021, the entire contents of which are incorporated herein by reference.

Technical Field

Aspects of one or more embodiments of the present disclosure relate to a swept frequency signal driver and a display device including the swept frequency signal driver.

Background

With the development of the information society, the demand for display devices for displaying images has increased and diversified. The display device may be a flat panel display device such as a Liquid Crystal Display (LCD) device, a Field Emission Display (FED) device, and a light emitting display device.

The light emitting display device may include an organic light emitting display device including an organic light emitting diode element as a light emitting element or a light emitting diode display device including an inorganic light emitting diode element such as a Light Emitting Diode (LED) as a light emitting element. In the case of an organic light emitting display device, the luminance or gray level of light of the organic light emitting diode element may be adjusted by adjusting the magnitude of a driving current applied to the organic light emitting diode element. However, since the wavelength of light emitted from the inorganic light emitting diode element may vary depending on the driving current, when the inorganic light emitting diode element is driven in the same manner as the organic light emitting diode element, image quality may be deteriorated.

The above information disclosed in this background section is for enhancement of understanding of the background of the disclosure and, therefore, may contain information that does not constitute prior art.

Disclosure of Invention

An aspect of some embodiments of the present disclosure relates to a display device capable of reducing or preventing deterioration of image quality due to a change in wavelength of light emitted from an inorganic light emitting diode element depending on a driving current applied to the inorganic light emitting diode element.

However, the present disclosure is not limited to the aspects and features set forth above. The above and other aspects and features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below with reference to the accompanying drawings.

In accordance with one or more embodiments of the present disclosure, a swept frequency signal driver includes: a plurality of stages configured to sequentially output the plurality of transmission signals to the plurality of transmission lines and the plurality of sweep signals to the plurality of sweep signal lines, the plurality of stages including a kth stage that outputs a kth transmission signal of the plurality of transmission signals to a kth transmission line of the plurality of transmission lines and a kth sweep signal of the plurality of sweep signals to a kth sweep signal line of the plurality of sweep signal lines, wherein k is a natural number greater than zero. The kth stage includes: a first pull-up node; a second pull-up node; a third pull-up node; a node connection circuit between the first pull-up node and the second pull-up node and between the first pull-up node and the third pull-up node; a first output circuit configured to output a sweep clock signal of the sweep clock terminal to a first output terminal when the third pull-up node has a gate-on voltage, the first output terminal being connected to a kth sweep signal line; and a second output circuit configured to output the gate-on voltage to a second output terminal when the second pull-up node has the gate-on voltage, the second output terminal being connected to the kth emission line. The pulse of the k-th swept frequency signal changes linearly from the gate-off voltage to the gate-on voltage.

In an embodiment, the pulse width of the kth transmit signal may be greater than the pulse width of the kth sweep signal.

In an embodiment, the kth stage may further include a pull-down node electrically disconnected from the first, second, and third pull-up nodes, and each of the first and second output circuits may be configured to output a gate-off voltage when the pull-down node has a gate-on voltage.

In an embodiment, the first output circuit may include: a first pull-up transistor including a gate electrode connected to the third pull-up node, a first electrode connected to the first output terminal, and a second electrode connected to the swept clock terminal; a first pull-down transistor including a gate electrode connected to a pull-down node, a first electrode connected to a gate-off voltage terminal configured to receive a gate-off voltage, and a second electrode connected to a first output terminal; and a first capacitor between the third pull-up node and the first output terminal.

In an embodiment, the second output circuit may include: a second pull-up transistor including a gate electrode connected to the second pull-up node, a first electrode connected to the second output terminal, and a second electrode connected to a gate-on voltage terminal configured to receive a gate-on voltage; and a second pull-down transistor including a gate electrode connected to the pull-down node, a first electrode connected to a gate-off voltage terminal configured to receive a gate-off voltage, and a second electrode connected to the second output terminal.

In an embodiment, the kth stage may further include: a pull-up node control circuit configured to supply a start signal or a carry signal of a start terminal to a first pull-up node according to a first transmit clock signal input to a first transmit clock terminal.

In an embodiment, the pull-up node control circuit may include: and a first transistor including a gate electrode connected to the first transmit clock terminal, a first electrode connected to the first pull-up node, and a second electrode connected to the start terminal.

In an embodiment, the kth stage may further include: a first control node control circuit configured to supply a gate-on voltage to the first control node according to a first transmit clock signal, and supply the first transmit clock signal to the first control node according to a voltage of the first pull-up node.

In an embodiment, the first control node control circuit may include: a second transistor including a gate electrode connected to the first transmission clock terminal, a first electrode connected to the first control node, and a second electrode connected to a gate-on voltage terminal configured to receive a gate-on voltage; a third transistor including a second electrode, a gate electrode connected to the first pull-up node, and a first electrode connected to the first transmission clock terminal; and a fourth transistor including a gate electrode connected to the first pull-up node, a first electrode connected to the second electrode of the third transistor, and a second electrode connected to the first control node.

In an embodiment, the kth stage may further include: a second control node control circuit configured to supply a gate-off voltage to the second control node when the first control node has the gate-on voltage, and to supply a second transmit clock signal of the second transmit clock terminal to the second control node when the second pull-up node has the gate-on voltage.

In an embodiment, the second control node control circuit may include: a fifth transistor including a gate electrode connected to the first control node, a first electrode connected to a gate-off voltage terminal configured to receive a gate-off voltage, and a second electrode connected to the second control node; a sixth transistor including a gate electrode connected to the second pull-up node, a first electrode connected to the second control node, and a second electrode connected to the second transmission clock terminal; and a second capacitor between the second pull-up node and the second control node.

In an embodiment, the node connection circuit may be further located between the first control node and the third control node, and the kth stage may further include: a pull-down node control circuit configured to supply a gate-on voltage of the second transmission clock signal to the pull-down node when the third control node has the gate-on voltage and the second transmission clock signal of the second transmission clock terminal has the gate-on voltage.

In an embodiment, the pull-down node control circuit may be further configured to supply a gate-off voltage to the pull-down node when the first pull-up node has the gate-on voltage.

In an embodiment, the pull-down node control circuit may include: a seventh transistor including a gate electrode connected to the third control node, a first electrode connected to the second transmission clock terminal, and a second electrode connected to the fourth control node; an eighth transistor including a gate electrode connected to the second transmission clock terminal, a first electrode connected to the fourth control node, and a second electrode connected to the pull-down node; a ninth transistor including a gate electrode connected to the first pull-up node, a first electrode connected to a gate-off voltage terminal configured to receive a gate-off voltage, and a second electrode connected to the pull-down node; a third capacitor between the third control node and the fourth control node; and a fourth capacitor between the pull-down node and the gate-off voltage terminal.

In an embodiment, the node connection circuit may include: a tenth transistor including a gate electrode connected to a gate-on voltage terminal configured to receive a gate-on voltage, a first electrode connected to the first pull-up node, and a second electrode connected to the second pull-up node; an eleventh transistor including a gate electrode connected to the gate-on voltage terminal, a first electrode connected to the first pull-up node, and a second electrode connected to the third pull-up node; and a twelfth transistor including a gate electrode connected to the gate-on voltage terminal, a first electrode connected to the third control node, and a second electrode connected to the first control node.

According to one or more embodiments of the present disclosure, a display device includes: a display panel including a plurality of data lines, a plurality of sweep signal lines and a plurality of Pulse Width Modulation (PWM) emission lines crossing the plurality of data lines, and a plurality of subpixels connected to the plurality of data lines, the plurality of sweep signal lines, and the plurality of PWM emission lines; a source driver configured to apply a plurality of data voltages to a plurality of data lines; and a sweep signal driver including a plurality of stages configured to sequentially output the plurality of PWM transmit signals to the plurality of PWM transmit lines and to sequentially output the plurality of sweep signals to the plurality of sweep signal lines. The plurality of stages includes a kth stage configured to output a kth PWM transmit signal of the plurality of PWM transmit signals to a kth PWM transmit line of the plurality of PWM transmit lines and a kth sweep signal of the plurality of sweep signals to a kth sweep signal line of the plurality of sweep signal lines, where k is a natural number greater than zero. The pulse of the kth PWM transmission signal includes a gate-on voltage, the pulse of the kth frequency sweep signal linearly changes from the gate-off voltage to the gate-on voltage, and the pulse width of the kth PWM transmission signal is greater than the pulse width of the kth frequency sweep signal.

In an embodiment, the display device may further include: a transmission signal driver configured to sequentially output a plurality of Pulse Amplitude Modulation (PAM) transmission signals to a plurality of data lines crossing the PAM transmission lines. The pulse of a kth PAM transmit signal of the plurality of PAM transmit signals that is output to a kth PAM transmit line of the plurality of PAM transmit lines may include a gate on voltage, and a pulse width of the kth PAM transmit signal may be the same as a pulse width of the kth sweep signal.

In an embodiment, the pulses of the kth PWM transmit signal may overlap with the pulses of the kth frequency sweep signal and the pulses of the ktam transmit signal.

In an embodiment, the kth stage may include: a first pull-up node, a second pull-up node and a third pull-up node; a node connection circuit between the first pull-up node and the second pull-up node and between the first pull-up node and the third pull-up node; a first output circuit configured to output a sweep clock signal of a sweep clock terminal to a first output terminal when the third pull-up node has a gate-on voltage, the first output terminal being connected to a kth sweep signal line; and a second output circuit configured to output the gate-on voltage to a second output terminal when the second pull-up node has the gate-on voltage, the second output terminal being connected to the kth pulse width modulation transmission line.

According to one or more embodiments of the present disclosure, the luminance of light emitted from the inorganic light emitting element can be controlled by adjusting the period in which the driving current is applied to the inorganic light emitting element while maintaining the driving current at or substantially at a constant or substantially constant. Accordingly, deterioration in image quality due to a change in the wavelength of light emitted from the inorganic light emitting element depending on the drive current applied to the inorganic light emitting element can be reduced or prevented.

According to one or more embodiments of the present disclosure, one stage of the sweep signal driver may output the sweep signal and the PWM transmission signal concurrently (e.g., simultaneously), and thus the area of the sweep driver may be reduced.

Drawings

The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments, with reference to the accompanying drawings, in which:

fig. 1 is a block diagram showing a display device according to an embodiment;

fig. 2 is a circuit diagram showing a first sub-pixel according to the embodiment;

fig. 3 shows graphs respectively showing wavelengths of light emitted from the light emitting element of the first sub-pixel, the light emitted from the light emitting element of the second sub-pixel, and the light emitted from the light emitting element of the third sub-pixel depending on the driving current according to the embodiment;

fig. 4 shows graphs respectively showing the light emitting efficiency of the light emitting element of the first sub-pixel, the light emitting efficiency of the light emitting element of the second sub-pixel, and the light emitting efficiency of the light emitting element of the third sub-pixel depending on the driving current according to the embodiment;

fig. 5 is a schematic diagram illustrating an operation of the display device during the nth to N +2 th frame periods;

fig. 6 is another schematic diagram illustrating an operation of the display apparatus during the nth to N +2 th frame periods;

fig. 7 is a waveform diagram illustrating a scan initialization signal, a scan write signal, a scan control signal, a Pulse Width Modulation (PWM) emission signal, a Pulse Amplitude Modulation (PAM) emission signal, and a frequency sweep signal applied to subpixels disposed in k-th to k + 5-th row lines during an nth frame period;

fig. 8 is a waveform diagram illustrating a kth scan initialization signal, a kth scan write signal, a kth scan control signal, a kth PWM emission signal, a kth PAM emission signal, and a kth sweep signal applied to each of subpixels disposed in a kth row line during an nth frame period, a voltage of a third node of a first subpixel, and a period in which a driving current is applied to a light emitting element;

fig. 9 to 12 are circuit diagrams illustrating operations of the first sub-pixel during the first period, the second period, the third period, and the sixth period;

FIG. 13 is a block diagram illustrating a swept frequency signal driver according to an embodiment;

fig. 14 is a circuit diagram showing a kth stage of a swept frequency signal driver according to an embodiment;

fig. 15 is a waveform diagram illustrating a start signal or a previous stage bit signal, a first transmit clock signal, a second transmit clock signal, and first to sixth frequency sweep clock signals applied to a kth stage, a voltage of a first pull-up node, a voltage of a second pull-up node, a voltage of a third pull-up node, and a voltage of a pull-down node of the kth stage, and a kth PWM transmit signal and a kth frequency sweep signal output from the kth stage according to an embodiment;

fig. 16 to 19 are circuit diagrams illustrating an operation of the kth stage during the first to eighth periods;

fig. 20 is a perspective view illustrating a display device according to an embodiment;

fig. 21 is a plan view showing a display device according to another embodiment; and

fig. 22 is a plan view illustrating a tiled display device including the display device illustrated in fig. 21.

Detailed Description

Embodiments will be described in more detail hereinafter with reference to the drawings, in which like reference numerals refer to like elements throughout. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects and features of the disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to a full understanding of the aspects and features of the disclosure may not be described to those of ordinary skill in the art. Unless otherwise indicated, like reference numerals refer to like elements throughout the drawings and written description, and thus, redundant description thereof may not be repeated.

While certain embodiments may be implemented differently, the particular process sequence may differ from that described. For example, two processes described in succession may be executed concurrently or substantially concurrently, or may be executed in the reverse order to that described.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as "below," "lower," "beneath," "above," and "upper" and the like, may be used herein for explanatory purposes to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. For example, when the first portion is described as being disposed "on" the second portion, it means that the first portion is disposed on an upper side or a lower side of the second portion based on the direction of gravity, and is not limited to the upper side of the second portion.

Moreover, cross-hatching and/or shading in the figures is generally employed to clarify boundaries between adjacent elements. Thus, the presence or absence of cross-hatching or shading, unless otherwise indicated, does not convey or indicate any preference or requirement for particular materials, material properties, sizes, proportions, commonality between illustrated elements, and/or any other characteristic, attribute, and/or property of an element, etc.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Further, specific structural or functional descriptions disclosed herein are merely illustrative for purposes of describing embodiments in accordance with the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as limited to the particular shapes of regions illustrated, but are to include variations and deviations in shapes that may result, for example, from their manufacture.

For example, an implanted region illustrated as a rectangle may generally have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are therefore not intended to be limiting. Moreover, as those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit and scope of the present disclosure.

As used herein, the phrase "in plane" or "in plan view" refers to a view of the target portion viewed from the top, and the phrase "in section" or "in cross-sectional view" refers to a view of a section formed by perpendicularly cutting the target portion viewed from the side.

In the drawings, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular or substantially perpendicular to each other, or may represent different directions from each other that are not perpendicular to each other.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or one or more intervening elements or layers may be present. Similarly, when a layer, region or element is referred to as being "electrically connected" to another layer, region or element, the layer, region or element may be directly electrically connected to the other layer, region or element, and/or may be indirectly electrically connected to the other layer, region or element with one or more intervening layers, regions or elements therebetween. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and/or B" means A, B or A and B. When placed after a list of elements, an expression such as "at least one of" modifies the entire list of elements and does not modify an individual element of the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, any combination of two or more of a, b, and c (such as, for example, abc, abb, bc, and cc), or variants thereof.

As used herein, the terms "substantially," "approximately," and the like are used as approximate terms and not as degree terms, and are intended to take into account the inherent variation in measured or calculated values that would be recognized by one of ordinary skill in the art. "approximately" or "about" as used herein includes the stated value and is meant to be within an acceptable range of deviation of the stated value as determined by one of ordinary skill in the art, given the measurement in question and the error associated with measuring the particular quantity (i.e., the limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.

Moreover, any numerical range disclosed and/or recited herein is intended to include all sub-ranges subsumed within the recited range with the same numerical precision. For example, a range of "1.0 to 10.0" is intended to include all sub-ranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0 (and including the recited minimum value of 1.0 and the recited maximum value of 10.0), that is, all sub-ranges having a minimum value equal to or greater than 1.0 and a maximum value of equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, applicants reserve the right to modify this document, including the claims, to explicitly recite any sub-ranges subsumed within the ranges explicitly recited herein. All such ranges are intended to be inherently described in this specification such that modifications to explicitly recite any such sub-ranges would comply with the requirements of clause 26, 3, and 33 of the chinese patent law.

Further, the use of "may" in describing an embodiment of the disclosure refers to "one or more embodiments of the disclosure. As used herein, the terms "use," "using," and "used" can be considered synonymous with the terms "utilizing," "utilizing," and "utilized," respectively. Moreover, the term "exemplary" is intended to refer to an example or illustration.

Electronic or electrical devices and/or any other related devices or components according to embodiments of the disclosure described herein may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or combination of software, firmware, and hardware. For example, various components of these devices may be formed on one Integrated Circuit (IC) chip or on separate IC chips. Further, various components of these devices may be implemented on a flexible printed circuit film, a Tape Carrier Package (TCP), or a Printed Circuit Board (PCB), or formed on one substrate.

Further, the various components of these devices may be processes or threads that execute on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that may be implemented in the computing device using standard memory devices, such as, for example, random Access Memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media, such as, for example, a CD-ROM or flash drive, etc. In addition, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or that the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the embodiments of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a block diagram illustrating a display device according to an embodiment.

Referring to fig. 1, the display device 10 includes a display panel 100, a scan driver 110, a source driver 200, a timing controller 300, and a power supply unit (e.g., power supply) 400.

The display area DA of the display panel 100 may include subpixels RP, GP, and BP for displaying an image and a scan write line GWL, a scan initialization line GIL, a scan control line GCL, a scan signal line SWPL, a Pulse Width Modulation (PWM) emission line PWEL, a Pulse Amplitude Modulation (PAM) emission line PAEL, a data line DL, a first PAM data line RDL, a second PAM data line GDL, and a third PAM data line BDL connected to the subpixels RP, GP, and BP.

The scan write line GWL, the scan initialization line GIL, the scan control line GCL, the scan signal line SWPL, the PWM emission line PWEL, and the PAM emission line PAEL may extend in a first direction (e.g., X-axis direction) DR1, and may be disposed in a second direction (e.g., Y-axis direction) DR2 crossing the first direction (e.g., X-axis direction) DR 1. The data line DL, the first PAM data line RDL, the second PAM data line GDL, and the third PAM data line BDL may extend in a second direction (e.g., Y-axis direction) DR2, and may be disposed along a first direction (e.g., X-axis direction) DR 1. The first PAM data lines RDL may be electrically connected to each other, the second PAM data lines GDL may be electrically connected to each other, and the third PAM data lines BDL may be electrically connected to each other.

The subpixels RP, GP and BP may include a first subpixel RP for emitting first light, a second subpixel GP for emitting second light, and a third subpixel BP for emitting third light. The first light is light referring to a red wavelength band, the second light is light referring to a green wavelength band, and the third light is light referring to a blue wavelength band. For example, the dominant peak wavelength of the first light may be between about 600nm and 750nm, the dominant peak wavelength of the second light may be between about 480nm and 560nm, and the dominant peak wavelength of the third light may be between about 370nm and 460 nm.

Each of the subpixels RP, GP, and BP may be connected to a corresponding one of the scan write lines GWL, a corresponding one of the scan initialization lines GIL, a corresponding one of the scan control lines GCL, a corresponding one of the sweep signal lines SWPL, a corresponding one of the PWM emission lines PWEL, and a corresponding one of the PAM emission lines PAEL. Each of the first subpixels RP may be further connected to a corresponding one of the data lines DL and a corresponding one of the first PAM data lines RDL. Each of the second subpixels GP may be further connected to a corresponding one of the data lines DL and a corresponding one of the second PAM data lines GDL. Each of the third subpixels BP may be further connected to a corresponding one of the data lines DL and a corresponding one of the third PAM data lines BDL.

The scan driver 110 may apply signals to the scan write line GWL, the scan initialization line GIL, the scan control line GCL, the sweep signal line SPWL, the PWM emission line PWEL, and the PAM emission line PAEL, and may be disposed at (e.g., in or on) the non-display area NDA of the display panel 100. Fig. 1 shows that the scan driver 110 may be disposed at an edge of one side of the display panel 100, but the present disclosure is not limited thereto. For example, in some embodiments, the plurality of scan drivers 110 may be disposed at edges of opposite sides of the display panel 100.

The scan driver 110 may include a first scan signal driver 111, a second scan signal driver 112, a sweep signal driver 113, and an emission signal driver 114.

The first scan signal driver 111 may receive the first scan driving control signal GDCS1 from the timing controller 300. The first scan signal driver 111 may output a scan initialization signal to the scan initialization line GIL according to the first scan driving control signal GDCS1, and may output a scan write signal to the scan write line GWL according to the first scan driving control signal GDCS1. In other words, the first scan signal driver 111 may output two scan signals, i.e., a scan initialization signal and a scan write signal, together.

The second scan signal driver 112 may receive the second scan driving control signal GDCS2 from the timing controller 300. The second scan signal driver 112 may output a scan control signal to the scan control lines GCL according to the second scan driving control signal GDCS2.

The sweep signal driver 113 may receive the first emission control signal ECS1 and the sweep control signal SWCS from the timing controller 300. The sweep signal driver 113 may output the PWM transmission signal to the PWM transmission line PWEL and may output the sweep signal to the sweep signal line SWPL according to the first transmission control signal ECS1 and the sweep control signal SWCS. In other words, the sweep signal driver 113 may output the PWM transmit signal and the sweep signal together.

The emission signal driver 114 may receive the second emission control signal ECS2 from the timing controller 300. The emission signal driver 114 may output a PAM emission signal to the PAM emission line PAEL according to the second emission control signal ECS2.

The timing controller 300 receives the digital video DATA and the timing signal TS. The timing controller 300 may generate a first scan driving control signal GDCS1, a second scan driving control signal GDCS2, a first emission control signal ECS1, a second emission control signal ECS2, and a sweep control signal SWCS for controlling an operation timing of the scan driver 110 according to the timing signal TS. In addition, the timing controller 300 may generate a data control signal DCS for controlling the operation timing of the source driver 200.

The timing controller 300 may output the first scan driving control signal GDCS1, the second scan driving control signal GDCS2, the first emission control signal ECS1, the second emission control signal ECS2, and the frequency sweep control signal SWCS to the scan driver 110. The timing controller 300 outputs the digital video DATA and the DATA control signal DCS to the source driver 200.

The source driver 200 converts the digital video DATA into an analog DATA voltage, and outputs the analog DATA voltage (hereinafter, also referred to as a DATA voltage) to the DATA lines DL. Accordingly, the subpixels RP, GP and BP may be selected by a scan write signal of the scan driver 110, and a data voltage may be supplied to the selected subpixels RP, GP and BP.

The power supply cell 400 may commonly output the first PAM data voltage to the first PAM data line RDL, may commonly output the second PAM data voltage to the second PAM data line GDL, and may commonly output the third PAM data voltage to the third PAM data line BDL. In addition, the power supply unit 400 may generate a plurality of source voltages and may output the plurality of source voltages to the display panel 100.

The power supply unit 400 may output the first source voltage VDD1, the second source voltage VDD2, the third source voltage VSS, the initialization voltage VINT, the gate-on voltage VGL, and the gate-off voltage VGH to the display panel 100. The first and second source voltages VDD1 and VDD2 may be high potential driving voltages for driving the light emitting elements of each of the sub-pixels RP, GP, and BP. The third source voltage VSS may be a low potential driving voltage for driving the light emitting element of each of the sub-pixels RP, GP, and BP. The initialization voltage VINT and the gate-off voltage VGH may be applied to each of the sub-pixels RP, GP, and BP, and the gate-on voltage VGL and the gate-off voltage VGH may be applied to the scan driver 110.

Fig. 2 is a circuit diagram illustrating a first sub-pixel according to an embodiment.

Referring to fig. 2, the first subpixel RP according to the embodiment may be connected to a kth scanning write line GWLk, a kth scanning initialization line GILk, a kth scanning control line GCLk, a kth scanning signal line SWPLk, a kth pwm emission line PWELk, and a kth PAM emission line PAELk, where k is a natural number greater than zero. In addition, the first subpixel RP may be connected to a jth data line DLj and a first PAM data line RDL, where j is a natural number greater than zero. Further, the first subpixel RP may be connected to the first power line VDL1 to which the first source voltage VDD1 is applied, the second power line VDL2 to which the second source voltage VDD2 is applied, the third power line VSL to which the third source voltage VSS is applied, the initialization voltage line VIL to which the initialization voltage VINT is applied, and the gate-off voltage line VGHL to which the gate-off voltage VGH is applied. For convenience of description, the jth data line DLj may be referred to as a first data line, and the first PAM data line RDL may be referred to as a second data line.

The first subpixel RP may include a light emitting element EL, a first pixel driving unit (e.g., a first pixel driving circuit or a first pixel driver) PDU1, a second pixel driving unit (e.g., a second pixel driving circuit or a second pixel driver) PDU2, and a third pixel driving unit (e.g., a third pixel driving circuit or a third pixel driver) PDU3.

The light emitting element EL emits light in accordance with (e.g., in dependence on) the drive current Ids (see fig. 12) generated by the second pixel drive unit PDU 2. The light emitting element EL may be disposed between the seventeenth transistor T17 and the third power line VSL. A first electrode of the light emitting element EL may be connected to a second electrode of the seventeenth transistor T17, and a second electrode of the light emitting element EL may be connected to the third power line VSL. The first electrode of the light emitting element EL may be an anode electrode, and the second electrode of the light emitting element EL may be a cathode electrode. The light-emitting element EL may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element EL may be a micro light emitting diode including (e.g., made of) an inorganic semiconductor, but the present disclosure is not limited thereto.

The first pixel driving unit PDU1 controls the voltage of the third node N3 of the third pixel driving unit PDU3 by generating a control current Ic (see fig. 12) according to the data voltage Vdata (see fig. 12) of the j-th data line DLj. Since the pulse width of the voltage applied to the first electrode of the light emitting element EL may be adjusted by the control current Ic of the first pixel driving unit PDU1, the first pixel driving unit PDU1 may be a Pulse Width Modulation (PWM) unit (e.g., a PWM circuit) for performing pulse width modulation of the voltage applied to the first electrode of the light emitting element EL.

The first pixel driving unit PDU1 may include first to seventh transistors T1 to T7 and a first capacitor PC1.

The first transistor T1 controls the control current Ic flowing between the second electrode and the first electrode of the first transistor T1 according to the voltage applied to the gate electrode of the first transistor T1.

The second transistor T2 is turned on by a kth scan write signal of the kth scan write line GWLk to supply the data voltage Vdata of the jth data line DLj to the first electrode of the first transistor T1. A gate electrode of the second transistor T2 may be connected to the kth scanning write line GWLk, a first electrode of the second transistor T2 may be connected to the jth data line DLj, and a second electrode of the second transistor T2 may be connected to a first electrode of the first transistor T1.

The third transistor T3 is turned on by a kth scan initialization signal of the kth scan initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the first transistor T1. Accordingly, during a period in which the third transistor T3 is turned on, the gate electrode of the first transistor T1 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. In this case, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In more detail, since a voltage difference between the gate-on voltage VGL and the initialization voltage VINT is greater than a threshold voltage of the third transistor T3, the third transistor T3 can be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the first transistor T1. Accordingly, when the third transistor T3 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the first transistor T1 regardless of the threshold voltage of the third transistor T3.

The third transistor T3 may include a plurality of transistors connected in series with each other. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. Accordingly, the voltage of the gate electrode of the first transistor T1 may be prevented or substantially prevented from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 may be connected to the kth scan initialization line GILk, the first electrode of the first sub-transistor T31 may be connected to the gate electrode of the first transistor T1, and the second electrode of the first sub-transistor T31 may be connected to the first electrode of the second sub-transistor T32. The gate electrode of the second sub-transistor T32 may be connected to the kth scan initialization line GILk, the first electrode of the second sub-transistor T32 may be connected to the second electrode of the first sub-transistor T31, and the second electrode of the second sub-transistor T32 may be connected to the initialization voltage line VIL.

The fourth transistor T4 is turned on by a kth scan write signal of the kth scan write line GWLk to connect the gate electrode and the second electrode of the first transistor T1 to each other. Accordingly, during a period in which the fourth transistor T4 is turned on, the first transistor T1 may operate as a diode. In other words, the fourth transistor T4 may be turned on to diode-connect the first transistor T1.

The fourth transistor T4 may include a plurality of transistors connected in series with each other. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. Accordingly, the voltage of the gate electrode of the first transistor T1 may be prevented or substantially prevented from leaking through the fourth transistor T4. A gate electrode of the third sub-transistor T41 may be connected to the kth scanning write line GWLk, a first electrode of the third sub-transistor T41 may be connected to the second electrode of the first transistor T1, and a second electrode of the third sub-transistor T41 may be connected to the first electrode of the fourth sub-transistor T42. A gate electrode of the fourth sub-transistor T42 may be connected to the kth scanning write line GWLk, a first electrode of the fourth sub-transistor T42 may be connected to a second electrode of the third sub-transistor T41, and a second electrode of the fourth sub-transistor T42 may be connected to a gate electrode of the first transistor T1.

The fifth transistor T5 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the first electrode of the first transistor T1 to the first power line VDL1. A gate electrode of the fifth transistor T5 may be connected to the kth PWM transmission line PWELk, a first electrode of the fifth transistor T5 may be connected to the first power line VDL1, and a second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1.

The sixth transistor T6 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the second electrode of the first transistor T1 to the third node N3 of the third pixel driving unit PDU3. A gate electrode of the sixth transistor T6 may be connected to the kth PWM emission line PWELk, a first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1, and a second electrode of the sixth transistor T6 may be connected to the third node N3 of the third pixel driving unit PDU3.

The seventh transistor T7 may be turned on by the kth scan control signal of the kth scan control line GCLk to supply the gate-off voltage VGH of the gate-off voltage line VGHL to the first node N1 connected to the kth scan signal line SWPLk. Accordingly, during a period in which the initialization voltage VINT is applied to the gate electrode of the first transistor T1 and a period in which the data voltage Vdata of the j-th data line DLj and the threshold voltage Vth1 (see fig. 12) of the first transistor T1 are programmed, it is possible to prevent or substantially prevent the amount of change in the voltage of the gate electrode of the first transistor T1 from being reflected in the k-th sweep signal of the k-th sweep signal line SWPLk through the first capacitor PC1. A gate electrode of the seventh transistor T7 may be connected to the kth scan control line GCLk, a first electrode of the seventh transistor T7 may be connected to the gate-off voltage line VGHL, and a second electrode of the seventh transistor T7 may be connected to the first node N1.

The first capacitor PC1 may be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor PC1 may be connected to the gate electrode of the first transistor T1, and the other electrode of the first capacitor PC1 may be connected to the first node N1.

The first node N1 may be a contact point between the kth sweep signal line SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor PC1.

The second pixel driving unit PDU2 generates a driving current Ids supplied to the light emitting element EL according to the first PAM data voltage of the first PAM data line RDL. The second pixel driving unit PDU2 may be a Pulse Amplitude Modulation (PAM) unit (e.g., PAM circuit) for performing pulse amplitude modulation. In this case, each of the first subpixels RP may be a constant or substantially constant current generator that receives the same or substantially the same first PAM data voltage and generates the same or substantially the same drive current Ids regardless of the luminance of the first subpixel RP.

The second pixel driving unit PDU2 may include eighth to fourteenth transistors T8 to T14 and a second capacitor PC2.

The eighth transistor T8 controls the drive current Ids flowing to the light emitting element EL according to the voltage applied to the gate electrode of the eighth transistor T8.

The ninth transistor T9 is turned on by the kth scan write signal of the kth scan write line GWLk to apply the first PAM data voltage of the first PAM data line RDL to the first electrode of the eighth transistor T8. A gate electrode of the ninth transistor T9 may be connected to the kth scanning write line GWLk, a first electrode of the ninth transistor T9 may be connected to the first PAM data line RDL, and a second electrode of the ninth transistor T9 may be connected to a first electrode of the eighth transistor T8.

The tenth transistor T10 is turned on by the kth scan initialization signal of the kth scan initialization line GILk to connect the initialization voltage line VIL to the gate electrode of the eighth transistor T8. Accordingly, during a period in which the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. In this case, the gate-on voltage VGL of the kth scan initialization signal may be different from the initialization voltage VINT of the initialization voltage line VIL. In more detail, since a voltage difference between the gate-on voltage VGL and the initialization voltage VINT is greater than a threshold voltage of the tenth transistor T10, the tenth transistor T10 may be stably turned on even after the initialization voltage VINT is applied to the gate electrode of the eighth transistor T8. Accordingly, when the tenth transistor T10 is turned on, the initialization voltage VINT may be stably applied to the gate electrode of the eighth transistor T8 regardless of the threshold voltage of the tenth transistor T10.

The tenth transistor T10 may include a plurality of transistors connected in series with each other. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. Accordingly, the voltage of the gate electrode of the eighth transistor T8 may be prevented or substantially prevented from leaking through the tenth transistor T10. A gate electrode of the fifth sub-transistor T101 may be connected to the kth scan initialization line GILk, a first electrode of the fifth sub-transistor T101 may be connected to a gate electrode of the eighth transistor T8, and a second electrode of the fifth sub-transistor T101 may be connected to a first electrode of the sixth sub-transistor T102. A gate electrode of the sixth sub-transistor T102 may be connected to the kth scan initialization line GILk, a first electrode of the sixth sub-transistor T102 may be connected to a second electrode of the fifth sub-transistor T101, and a second electrode of the sixth sub-transistor T102 may be connected to the initialization voltage line VIL.

The eleventh transistor T11 is turned on by the kth scanning write signal of the kth scanning write line GWLk to connect the gate electrode and the second electrode of the eighth transistor T8 to each other. Accordingly, during a period in which the eleventh transistor T11 is turned on, the eighth transistor T8 may operate as a diode. In other words, the eleventh transistor T11 may be turned on to diode-connect the eighth transistor T8.

The eleventh transistor T11 may include a plurality of transistors connected in series with each other. For example, the eleventh transistor T11 may include a seventh sub-transistor T111 and an eighth sub-transistor T112. Accordingly, the voltage of the gate electrode of the eighth transistor T8 may be prevented or substantially prevented from leaking through the eleventh transistor T11. A gate electrode of the seventh sub-transistor T111 may be connected to the kth scanning write line GWLk, a first electrode of the seventh sub-transistor T111 may be connected to a second electrode of the eighth transistor T8, and a second electrode of the seventh sub-transistor T111 may be connected to a first electrode of the eighth sub-transistor T112. A gate electrode of the eighth sub-transistor T112 may be connected to the kth scanning write line GWLk, a first electrode of the eighth sub-transistor T112 may be connected to a second electrode of the seventh sub-transistor T111, and a second electrode of the eighth sub-transistor T112 may be connected to a gate electrode of the eighth transistor T8.

The twelfth transistor T12 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the first electrode of the eighth transistor T8 to the second power line VDL2. A gate electrode of the twelfth transistor T12 may be connected to the kth PWM emission line PWELk, a first electrode of the twelfth transistor T12 may be connected to the second power line VDL2, and a second electrode of the twelfth transistor T12 may be connected to a first electrode of the eighth transistor T8.

The thirteenth transistor T13 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the first power line VDL1 to the second node N2. A gate electrode of the thirteenth transistor T13 may be connected to the kth scanning control line GCLk, a first electrode of the thirteenth transistor T13 may be connected to the first power line VDL1, and a second electrode of the thirteenth transistor T13 may be connected to the second node N2.

The fourteenth transistor T14 is turned on by the kth PWM emission signal of the kth PWM emission line PWELk to connect the second power line VDL2 to the second node N2. Accordingly, when the fourteenth transistor T14 is turned on, the second source voltage VDD2 of the second power line VDL2 may be supplied to the second node N2. A gate electrode of the fourteenth transistor T14 may be connected to the kth PWM emission line PWELk, a first electrode of the fourteenth transistor T14 may be connected to the second power line VDL2, and a second electrode of the fourteenth transistor T14 may be connected to the second node N2.

The second capacitor PC2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor PC2 may be connected to the gate electrode of the eighth transistor T8, and the other electrode of the second capacitor PC2 may be connected to the second node N2.

The second node N2 may be a contact point between the second electrode of the thirteenth transistor T13, the second electrode of the fourteenth transistor T14, and the other electrode of the second capacitor PC2.

The third pixel driving unit PDU3 adjusts a period in which the driving current Ids is supplied to the light emitting element EL according to the voltage of the third node N3.

The third pixel driving unit PDU3 may include fifteenth to nineteenth transistors T15 to T19 and a third capacitor PC3.

The fifteenth transistor T15 is turned on or off according to the voltage of the third node N3. When the fifteenth transistor T15 is turned on, the driving current Ids of the eighth transistor T8 may be supplied to the light emitting element EL, and when the fifteenth transistor T15 is turned off, the driving current Ids of the eighth transistor T8 may not be supplied to the light emitting element EL. Therefore, the turn-on period of the fifteenth transistor T15 may be the same as or substantially the same as the emission period of the light emitting element EL. A gate electrode of the fifteenth transistor T15 may be connected to the third node N3, a first electrode of the fifteenth transistor T15 may be connected to a second electrode of the eighth transistor T8, and a second electrode of the fifteenth transistor T15 may be connected to a first electrode of the seventeenth transistor T17.

The sixteenth transistor T16 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the third node N3. Accordingly, during a period in which the sixteenth transistor T16 is turned on, the third node N3 may be discharged to the initialization voltage VINT of the initialization voltage line VIL.

The sixteenth transistor T16 may include a plurality of transistors connected in series to each other. For example, the sixteenth transistor T16 may include a ninth sub-transistor T161 and a tenth sub-transistor T162. Accordingly, the voltage of the third node N3 may be prevented or substantially prevented from leaking through the sixteenth transistor T16. A gate electrode of the ninth sub-transistor T161 may be connected to the kth scan control line GCLk, a first electrode of the ninth sub-transistor T161 may be connected to the third node N3, and a second electrode of the ninth sub-transistor T161 may be connected to a first electrode of the tenth sub-transistor T162. A gate electrode of the tenth sub-transistor T162 may be connected to the kth scan control line GCLk, a first electrode of the tenth sub-transistor T162 may be connected to a second electrode of the ninth sub-transistor T161, and a second electrode of the tenth sub-transistor T162 may be connected to the initialization voltage line VIL.

The seventeenth transistor T17 is turned on by the kth PAM emission signal of the kth PAM emission line PAELk to connect the second electrode of the fifteenth transistor T15 to the first electrode of the light emitting element EL. A gate electrode of the seventeenth transistor T17 may be connected to the kth PAM emission line PAELk, a first electrode of the seventeenth transistor T17 may be connected to the second electrode of the fifteenth transistor T15, and a second electrode of the seventeenth transistor T17 may be connected to the first electrode of the light emitting element EL.

The eighteenth transistor T18 is turned on by the kth scan control signal of the kth scan control line GCLk to connect the initialization voltage line VIL to the first electrode of the light emitting element EL. Accordingly, during a period in which the eighteenth transistor T18 is turned on, the first electrode of the light emitting element EL may be discharged to the initialization voltage VINT of the initialization voltage line VIL. A gate electrode of the eighteenth transistor T18 may be connected to the kth scanning control line GCLk, a first electrode of the eighteenth transistor T18 may be connected to a first electrode of the light emitting element EL, and a second electrode of the eighteenth transistor T18 may be connected to the initialization voltage line VIL.

The nineteenth transistor T19 is turned on by the test signal of the test signal line TSTL to connect the first electrode of the light emitting element EL to the third power line VSL. A gate electrode of the nineteenth transistor T19 may be connected to the test signal line TSTL, a first electrode of the nineteenth transistor T19 may be connected to a first electrode of the light emitting element EL, and a second electrode of the nineteenth transistor T19 may be connected to the third power line VSL.

The third capacitor PC3 may be disposed between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor PC3 may be connected to the third node N3, and the other electrode of the third capacitor PC3 may be connected to the initialization voltage line VIL.

The third node N3 may be a contact point between the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one electrode of the third capacitor PC3.

Any one of the first electrode and the second electrode of each of the first to nineteenth transistors T1 to T19 may be a source electrode, and the other one of the first electrode and the second electrode of each of the first to nineteenth transistors T1 to T19 may be a drain electrode. The active layer of each of the first to nineteenth transistors T1 to T19 may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the active layer of each of the first to nineteenth transistors T1 to T19 is formed of polysilicon, the active layer of each of the first to nineteenth transistors T1 to T19 may be formed through a Low Temperature Polysilicon (LTPS) process.

In addition, although fig. 2 illustrates that each of the first to nineteenth transistors T1 to T19 is formed as a P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the present disclosure is not limited thereto. For example, each of the first to nineteenth transistors T1 to T19 may be alternatively formed as an N-type MOSFET.

As another example, in order to increase the black expression capability of the light emitting element EL by blocking the leakage current, the first and second sub-transistors T31 and T32 of the third transistor T3, the third and fourth sub-transistors T41 and T42 of the fourth transistor T4, the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10, and the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 in the first sub-pixel RP may be formed as N-type MOSFETs. In this case, the gate electrodes of the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 and the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be connected to the kth control line. The kth scan initialization signal and the kth control signal of the kth control line may have a pulse generated as the gate off voltage VGH. In addition, the active layers of the first and second sub-transistors T31 and T32 of the third transistor T3, the third and fourth sub-transistors T41 and T42 of the fourth transistor T4, the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10, and the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and the active layers of the other transistors may be formed of polysilicon.

As another example, any one of the first and second sub-transistors T31 and T32 of the third transistor T3 may be formed as an N-type MOSFET, and the other one of the first and second sub-transistors T31 and T32 of the third transistor T3 may be formed as a P-type MOSFET. In this case, a transistor formed as an N-type MOSFET among the first and second sub-transistors T31 and T32 of the third transistor T3 may be formed of an oxide semiconductor, and a transistor formed as a P-type MOSFET among the first and second sub-transistors T31 and T32 of the third transistor T3 may be formed of polysilicon.

As another example, any one of the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 may be formed as an N-type MOSFET, and the other one of the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 may be formed as a P-type MOSFET. In this case, a transistor formed as an N-type MOSFET among the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 may be formed of an oxide semiconductor, and a transistor formed as a P-type MOSFET among the third and fourth sub-transistors T41 and T42 of the fourth transistor T4 may be formed of polysilicon.

As another example, any one of the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10 may be formed as an N-type MOSFET, and the other one of the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10 may be formed as a P-type MOSFET. In this case, a transistor formed as an N-type MOSFET among the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10 may be formed of an oxide semiconductor, and a transistor formed as a P-type MOSFET among the fifth and sixth sub-transistors T101 and T102 of the tenth transistor T10 may be formed of polysilicon.

As another example, any one of the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed as an N-type MOSFET, and the other one of the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed as a P-type MOSFET. In this case, a transistor formed as an N-type MOSFET among the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed of an oxide semiconductor, and a transistor formed as a P-type MOSFET among the seventh and eighth sub-transistors T111 and T112 of the eleventh transistor T11 may be formed of polysilicon.

The circuits of the second subpixel GP and the third subpixel BP may be the same or substantially the same as the circuits of the first subpixel RP described above with reference to fig. 2, and thus, redundant description thereof will not be repeated.

Fig. 3 shows graphs respectively showing the wavelength of light emitted from the light emitting element of the first sub-pixel, the wavelength of light emitted from the light emitting element of the second sub-pixel, and the wavelength of light emitted from the light emitting element of the third sub-pixel depending on the driving current according to the embodiment.

In fig. 3, graph (a) shows the wavelength of light emitted from the light-emitting element EL of the first subpixel RP depending on the driving current Ids applied to the light-emitting element EL of the first subpixel RP when the light-emitting element EL of the first subpixel RP includes, for example, an inorganic material such as GaN. In fig. 3, graph (b) shows the wavelength of light emitted from the light emitting element EL of the second subpixel GP depending on the driving current Ids applied to the light emitting element EL of the second subpixel GP when the light emitting element EL of the second subpixel GP includes, for example, an inorganic material such as GaN. In fig. 3, graph (c) shows the wavelength of light emitted from the light emitting element EL of the third subpixel BP, which is applied to the driving current Ids of the light emitting element EL of the third subpixel BP when the light emitting element EL of the third subpixel BP includes, for example, an inorganic material such as GaN. In each of the graphs (a), (b), and (c) of fig. 3, the X-axis represents the drive current Ids, and the Y-axis represents the wavelength of light emitted from the light emitting element EL.

Referring to graph (a) in fig. 3, when the driving current Ids applied to the light emitting element EL of the first subpixel RP is 1 μ a to 300 μ a, the wavelength of light emitted from the light emitting element EL of the first subpixel RP is about 618nm and is constant or substantially constant. As the drive current Ids applied to the light emitting element EL of the first subpixel RP increases from 300 μ a to 1000 μ a, the wavelength of light emitted from the light emitting element EL of the first subpixel RP increases from about 618nm to about 620nm.

Referring to graph (b) in fig. 3, when the driving current Ids applied to the light emitting element EL of the second subpixel GP is increased from 1 μ a to 1000 μ a, the wavelength of light emitted from the light emitting element EL of the second subpixel GP is decreased from about 536nm to about 520nm.

Referring to graph (c) in fig. 3, when the driving current Ids applied to the light emitting element EL of the third subpixel BP is increased from 1 μ a to 1000 μ a, the wavelength of light emitted from the light emitting element EL of the third subpixel BP is decreased from about 464nm to about 461nm.

Therefore, even if the drive current Ids changes, the wavelength of light emitted from the light-emitting element EL of the first subpixel RP and the wavelength of light emitted from the light-emitting element EL of the third subpixel BP hardly change. On the other hand, the wavelength of light emitted from the light emitting element EL of the second subpixel GP is inversely proportional to the driving current Ids. Therefore, when the driving current Ids applied to the light emitting element EL of the second subpixel GP is adjusted, the wavelength of light emitted from the light emitting element EL of the second subpixel GP may be changed, and the color coordinates of an image displayed by the display panel 100 may be changed.

Fig. 4 shows graphs respectively showing the light emitting efficiency of the light emitting element of the first sub-pixel, the light emitting efficiency of the light emitting element of the second sub-pixel, and the light emitting efficiency of the light emitting element of the third sub-pixel depending on the driving current according to the embodiment.

In fig. 4, graph (a) shows the luminous efficiency of the light-emitting element EL of the first subpixel RP in dependence on the drive current Ids applied to the light-emitting element EL of the first subpixel RP when the light-emitting element EL of the first subpixel RP includes (e.g., is made of) an inorganic material. In fig. 4, graph (b) shows the light emitting efficiency of the light emitting element EL of the second subpixel GP depending on the driving current Ids applied to the light emitting element EL of the second subpixel GP when the light emitting element EL of the second subpixel GP includes (e.g., is made of) an inorganic material. In fig. 4, graph (c) shows the light emission efficiency of the light emitting element EL of the third subpixel BP depending on the driving current Ids applied to the light emitting element EL of the third subpixel BP when the light emitting element EL of the third subpixel BP includes (e.g., is made of) an inorganic material.

Referring to graph (a) of fig. 4, when the driving current Ids applied to the light emitting element EL of the first subpixel RP is about 10 μ a, the light emitting efficiency of the light emitting element EL of the first subpixel RP is about 8.5cd/a. When the driving current Ids applied to the light emitting element EL of the first subpixel RP is about 50 μ a, the light emitting efficiency of the light emitting element EL of the first subpixel RP is about 18cd/a. In other words, when the driving current Ids applied to the light emitting element EL of the first subpixel RP is 50 μ a, the light emitting efficiency of the light emitting element EL of the first subpixel RP increases by about 2.1 times when compared with the case where the driving current Ids applied to the light emitting element EL of the first subpixel RP is 10 μ a.

Referring to graph (b) of fig. 4, when the driving current Ids applied to the light emitting element EL of the second subpixel GP is about 10 μ a, the light emitting efficiency of the light emitting element EL of the second subpixel GP is about 72cd/a. When the driving current Ids applied to the light emitting element EL of the second subpixel GP is about 50 μ a, the light emitting efficiency of the light emitting element EL of the second subpixel GP is about 80cd/a. In other words, when the driving current Ids applied to the light emitting element EL of the second subpixel GP is 50 μ a, the light emitting efficiency of the light emitting element EL of the second subpixel GP is increased by about 1.1 times, when compared with the case where the driving current Ids applied to the light emitting element EL of the second subpixel GP is 10 μ a.

Referring to graph (c) of fig. 4, when the driving current Ids applied to the light emitting element EL of the third subpixel BP is about 10 μ a, the light emitting efficiency of the light emitting element EL of the third subpixel BP is about 13.2cd/a. When the driving current Ids applied to the light emitting element EL of the third subpixel BP is about 50 μ a, the light emitting efficiency of the light emitting element EL of the third subpixel BP is about 14cd/a. In other words, when the drive current Ids applied to the light-emitting element EL of the third subpixel BP is 50 μ a, the light-emitting efficiency of the light-emitting element EL of the third subpixel BP increases by about 1.06 times when compared with the case where the drive current Ids applied to the light-emitting element EL of the third subpixel BP is 10 μ a.

Accordingly, the light emission efficiency of the light emitting element EL of the first subpixel RP, the light emission efficiency of the light emitting element EL of the second subpixel GP, and the light emission efficiency of the light emitting element EL of the third subpixel BP may vary depending on the driving current Ids.

As shown in fig. 3 and 4, when the driving current Ids applied to the light emitting element EL of the second subpixel GP is adjusted, the color coordinates of an image displayed by the display panel 100 may change. In addition, the light emission efficiency of the light emitting element EL of the first subpixel RP, the light emission efficiency of the light emitting element EL of the second subpixel GP, and the light emission efficiency BP of the light emitting element EL of the third subpixel BP may vary depending on the driving current Ids. Accordingly, the driving current Ids may be fixed or substantially fixed (e.g., may be constant or substantially constant) such that the color coordinates of the image displayed by the display panel 100 are constantly or substantially constantly maintained and the light emitting elements EL of the first subpixel RP, the second subpixel GP, and the third subpixel BP have improved or optimal light emitting efficiency.

Thus, as shown in fig. 2, the first subpixel RP may adjust the luminance of light emitted from the light-emitting element EL by supplying the driving current Ids to the light-emitting element EL thereof such that the light-emitting element EL of the first subpixel RP is driven at an increased or optimized light-emitting efficiency according to the first PAM data voltage of the first PAM data line RDL and by adjusting the duty cycle of the light-emitting element EL (or in other words, adjusting the emission period of the light-emitting element EL). In addition, the second subpixel GP may adjust the luminance of light emitted from the light-emitting element EL by supplying the driving current Ids to the light-emitting element EL thereof such that the light-emitting element EL of the second subpixel GP is driven at an increased or optimized light-emitting efficiency according to the second PAM data voltage of the second PAM data line GDL and by adjusting the duty ratio of the light-emitting element EL (or in other words, adjusting the emission period of the light-emitting element EL). Further, the third subpixel BP may adjust the luminance of light emitted from the light-emitting element EL by supplying the driving current Ids to the light-emitting element EL thereof such that the light-emitting element EL of the third subpixel BP is driven at an increased or optimized light-emitting efficiency according to the third PAM data voltage of the third PAM data line BDL and by adjusting the duty ratio of the light-emitting element EL (or in other words, adjusting the emission period of the light-emitting element EL).

Accordingly, deterioration in image quality due to a change in the wavelength of the emitted light depending on the drive current Ids applied to the light emitting element EL can be reduced or prevented. In addition, each of the light emitting element EL of the first subpixel RP, the light emitting element EL of the second subpixel GP, and the light emitting element EL of the third subpixel BP may emit light with improved or optimized light emitting efficiency.

Fig. 5 is a schematic diagram illustrating an operation of the display apparatus during the nth to N +2 th frame periods.

Referring to fig. 5, each of the N-th to N + 2-th frame periods may include an active period ACT and a blank period VB, where N is a natural number greater than zero. The active period ACT may include a data address period ADDR in which data voltages and first/second/third PAM data voltages are supplied to respective some of the first to third subpixels RP, GP and BP and a plurality of emission periods EP1, EP2, EP3, EP4, EP5, \ 8230 \ 8230 \, EPn in which the light emitting elements EL of the respective subpixels RP, GP and BP emit light, where n is a natural number greater than zero. The blank period VB may be a period in which the subpixels RP, GP, and BP of the display panel 100 are idle without performing a specific operation.

The data address period ADDR and the first transmission period EP1 may be about five horizontal periods, and each of the second to nth transmission periods EP2, EP3, EP4, EP5, \8230;, EPn may be about twelve horizontal periods, but the present disclosure is not limited thereto. In addition, the active period ACT may include 25 emission periods, but the number of emission periods EP1, EP2, EP3, EP4, EP5, \8230;, EPn included in the active period ACT is not limited thereto.

During the data address period ADDR, the subpixels RP, GP and BP of the display panel 100 may sequentially receive a data voltage and first/second/third PAM data voltages for each row line. For example, the subpixels RP, GP and BP disposed in the first row line to the subpixels RP, GP and BP disposed in the nth row line corresponding to the last row line may sequentially receive the data voltage and the first/second/third PAM data voltages.

In each of the plurality of emission periods EP1, EP2, EP3, EP4, EP5, \8230;, EPn, the subpixels RP, GP, and BP of the display panel 100 may sequentially emit light for each row line. For example, the subpixels RP, GP, and BP disposed in the first row line to the subpixels RP, GP, and BP disposed in the last row line may sequentially emit light.

Fig. 6 is another schematic diagram illustrating an operation of the display apparatus during the nth to N +2 th frame periods.

The embodiment of fig. 6 differs from the embodiment of fig. 5 in that: in fig. 6, in each of a plurality of emission periods EP1, EP2, EP3, EP4, \8230;, EPn, sub-pixels RP, GP, and BP of the display panel 100 may emit light concurrently with each other (e.g., may be simultaneous with each other). Otherwise, the embodiment of fig. 6 may be the same or substantially the same as the embodiment of fig. 5, and thus, redundant description thereof will not be repeated.

Fig. 7 is a waveform diagram illustrating a scan initialization signal, a scan write signal, a scan control signal, a PWM emission signal, a PAM emission signal, and a frequency sweep signal applied to subpixels disposed in k-th to k + 5-th row lines during an nth frame period.

Referring to fig. 7, the subpixels RP, GP and BP disposed in the kth row line refer to subpixels RP, GP and BP connected to the kth scanning initialization line GILk, the kth scanning write line GWLk, the kth scanning control line GCLk, the kth PWM emission line PWELk, the kth PAM emission line PAELk, and the kth scanning signal line SWPLk. The kth scan initialization signal GIk refers to a signal applied to the kth scan initialization line GILk, and the kth scan write signal GWk refers to a signal applied to the kth scan write line GWLk. The kth scan control signal GCk refers to a signal applied to the kth scan control line GCLk, and the kth PWM emission signal PWEMk refers to a signal applied to the kth PWM emission line PWELk. The k PAM transmit signal PAEMk refers to a signal applied to the k PAM transmit line PAELk, and the k sweep signal SWPk refers to a signal applied to the k sweep signal line SWPLk.

The scan initialization signals GIk to GIk +5, the scan write signals GWk to GWk +5, the scan control signals GCk to GCk +5, the PWM emission signals PWEMk to PWEMk +5, the PAM emission signals PAEMk to PAEMk +5, and the sweep frequency signals SWPk to SWPk +5 may be sequentially shifted by one horizontal period (1H). The kth scan write signal GWk may be a signal shifted from the kth scan initialization signal GIk by one horizontal period, and the (k + 1) th scan write signal GWk +1 may be a signal shifted from the (k + 1) th scan initialization signal GIk +1 by one horizontal period. In this case, the k +1 th scan initialization signal GIk +1 may be a signal shifted from the k-th scan initialization signal GIk by one horizontal period, and thus, the k-th scan write signal GWk and the k +1 th scan initialization signal GIk +1 may be identical or substantially identical to each other.

Fig. 8 is a waveform diagram illustrating a kth scan initialization signal, a kth scan write signal, a kth scan control signal, a kth PWM emission signal, a kth PAM emission signal, and a kth sweep signal applied to each of subpixels disposed in a kth row line during an nth frame period, a voltage of a third node of a first subpixel, and a period in which a driving current is applied to a light emitting element.

Referring to fig. 8, the kth scan initialization signal GIk is a signal for controlling turn-on and turn-off of the third transistor T3 and the tenth transistor T10 of each of the sub-pixels RP, GP, and BP. The k-th scan write signal GWk is a signal for controlling the turn-on and turn-off of the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the eleventh transistor T11 of each of the sub-pixels RP, GP, and BP. The kth scan control signal GCk is a signal for controlling the turn-on and turn-off of the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 of each of the sub-pixels RP, GP, and BP. The kth PWM emission signal PWEMk is a signal for controlling the turn-on and turn-off of the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14. The kth PAM emission signal PAEMk is a signal for controlling the seventeenth transistor T17 to be turned on and off. The kth scan initialization signal GIk, the kth scan write signal GWk, the kth scan control signal GCk, the kth PWM emission signal PWEMk, the kth PAM emission signal PAEMk, and the kth sweep signal SWPk may be generated with one frame period as a cycle.

The data address period ADDR includes first to fourth periods t1 to t4. The first and fourth periods t1 and t4 are a first initialization period in which the voltage of the third node N3 and the first electrode of the light emitting element EL are initialized. The second period T2 is a second initialization period in which the gate electrode of the first transistor T1 and the gate electrode of the eighth transistor T8 are initialized. The third period T3 is a period in which the data voltage Vdata of the jth data line DLj and the threshold voltage Vth1 of the first transistor T1 are sampled at the gate electrode of the first transistor T1 and the first PAM data voltage Rdata of the first PAM data line RDL and the threshold voltage Vth8 of the eighth transistor T8 are sampled at the gate electrode of the eighth transistor T8.

The first transmission period EP1 includes a fifth period t5 and a sixth period t6. The fifth period T5 is a period in which the control current Ic is applied to the third node N3, and the sixth period T6 is a period in which the turn-on period of the fifteenth transistor T15 is controlled according to the control current Ic and the driving current Ids is supplied to the light emitting element EL.

Each of the second to nth transmission periods EP2 to EPn includes seventh to ninth periods t7 to t9. The seventh period t7 is a third initialization period in which the voltage of the third node N3 is initialized, the eighth period t8 is the same or substantially the same period as the fifth period t5, and the ninth period t9 is the same or substantially the same period as the sixth period t6.

The transmission periods adjacent to each other among the first to nth transmission periods EP1 to EPn may be spaced apart from each other by about several to several tens of horizontal periods.

The kth scan initialization signal GIk may have the gate-on voltage VGL during the second period t2 and may have the gate-off voltage VGH during the other periods. The kth scan write signal GWk may have a gate-on voltage VGL during the third period t3 and may have a gate-off voltage VGH during other periods. The kth scan control signal GCk may have the gate-on voltage VGL during the first to fourth periods t1 to t4 and during the seventh period t7, and may have the gate-off voltage VGH during the other periods. The gate off voltage VGH may be a voltage having a level higher than that of the gate on voltage VGL, but the present disclosure is not limited thereto, and the gate off voltage VGH may be a voltage having a level lower than that of the gate on voltage VGL according to the type of the transistor.

The kth PWM emission signal PWEMk may have the gate-on voltage VGL during the fifth and sixth periods t5 and t6 and during the eighth and ninth periods t8 and t9, and may have the gate-off voltage VGH during the other periods. The kth PAM transmission signal PAEMk may have the gate-on voltage VGL during the sixth period t6 and during the ninth period t9, and may have the gate-off voltage VGH during other periods.

The k-th swept frequency signal SWPk may include a pulse having a triangular wave shape during the sixth period t6 and during the ninth period t9, and may have the gate off voltage VGH during the other periods. For example, the k sweep signal SWPk may include a pulse having a triangular waveform linearly decreasing from the gate-off voltage VGH to the gate-on voltage VGL during the sixth period t6 and increasing from the gate-on voltage VGL to the gate-off voltage VGH at the end of the sixth period t6.

The kth PWM emission signal PWEMk may have the gate-on voltage VGL during the fifth and sixth periods t5 and t6 and during the eighth and ninth periods t8 and t9, and may have the gate-off voltage VGH during the other periods. The kth PAM transmission signal PAEMk may have the gate-on voltage VGL during the sixth period t6 and during the ninth period t9, and may have the gate-off voltage VGH during other periods. The pulse width of the kth PWM transmit signal PWEMk may be greater than the pulse width of the kth frequency sweep signal SWPk. The pulse width of the kth PAM transmit signal PAEMk may be the same as the pulse width of the kth frequency sweep signal SWPk.

Fig. 9 to 12 are circuit diagrams illustrating operations of the first sub-pixel during the first period, the second period, the third period, and the sixth period.

Hereinafter, for convenience, the operation of the first subpixel RP during the first to ninth periods t1 to t9 will be described in more detail with reference to fig. 8 to 12.

First, as shown in fig. 9, during the first period T1, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on by the kth scan control signal GCk having the gate-on voltage VGL.

The gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1 due to the turn-on of the seventh transistor T7. Due to the turn-on of the thirteenth transistor T13, the first source voltage VDD1 of the first power line VDL1 is applied to the second node N2.

Due to the turn-on of the sixteenth transistor T16, the voltage of the third node N3 is initialized to the initialization voltage VINT of the initialization voltage line VIL. Due to the turn-on of the eighteenth transistor T18, the first electrode of the light emitting element EL is initialized to the initialization voltage VINT of the initialization voltage line VIL.

Next, as shown in fig. 10, during the second period T2, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 maintain the turn-on state by the kth scan control signal GCk having the gate-on voltage VGL. In addition, during the second period T2, the third and tenth transistors T3 and T10 are turned on by the kth scan initialization signal GIk having the gate-on voltage VGL.

The seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 are the same or substantially the same as those described above with reference to the first period T1.

Due to the turn-on of the third transistor T3, the gate electrode of the first transistor T1 is initialized to the initialization voltage VINT of the initialization voltage line VIL. In addition, due to the turn-on of the tenth transistor T10, the gate electrode of the eighth transistor T8 is initialized to the initialization voltage VINT of the initialization voltage line VIL.

In this case, the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, and thus, a phenomenon in which the amount of change in the voltage of the gate electrode of the first transistor T1 is reflected in the k-th swept frequency signal SWPk of the k-th swept frequency signal line SWPLk through the first capacitor PC1 so that the gate-off voltage VGH of the k-th swept frequency signal SWPk is changed may be prevented or substantially prevented.

Third, as shown in fig. 11, during the third period T3, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 maintain the turn-on state by the kth scan control signal GCk having the gate-on voltage VGL. In addition, during the third period T3, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the eleventh transistor T11 are turned on by the kth scan write signal GWk having the gate-on voltage VGL.

Due to the turn-on of the second transistor T2, the data voltage Vdata of the jth data line DLj is applied to the first electrode of the first transistor T1. Due to the turn-on of the fourth transistor T4, the gate electrode and the second electrode of the first transistor T1 are connected to each other, and thus, the first transistor T1 is driven as a diode.

In this case, a voltage (e.g., vgs1= VINT-Vdata) between the gate electrode and the first electrode of the first transistor T1 is greater than the threshold voltage Vth1 of the first transistor T1, and thus, the first transistor T1 forms a current path until the voltage Vgs1 between the gate electrode and the first electrode of the first transistor T1 reaches the threshold voltage Vth1. Accordingly, the voltage of the gate electrode of the first transistor T1 may be increased from "VINT" to "Vdata + Vth1". Since the first transistor T1 is formed as a P-type MOSFET, the threshold voltage Vth1 of the first transistor T1 may be less than 0V.

In addition, the gate-off voltage VGH of the gate-off voltage line VGHL is applied to the first node N1, and thus, a phenomenon in which the amount of change in the voltage of the gate electrode of the first transistor T1 is reflected in the k-th sweep signal SWPk of the k-th sweep signal line SWPLk through the first capacitor PC1 so that the gate-off voltage VGH of the k-th sweep signal SWPk is changed can be prevented or substantially prevented.

Due to the turn-on of the ninth transistor T9, the first PAM data voltage Rdata of the first PAM data line RDL is applied to the first electrode of the eighth transistor T8. Due to the turn-on of the eleventh transistor T11, the gate electrode and the second electrode of the eighth transistor T8 are connected to each other, and thus, the eighth transistor T8 is driven as a diode.

In this case, a voltage (e.g., vgs8= VINT-Rdata) between the gate electrode and the first electrode of the eighth transistor T8 is greater than the threshold voltage Vth8 of the eighth transistor T8, and thus, the eighth transistor T8 forms a current path until the voltage Vgs8 between the gate electrode and the first electrode of the eighth transistor T8 reaches the threshold voltage Vth8. Accordingly, the voltage of the gate electrode of the eighth transistor T8 may increase from "VINT" to "Rdata + Vth8".

Fourth, during the fourth period T4, the seventh transistor T7, the thirteenth transistor T13, the sixteenth transistor T16, and the eighteenth transistor T18 maintain the turn-on state by the kth scan control signal GCk having the gate-on voltage VGL.

Fifth, during a fifth period T5, the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are turned on by the kth PWM emission signal PWEMk having the gate-on voltage VGL.

Due to the conduction of the fifth transistor T5, the first source voltage VDD1 is applied to the first electrode of the first transistor T1. In addition, the second electrode of the first transistor T1 is connected to the third node N3 due to the turn-on of the sixth transistor T6. However, during the fifth period T5, the voltage of the gate electrode of the first transistor T1 (e.g., vdata + Vth 1) may be the same or substantially the same as the first source voltage VDD1, or may be higher than the first source voltage VDD1. Accordingly, the first transistor T1 may be turned off during the fifth period T5.

In addition, the first electrode of the eighth transistor T8 may be connected to the second power line VDL2 due to the turn-on of the twelfth transistor T12.

In addition, the second source voltage VDD2 of the second power line VDL2 is applied to the second node N2 due to the turn-on of the fourteenth transistor T14. When the second source voltage VDD2 of the second power line VDL2 is changed due to a voltage drop or the like, a voltage difference Δ V2 between the first source voltage VDD1 and the second source voltage VDD2 may be reflected in the voltage of the gate electrode of the eighth transistor T8 through the second capacitor PC2.

Due to the turn-on of the fourteenth transistor T14, the driving current Ids flowing according to the voltage (e.g., rdata + Vth 8) of the gate electrode of the eighth transistor T8 may be supplied to the fifteenth transistor T15. As expressed in equation 1, the driving current Ids may not depend on the threshold voltage Vth8 of the eighth transistor T8.

[ EQUATION 1 ]

Ids＝k′×(Vgs8-Vth8) ² ＝k′×(Rdata+Vth8-VDD2-Vth8) ² ＝k′×(Rdata-VDD2) ²

In equation 1, k' refers to a scaling coefficient determined by the structure and physical properties of the eighth transistor T8, vth8 refers to a threshold voltage of the eighth transistor T8, VDD2 refers to a second source voltage, and Rdata refers to a first PAM data voltage.

Sixthly, as shown in fig. 12, during a sixth period T6, the fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 maintain the turn-on state by the kth PWM emission signal PWEMk having the gate-on voltage VGL. As shown in fig. 12, during the sixth period T6, the seventeenth transistor T17 is turned on by the kth PAM emission signal PAEMk having the gate turn-on voltage VGL. During the sixth period t6, the k-th frequency sweep signal SWPk is linearly decreased from the gate-off voltage VGH to the gate-on voltage VGL.

The fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the fourteenth transistor T14 are the same or substantially the same as those described above with reference to the fifth period T5.

Due to the turn-on of the seventeenth transistor T17, the first electrode of the light emitting element EL may be connected to the second electrode of the fifteenth transistor T15.

During the sixth period T6, the k-th frequency sweep signal SWPk linearly decreases from the gate-off voltage VGH to the gate-on voltage VGL, and the change amount Δ V1 of the voltage of the k-th frequency sweep signal SWPk is reflected in the voltage of the gate electrode of the first transistor T1 through the first capacitor PC1, and thus, the voltage of the gate electrode of the first transistor T1 may be Vdata + Vth1- Δ V1. In other words, as the voltage of the kth frequency sweep signal SWPk linearly decreases during the sixth period T6, the voltage of the gate electrode of the first transistor T1 may linearly decrease.

As expressed in equation 2, during the sixth period T6, the control current Ic flowing according to the voltage (e.g., vdata + Vth1- Δ V1) of the gate electrode of the first transistor T1 may not depend on the threshold voltage Vth1 of the first transistor T1.

[ EQUATION 2 ]

Ids＝k″×(Vgs1-Vth1) ² ＝k″×(Vdata+Vth1-ΔV1-VDD1-Vth1) ² ＝k″×(Vdata-ΔV1-VDD1) ²

In equation 2, k ″ refers to a proportionality coefficient determined by the structure and physical properties of the first transistor T1, vth1 refers to a threshold voltage of the first transistor T1, VDD1 refers to a first source voltage, and Vdata refers to a data voltage.

The period in which the control current Ic is applied to the third node N3 may be changed depending on the magnitude of the data voltage Vdata applied to the first transistor T1. Accordingly, the voltage of the third node N3 is changed depending on the magnitude of the data voltage Vdata applied to the first transistor T1, and thus, the turn-on period of the fifteenth transistor T15 may be controlled. Therefore, the light emission period SET during which the driving current Ids is applied to the light emitting element EL during the sixth period T6 may be controlled by controlling the turn-on period of the fifteenth transistor T15.

When the data voltage Vdata applied to the gate electrode of the first transistor T1 is the PWM data voltage of the peak black gray level, the voltage of the gate electrode of the first transistor T1 may be lower than the first source voltage VDD1 of the voltage of the first electrode of the first transistor T1 throughout the sixth period T6 due to the decrease of the voltage of the k-th sweep signal SWPk. Accordingly, the first transistor T1 may be turned on throughout the sixth period T6. Accordingly, the control current Ic of the first transistor T1 flows to the third node N3 throughout the sixth period T6, and the voltage of the third node N3 may increase to the high level VH with the start of the sixth period T6. Therefore, the fifteenth transistor T15 may be turned off throughout the sixth period T6. Accordingly, the driving current Ids is not applied to the light emitting element EL during the sixth period t6, and thus, the light emitting element EL may not emit light during the sixth period t6.

On the other hand, when the data voltage Vdata applied to the gate electrode of the first transistor T1 is the PWM data voltage of the gray scale, the voltage of the gate electrode of the first transistor T1 may have a level higher than that of the first source voltage VDD1 during the first sub-period T61 and may have a level lower than that of the first source voltage VDD1 during the second sub-period T62 due to the decrease in the voltage of the k-th sweep signal SWPk. Accordingly, the first transistor T1 may be turned on during the second sub-period T62 of the sixth period T6. In this case, the control current Ic of the first transistor T1 flows to the third node N3 during the second sub-period T62, and thus, the voltage of the third node N3 may have the high level VH during the second sub-period T62. Accordingly, the fifteenth transistor T15 may be turned off during the second sub period T62. Accordingly, the driving current Ids may be applied to the light emitting element EL during the first sub-period t61, and the driving current Ids may not be applied to the light emitting element EL during the second sub-period t 62. In other words, the light emitting element EL can emit light during the first sub-period t61 which is a part of the sixth period t6. As the first subpixel RP exhibits a gray level close to the peak black gray level, the light emission period SET of the light emitting element EL may become shorter. As the first subpixel RP exhibits a gray level close to the peak white gray level, the light emission period SET of the light emitting element EL may become longer.

When the data voltage Vdata applied to the gate electrode of the first transistor T1 is the PWM data voltage of the peak white gray, the voltage of the gate electrode of the first transistor T1 may be higher than the first source voltage VDD1 during the sixth period T6 regardless of a decrease in the voltage of the k-th sweep signal SWPk. Accordingly, the first transistor T1 may be turned off throughout the sixth period T6. In this case, the control current Ic of the first transistor T1 does not flow to the third node N3 throughout the sixth period T6, and thus, the voltage of the third node N3 may be maintained or substantially maintained as the initialization voltage VINT. Accordingly, the fifteenth transistor T15 may be turned on throughout the sixth period T6. Accordingly, the driving current Ids may be applied to the light emitting element EL during the entire sixth period t6, and the light emitting element EL may emit light throughout the sixth period t6.

As described above, the light emission period SET of the light emitting element EL can be adjusted by adjusting the data voltage Vdata applied to the gate electrode of the first transistor T1. Therefore, the gray scale or luminance displayed by the first subpixel RP may be adjusted by adjusting the pulse width of the voltage applied to the first electrode of the light emitting element EL while maintaining or substantially maintaining the driving current Ids applied to the light emitting element EL constant or substantially constant, rather than by adjusting the magnitude of the driving current Ids applied to the light emitting element EL.

When the digital video data converted into the data voltage is 8-bit data, the digital video data converted into the data voltage of the peak black gray level may be 0, and the digital video data converted into the data voltage of the peak white gray level may be 255. In this case, the digital video data converted into the data voltage of the gray scale may be data other than 0 and 255 (e.g., may be data between 0 and 255).

In addition, the seventh, eighth and ninth periods t7, t8 and t9 of each of the second to nth transmission periods EP2 to EPn are the same as or substantially the same as the above-described first, fifth and sixth periods t1, t5 and t6, respectively. In other words, in each of the second to nth emission periods EP2 to EPn, after the voltage of the third node N3 is initialized, a period in which the driving current Ids generated according to the first PAM data voltage Rdata written to the gate electrode of the eighth transistor T8 is applied to the light emitting element EL may be adjusted based on the data voltage Vdata written to the gate electrode of the first transistor T1 during the data address period ADDR.

Since the test signal of the test signal line TSTL may be applied as the gate off voltage VGH during the active period ACT of the nth frame period, the nineteenth transistor T19 may be turned off during the active period ACT of the nth frame period.

The second subpixel GP and the third subpixel BP may operate in the same or substantially the same manner as the first subpixel RP described above with reference to fig. 8 to 12, and thus, redundant description thereof will not be repeated.

Fig. 13 is a block diagram illustrating a swept frequency signal driver according to an embodiment. In fig. 13, for convenience of illustration, the kth to kth + 6-th stages STAk to STAk +6 of the swept frequency signal driver 113 are shown, where k is a natural number greater than zero.

As used herein, "preceding stage" refers to a stage that precedes (e.g., precedes) a reference stage. For example, the previous stages of the (k + 1) -th stage STAk +1 refer to first to k-th stages, and the previous stages of the (k + 2) -th stage STAk +2 refer to first to k + 1-th stages.

Referring to fig. 13, the emission clock lines ECL1 and ECL2 and the sweep clock lines SWPCL1 to SWPCL6 may be disposed at one side (e.g., in or on) of the k-th to k + 6-th stages STAk to STAk +6. A transmit clock signal having sequentially delayed phases may be applied to the transmit clock lines ECL1 and ECL2. The frequency sweep clock signals having phases sequentially delayed may be applied to the frequency sweep clock lines SWPCL1 to SWPCL6. The first transmission control signal ECS1 described above with reference to fig. 1 may comprise a transmission clock signal and the frequency sweep control signal SWCS may comprise a frequency sweep clock signal. For convenience, two emission clock lines ECL1 and ECL2 and six sweep clock lines SWPCL1 to SWPCL6 are shown in fig. 13, but the number of emission clock lines and the number of sweep clock lines are not limited thereto.

The sweep signal driver 113 includes a plurality of stages STAk to STAk +6 connected to the sweep signal lines SWPLk to SWPLk +6 and the PWM emission lines PWELk to PWELk +6. For example, the kth stage STAk may output the kth frequency sweep signal to the kth frequency sweep signal line SWPLk, and may output the kth PWM emission signal to the kth PWM emission line PWELk. The (k + 1) th stage STAk +1 may output the (k + 1) th frequency sweep signal to the (k + 1) th frequency sweep signal line SWPLk +1, and may output the (k + 1) th PWM emission signal to the (k + 1) th PWM emission line PWELk +1.

Each of the plurality of stages STAk to STAk +6 includes a start terminal ST, a first clock terminal CT1, a second clock terminal CT2, a third clock terminal CT3, a first output terminal OUT1, and a second output terminal OUT2. The first clock terminal CT1 may be a first transmission clock terminal to which any one of the transmission clock signals of the transmission clock lines ECL1 and ECL2 is input, and the second clock terminal CT2 may be a second transmission clock terminal to which the other one of the transmission clock signals of the transmission clock lines ECL1 and ECL2 is input. The third clock terminal CT3 may be a swept clock terminal to which any one of the swept clock signals of the swept clock lines SWPCL1 to SWPCL6 is input.

The start terminal ST of each of the plurality of stages STAk to STAk6 may be connected to the start signal line or the second output terminal OUT2 of the previous stage. For example, the start signal line may be connected to the start terminal ST of the first stage which is the first stage of the swept signal driver 113. Accordingly, a start signal of the start signal line may be input to the start terminal ST of the first stage. In addition, as shown in fig. 13, the start terminal ST of the k +6 th stage STAk +6 may be connected to the second output terminal OUT2 of the k stage STAk. In this case, the kth PWM transmission signal output to the second output terminal OUT2 of the kth stage STAk may be input to the start terminal ST of the kth +6 stage STAk +6 as the previous stage bit signal.

The first clock terminal CT1 of each of the plurality of stages STAk to STAk +6 may be connected to any one of the transmission clock lines ECL1 and ECL2, and the second clock terminal CT2 of each of the plurality of stages STAk to STAk +6 may be connected to the other one of the transmission clock lines ECL1 and ECL2. The transmission clock lines ECL1 and ECL2 may be alternately connected to the first clock terminal CT1 of the plurality of stages STAk to STAk +6. For example, the first transmission clock line ECL1 may be connected to the first clock terminal CT1 of the kth stage STAk, the second transmission clock line ECL2 may be connected to the first clock terminal CT1 of the k +1 th stage STAk +1, the first transmission clock line ECL1 may be connected to the first clock terminal CT1 of the k +2 th stage STAk +2, the second transmission clock line ECL2 may be connected to the first clock terminal CT1 of the k +3 th stage STAk +3, and so on.

In addition, the transmission clock lines ECL1 and ECL2 may be alternately connected to the second clock terminal CT2 of the plurality of stages STAk to STAk +6. For example, the second transmission clock line ECL2 may be connected to the second clock terminal CT2 of the kth stage STAk, the first transmission clock line ECL1 may be connected to the second clock terminal CT2 of the k +1 th stage STAk +1, the second transmission clock line ECL2 may be connected to the second clock terminal CT2 of the k +2 th stage STAk +2, the first transmission clock line ECL1 may be connected to the second clock terminal CT2 of the k +3 th stage STAk +3, and so on.

The swept clock lines SWPCL1 to SWPCL6 may be alternately connected to the third clock terminal CT3 of the plurality of stages STAk to STAk +6. For example, the first sweep clock line SWPCL1 may be connected to the third clock terminal CT3 of the kth stage STAk, the second sweep clock line SWPCL2 may be connected to the third clock terminal CT3 of the (k + 1) th stage STAk +1, and the third sweep clock line SWPCL3 may be connected to the third clock terminal CT3 of the (k + 2) th stage STAk + 2. In addition, the fourth frequency sweep clock line SWPCL4 may be connected to the third clock terminal CT3 of the (k + 3) th stage STAk +3, the fifth frequency sweep clock line SWPCL5 may be connected to the third clock terminal CT3 of the (k + 4) th stage STAk +4, and the sixth frequency sweep clock line SWPCL6 may be connected to the third clock terminal CT3 of the (k + 5) th stage STAk + 5. Further, the first scan clock line SWPCL1 may be connected to the third clock terminal CT3 of the (k + 6) th stage STAk +6.

The first output terminal OUT1 of each of the plurality of stages STAk to STAk +6 is connected to a corresponding one of the sweep signal lines SWPLk to SWPLk +6 to output the sweep signal, and the second output terminal OUT2 of each of the plurality of stages STAk to STAk +6 is connected to a corresponding one of the PWM emission lines PWELk to PWELk +6 to output the PWM emission signal. For example, as shown in fig. 13, the first output terminal OUT1 of the kth stage STAk may be connected to the kth swept signal line SWPLk to output the kth swept signal, and the second output terminal OUT2 of the kth stage STAk may be connected to the kth PWM emission line PWELk to output the kth PWM emission signal. In addition, a first output terminal OUT1 of the (k + 1) th stage STAk +1 may be connected to the (k + 1) th sweep signal line SWPLk +1 to output a (k + 1) th sweep signal, and a second output terminal OUT2 of the (k + 1) th stage STAk +1 may be connected to the (k + 1) th PWM transmission line PWELk +1 to output a (k + 1) th PWM transmission signal.

As shown in fig. 13, one stage in the sweep signal driver 113 may output the sweep signal and the PWM transmission signal concurrently (e.g., may be simultaneous), and thus, the area of the scan driver 110 may be reduced.

Fig. 14 is a circuit diagram illustrating a kth stage of a swept frequency signal driver according to an embodiment.

Referring to fig. 14, the k-th stage STAk includes a start terminal ST, a first clock terminal CT1, a second clock terminal CT2, a third clock terminal CT3, a gate-on voltage terminal VGLT, a gate-off voltage terminal VGHT, a first output terminal OUT1, and a second output terminal OUT2. The gate-on voltage is applied to the gate-on voltage terminal VGLT, and the gate-off voltage is applied to the gate-off voltage terminal VGHT. The gate-off voltage may be a voltage having a higher level than that of the gate-on voltage. Since the kth stage STAk is shown in more detail in fig. 14, it will be mainly described that the first transmission clock signal of the first transmission clock line ECL1 is input to the first clock terminal CT1, the second transmission clock signal of the second transmission clock line ECL2 is input to the second clock terminal CT2, and the first scan clock signal of the first scan clock line SWPCL1 is input to the third clock terminal CT3, but the present disclosure is not limited thereto, and those of ordinary skill in the art will understand that appropriate modifications may be made on the basis of, for example, the stages STAk +1 to STAk +6 of the scan signal driver 113 as shown in fig. 13.

In addition, the kth stage STAk includes a first output unit (e.g., a first output circuit) 1131, a second output unit (e.g., a second output circuit) 1132, a pull-up node control unit (e.g., a pull-up node control circuit) 1133, a first control node control unit (e.g., a first control node control circuit) 1134, a second control node control unit (e.g., a second control node control circuit) 1135, a pull-down node control unit (e.g., a pull-down node control circuit) 1136, and a node connection unit (e.g., a node connection circuit) 1137.

When the third pull-up node Q3 has the gate-on voltage, the first output unit 1131 outputs the swept clock signal input to the third clock terminal CT3 to the first output terminal OUT1. In addition, when the pull-down node QB has the gate-on voltage, the first output unit 1131 outputs the gate-off voltage of the gate-off voltage terminal VGHT to the first output terminal OUT1. The first output unit 1131 may include a first pull-up transistor PU1, a first pull-down transistor PD1, and a first capacitor C1.

The first, second, and third pull-up nodes Q1, Q2, and Q3 may be electrically connected to each other. On the other hand, the pull-down node QB may be electrically disconnected from the first, second, and third pull-up nodes Q1, Q2, and Q3.

The first pull-up transistor PU1 is turned on by the gate-on voltage of the third pull-up node Q3 to output the swept frequency clock signal input to the third clock terminal CT3 to the first output terminal OUT1. A gate electrode of the first pull-up transistor PU1 may be connected to the third pull-up node Q3, a first electrode of the first pull-up transistor PU1 may be connected to the first output terminal OUT1, and a second electrode of the first pull-up transistor PU1 may be connected to the third clock terminal CT3.

In order to increase the amount of current flowing through the channel of the first pull-up transistor PU1 when the first pull-up transistor PU1 is turned on, the first pull-up transistor PU1 may further include a second gate electrode electrically connected to the third pull-up node Q3. In this case, the first pull-up transistor PU1 may be formed as a dual gate structure including a first gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

The first pull-down transistor PD1 is turned on by the gate-on voltage of the pull-down node QB to output the gate-off voltage input to the gate-off voltage terminal VGHT to the first output terminal OUT1. A gate electrode of the first pull-down transistor PD1 may be connected to the pull-down node QB, a first electrode of the first pull-down transistor PD1 may be connected to the gate off voltage terminal VGHT, and a second electrode of the first pull-down transistor PD1 may be connected to the first output terminal OUT1.

In order to prevent or reduce leakage current flowing through the first pull-down transistor PD1, the first pull-down transistor PD1 may further include a second gate electrode connected to the gate off voltage terminal VGHT. In this case, the first pull-down transistor PD1 may be formed as a dual gate structure including a first gate electrode corresponding to the upper gate electrode and a second gate electrode corresponding to the lower gate electrode.

The first capacitor C1 is disposed between the third pull-up node Q3 and the first output terminal OUT1. One electrode of the first capacitor C1 may be connected to the third pull-up node Q3, and the other electrode of the first capacitor C1 may be connected to the first output terminal OUT1. Since the first capacitor C1 stores charges corresponding to a voltage difference between the third pull-up node Q3 and the first output terminal OUT1, a voltage difference between the third pull-up node Q3 and the first output terminal OUT1 may be maintained or substantially maintained as constant or substantially constant by the first capacitor C1.

The second output unit 1132 outputs the gate-on voltage of the gate-on voltage terminal VGLT to the second output terminal OUT2 when the second pull-up node Q2 has the gate-on voltage. The second output unit 1132 outputs the gate-off voltage of the gate-off voltage terminal VGHT to the second output terminal OUT2 when the pull-down node QB has the gate-on voltage. The second output unit 1132 may include a second pull-up transistor PU2 and a second pull-down transistor PD2.

The second pull-up transistor PU2 is turned on by the gate-on voltage of the second pull-up node Q2 to output the gate-on voltage of the gate-on voltage terminal VGLT to the second output terminal OUT2. A gate electrode of the second pull-up transistor PU2 may be connected to the second pull-up node Q2, a first electrode of the second pull-up transistor PU2 may be connected to the second output terminal OUT2, and a second electrode of the second pull-up transistor PU2 may be connected to the gate-on voltage terminal VGLT.

The second pull-down transistor PD2 is turned on by the gate-on voltage of the pull-down node QB to output the gate-off voltage of the gate-off voltage terminal VGHT to the second output terminal OUT2. A gate electrode of the second pull-down transistor PD2 may be connected to the pull-down node QB, a first electrode of the second pull-down transistor PD2 may be connected to the gate-off voltage terminal VGHT, and a second electrode of the second pull-down transistor PD2 may be connected to the second output terminal OUT2.

When the first transmit clock signal input to the first clock terminal CT1 has the gate-on voltage, the pull-up node control unit 1133 supplies the start signal or the previous stage bit signal input to the start terminal ST to the first pull-up node Q1. The pull-up node control unit 1133 may include a first switching transistor ST1.

The first switching transistor ST1 is turned on by a first transmission clock signal having a gate-on voltage input to the first clock terminal CT1 to connect the first pull-up node Q1 to the start terminal ST. A gate electrode of the first switching transistor ST1 may be connected to the first clock terminal CT1, a first electrode of the first switching transistor ST1 may be connected to the start terminal ST, and a second electrode of the first switching transistor ST1 may be connected to the first pull-up node Q1.

The first control node control unit 1134 supplies the gate-on voltage of the gate-on voltage terminal VGLT to the first control node CN1 when the first transmission clock signal input to the first clock terminal CT1 has the gate-on voltage. When the first pull-up node Q1 has the gate-on voltage, the first control node control unit 1134 supplies the first transmission clock signal input to the first clock terminal CT1 to the first control node CN1. The first control node control unit 1134 may include a second switching transistor ST2, a third switching transistor ST3, and a fourth switching transistor ST4.

The second switching transistor ST2 is turned on by the first transmit clock signal having the gate-on voltage input to the first clock terminal CT1 to connect the first control node CN1 to the gate-on voltage terminal VGLT. A gate electrode of the second switching transistor ST2 may be connected to the first clock terminal CT1, a first electrode of the second switching transistor ST2 may be connected to the first control node CN1, and a second electrode of the second switching transistor ST2 may be connected to the gate-on voltage terminal VGLT.

The third and fourth switching transistors ST3 and ST4 are turned on by the gate-on voltage of the first pull-up node Q1 to connect the first control node CN1 to the first clock terminal CT1. A gate electrode of the third switching transistor ST3 may be connected to the first pull-up node Q1, a first electrode of the third switching transistor ST3 may be connected to the first clock terminal CT1, and a second electrode of the third switching transistor ST3 may be connected to a first electrode of the fourth switching transistor ST4. A gate electrode of the fourth switching transistor ST4 may be connected to the first pull-up node Q1, a first electrode of the fourth switching transistor ST4 may be connected to a second electrode of the third switching transistor ST3, and a second electrode of the fourth switching transistor ST4 may be connected to the first control node CN1.

The second control node control unit 1135 supplies the gate-off voltage of the gate-off voltage terminal VGHT to the second control node CN2 when the first control node CN1 has the gate-on voltage. When the second pull-up node Q2 has the gate-on voltage, the second control node control unit 1135 supplies the second transmission clock signal input to the second clock terminal CT2 to the second control node CN2. The second control node control unit 1135 may include a fifth switching transistor ST5, a sixth switching transistor ST6, and a second capacitor C2.

The fifth switching transistor ST5 is turned on by the gate-on voltage of the first control node CN1 to connect the second control node CN2 to the gate-off voltage terminal VGHT. A gate electrode of the fifth switching transistor ST5 may be connected to the first control node CN1, a first electrode of the fifth switching transistor ST5 may be connected to the gate-off voltage terminal VGHT, and a second electrode of the fifth switching transistor ST5 may be connected to the second control node CN2.

The sixth switching transistor ST6 is turned on by the gate-on voltage of the second pull-up node Q2 to connect the second control node CN2 to the second clock terminal CT2. A gate electrode of the sixth switching transistor ST6 may be connected to the second pull-up node Q2, a first electrode of the sixth switching transistor ST6 may be connected to the second control node CN2, and a second electrode of the sixth switching transistor ST6 may be connected to the second clock terminal CT2.

The second capacitor C2 is disposed between the second pull-up node Q2 and the second control node CN2. One electrode of the second capacitor C2 may be connected to the second pull-up node Q2, and the other electrode of the second capacitor C2 may be connected to the second control node CN2. Since the second capacitor C2 stores charges corresponding to a voltage difference between the second pull-up node Q2 and the second control node CN2, the voltage difference between the second pull-up node Q2 and the second control node CN2 may be maintained or substantially maintained as constant or substantially constant by the second capacitor C2.

When the fourth control node CN4 has the gate-on voltage and the second transmit clock signal input to the second clock terminal CT2 has the gate-on voltage, the pull-down node control unit 1136 supplies the gate-on voltage of the second transmit clock signal input to the second clock terminal CT2 to the pull-down node QB. In addition, when the first pull-up node Q1 has the gate-on voltage, the pull-down node control unit 1136 supplies the gate-off voltage of the gate-off voltage terminal VGHT to the pull-down node QB. The pull-down node control unit 1136 may include a seventh switching transistor ST7, an eighth switching transistor ST8, a ninth switching transistor ST9, a third capacitor C3, and a fourth capacitor C4.

The seventh switching transistor ST7 is turned on by the gate-on voltage of the fourth control node CN4 to connect the second clock terminal CT2 to the third control node CN3. A gate electrode of the seventh switching transistor ST7 may be connected to the fourth control node CN4, a first electrode of the seventh switching transistor ST7 may be connected to the third control node CN3, and a second electrode of the seventh switching transistor ST7 may be connected to the second clock terminal CT2.

The eighth switching transistor ST8 is turned on by the gate-on voltage of the second transmit clock signal input to the second clock terminal CT2 to connect the pull-down node QB to the third control node CN3. A gate electrode of the eighth switching transistor ST8 may be connected to the second clock terminal CT2, a first electrode of the eighth switching transistor ST8 may be connected to the pull-down node QB, and a second electrode of the eighth switching transistor ST8 may be connected to the third control node CN3.

The ninth switching transistor ST9 is turned on by the gate-on voltage of the first pull-up node Q1 to connect the gate-off voltage terminal VGHT to the pull-down node QB. A gate electrode of the ninth switching transistor ST9 may be connected to the first pull-up node Q1, a first electrode of the ninth switching transistor ST9 may be connected to the gate-off voltage terminal VGHT, and a second electrode of the ninth switching transistor ST9 may be connected to the pull-down node QB.

The third capacitor C3 is disposed between the third control node CN3 and the fourth control node CN4. One electrode of the third capacitor C3 may be connected to the third control node CN3, and the other electrode of the third capacitor C3 may be connected to the fourth control node CN4. Because the third capacitor C3 stores a charge corresponding to the voltage difference between the third control node CN3 and the fourth control node CN4, the voltage difference between the third control node CN3 and the fourth control node CN4 may be maintained or substantially maintained constant or substantially constant by the third capacitor C3.

The fourth capacitor C4 is disposed between the pull-down node QB and the gate-off voltage terminal VGHT. One electrode of the fourth capacitor C4 may be connected to the pull-down node QB, and the other electrode of the fourth capacitor C4 may be connected to the gate-off voltage terminal VGHT. Since the fourth capacitor C4 stores charges corresponding to a voltage difference between the pull-down node QB and the gate off voltage terminal VGHT, the voltage difference between the pull-down node QB and the gate off voltage terminal VGHT may be maintained or substantially maintained as constant or substantially constant by the fourth capacitor C4.

The node connection unit 1137 connects the first pull-up node Q1 and the second pull-up node Q2 to each other, and connects the first pull-up node Q1 and the third pull-up node Q3 to each other. In addition, the node connection unit 1137 connects the first control node CN1 and the fourth control node CN4 to each other. The node connection unit 1137 includes a tenth switching transistor ST10, an eleventh switching transistor ST11, and a twelfth switching transistor ST12.

The tenth switching transistor ST10 may be disposed between the first and second pull-up nodes Q1 and Q2. A gate electrode of the tenth switching transistor ST10 may be connected to the gate-on voltage terminal VGLT, a first electrode of the tenth switching transistor ST10 may be connected to the first pull-up node Q1, and a second electrode of the tenth switching transistor ST10 may be connected to the second pull-up node Q2.

The eleventh switching transistor ST11 may be disposed between the first pull-up node Q1 and the third pull-up node Q3. A gate electrode of the eleventh switching transistor ST11 may be connected to the gate-on voltage terminal VGLT, a first electrode of the eleventh switching transistor ST11 may be connected to the first pull-up node Q1, and a second electrode of the eleventh switching transistor ST11 may be connected to the third pull-up node Q3.

The twelfth switching transistor ST12 may be disposed between the first control node CN1 and the fourth control node CN4. A gate electrode of the twelfth switching transistor ST12 may be connected to the gate-on voltage terminal VGLT, a first electrode of the twelfth switching transistor ST12 may be connected to the first control node CN1, and a second electrode of the twelfth switching transistor ST12 may be connected to the fourth control node CN4.

Fig. 14 shows that the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD, and the first to twelfth switching transistors ST1 to ST12 are formed as P-type MOSFETs. In this case, when the gate-on voltage is applied to their gate electrodes, the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the first to twelfth switching transistors ST1 to ST12 are turned on. The gate-on voltage may be a gate-low voltage and the gate-off voltage may be a gate-high voltage, but the present disclosure is not limited thereto, and the gate-on voltage and the gate-off voltage may be modified according to the type of the transistor.

Any one of the first electrode and the second electrode of each of the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the first to twelfth switching transistors ST1 to ST12 may be a source electrode, and another one of the first electrode and the second electrode of each of the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the first to twelfth switching transistors ST1 to ST12 may be a drain electrode.

In addition, the semiconductor layer of each of the first pull-up transistor PU1, the first pull-down transistor PD1, the second pull-up transistor PU2, the second pull-down transistor PD2, and the first to twelfth switching transistors ST1 to ST12 may be formed of amorphous silicon (a-Si), polycrystalline silicon (Poly-Si), or an oxide semiconductor.

Fig. 15 is a waveform diagram illustrating a start signal or a previous stage bit signal, a first transmit clock signal, a second transmit clock signal, and first to sixth frequency sweep clock signals applied to a kth stage, a voltage of a first pull-up node, a voltage of a second pull-up node, a voltage of a third pull-up node, and a voltage of a pull-down node of the kth stage, and a kth PWM transmit signal and a kth frequency sweep signal output from the kth stage according to an embodiment.

Fig. 15 shows the start signal VST or the previous stage bit signal CR, the first transmission clock signal ECK1, the second transmission clock signal ECK2, the first to sixth frequency sweep clock signals SWPCK1 to SWPCK6, the voltage VQ1 of the first pull-up node Q1, the voltage VQ2 of the second pull-up node Q2, the voltage VQ3 of the third pull-up node Q3, and the voltage VQB of the pull-down node QB of the kth stage STAk, the kth PWM transmission signal PWEMk, and the kth frequency sweep signal SWPk in the first transmission period EP1 and the second transmission period EP2 of the active period ACT of the nth frame period. In fig. 15, the first to sixth periods st1 to st6 of the first transmission period EP1 and the seventh and eighth periods st7 and st8 after the first transmission period EP1 are shown. In addition, the first and second transmission periods EP1 and EP2 have been shown in fig. 15, but the third to nth transmission periods EP3 to EPn may be the same as or substantially the same as (or similar to) those shown in fig. 15, and thus, redundant description thereof may not be repeated.

The start signal VST or the previous stage bit signal CR may be generated as the gate-on voltage VGL during the emission periods EP1 to EPn, and may be generated as the gate-off voltage VGH during other periods. In other words, the start signal VST or the previous stage bit signal CR may include a pulse having the gate-on voltage VGL in each of the emission periods EP1 to EPn.

The first transmission clock signal ECK1 and the second transmission clock signal ECK2 are clock signals having phases that are sequentially delayed. For example, the second transmission clock signal ECK2 may be a signal having a phase delayed by one horizontal period when compared with the first transmission clock signal ECK 1. The first transmission clock signal ECK1 and the second transmission clock signal ECK2 may be repeated with a cycle of two horizontal periods. Each of the first and second emission clock signals ECK1 and ECK2 may include pulses generated as the gate-on voltage VGL during one horizontal period or less. Fig. 15 shows that each of the first to eighth periods st1 to st8 is equal to one horizontal period (1H). One horizontal period (1H) refers to a period in which a data voltage and a PAM data voltage are applied to the sub-pixels RP, GP, and BP disposed in the first row line.

The first to sixth sweep clock signals SWPCK1 to SWPCK6 are signals having phases that are sequentially delayed. For example, the second swept frequency clock signal SWPCK2 may have a signal delayed by a phase of one horizontal period (1H) when compared to the first swept frequency clock signal SWPCK 1. The first to sixth frequency sweep clock signals SWPCK1 to SWPCK6 may be repeated with six horizontal periods (6H) as a cycle. Each of the first to sixth swept clock signals SWPCK1 to SWPCK6 may include a pulse linearly decreasing from the gate-off voltage VGH to the gate-on voltage VGL during five horizontal periods (5H).

Fig. 16 to 19 are circuit diagrams illustrating an operation of the kth stage during the first to eighth periods.

Hereinafter, the operation of the kth stage STAk during the first to eighth periods st1 to st8 will be described in more detail with reference to fig. 15 to 19.

First, as shown in fig. 15 and 16, during the first period ST1, the start signal VST having the gate-on voltage VGL or the previous stage bit signal CR may be input to the start terminal ST of the kth stage STAk, the first emission clock signal ECK1 having the gate-on voltage VGL may be input to the first clock terminal CT1 of the kth stage STAk, the second emission clock signal ECK2 having the gate-off voltage VGH may be input to the second clock terminal CT2 of the kth stage STAk, and the first scan clock signal SWPCK1 having the gate-off voltage VGH may be input to the third clock terminal CT3 of the kth stage STAk.

The first switching transistor ST1 is turned on by the first transmission clock signal ECK1 having the gate-on voltage VGL to connect the first pull-up node Q1 to the start terminal ST. Accordingly, the gate-on voltage VGL of the start signal VST or the previous stage bit signal CR may be supplied to the first pull-up node Q1.

The second switching transistor ST2 is turned on by the first transmission clock signal ECK1 having the gate-on voltage VGL to connect the first control node CN1 to the gate-on voltage terminal VGLT. Accordingly, the gate turn-on voltage VGL of the gate turn-on voltage terminal VGLT may be supplied to the first control node CN1.

The third and fourth switching transistors ST3 and ST4 are turned on by the gate-on voltage VGL of the first pull-up node Q1 to connect the first control node CN1 to the first clock terminal CT1. Accordingly, the gate-on voltage VGL of the first transmission clock signal ECK1 may be supplied to the first control node CN1.

The fifth switching transistor ST5 is turned on by the gate-on voltage VGL of the first control node CN1 to connect the gate-off voltage terminal VGHT to the second control node CN2. Accordingly, the gate off voltage VGH may be supplied to the second control node CN2.

The tenth switching transistor ST10 is turned on by the gate-on voltage VGL of the gate-on voltage terminal VGLT to connect the second pull-up node Q2 to the first pull-up node Q1. Accordingly, the gate-on voltage VGL of the first pull-up node Q1 may be supplied to the second pull-up node Q2.

The sixth switching transistor ST6 is turned on by the gate-on voltage VGL of the second pull-up node Q2 to connect the second clock terminal CT2 to the second control node CN2. Accordingly, the gate-off voltage VGH of the second emission clock signal ECK2 input to the second clock terminal CT2 may be supplied to the second control node CN2.

The twelfth switching transistor ST12 is turned on by the gate-on voltage VGL of the gate-on voltage terminal VGLT to connect the fourth control node CN4 to the first control node CN1. Accordingly, the gate-on voltage VGL of the first control node CN1 may be supplied to the fourth control node CN4.

The seventh switching transistor ST7 is turned on by the gate-on voltage VGL of the fourth control node CN4 to connect the third control node CN3 to the second clock terminal CT2. Accordingly, the gate off voltage VGH of the second emission clock signal ECK2 input to the second clock terminal CT2 may be supplied to the third control node CN3.

The ninth switching transistor ST9 is turned on by the gate-on voltage VGL of the first pull-up node Q1 to connect the pull-down node QB to the gate-off voltage terminal VGHT. Accordingly, the gate off voltage VGH of the gate off voltage terminal VGHT may be supplied to the pull-down node QB.

The eleventh switching transistor ST11 is turned on by the gate-on voltage VGL of the gate-on voltage terminal VGLT to connect the first pull-up node Q1 to the third pull-up node Q3. Accordingly, the gate-on voltage VGL of the first pull-up node Q1 may be supplied to the third pull-up node Q3.

The first pull-up transistor PU1 is turned on by the gate-on voltage VGL of the third pull-up node Q3 to connect the first output terminal OUT1 to the third clock terminal CT3. Accordingly, the first scan clock signal SWPCK1 input to the third clock terminal CT3 may be supplied to the first output terminal OUT1.

The second pull-up transistor PU2 is turned on by the gate-on voltage VGL of the second pull-up node Q2 to connect the second output terminal OUT2 to the gate-on voltage terminal VGLT. Accordingly, the gate-on voltage VGL of the gate-on voltage terminal VGLT may be supplied to the second output terminal OUT2.

During the first period ST1, the eighth switching transistor ST8, the first pull-down transistor PD1, and the second pull-down transistor PD2 may be turned off.

Second, as shown in fig. 15 and 17, during the second period ST2, the start signal VST having the gate-on voltage VGL or the previous stage bit signal CR may be input to the start terminal ST of the kth stage STAk, the first emission clock signal ECK1 having the gate-off voltage VGH may be input to the first clock terminal CT1 of the kth stage STAk, the second emission clock signal ECK2 having the gate-on voltage VGL may be input to the second clock terminal CT2 of the kth stage STAk, and the first scan clock signal SWPCK1 having the gate-off voltage VGH may be input to the third clock terminal CT3 of the kth stage STAk.

The third and fourth switching transistors ST3 and ST4 are turned on by the gate-on voltage VGL of the first pull-up node Q1 to connect the first control node CN1 to the first clock terminal CT1. Accordingly, the gate-off voltage VGH of the first transmission clock signal ECK1 may be supplied to the first control node CN1.

The sixth switching transistor ST6 is turned on by the gate-on voltage VGL of the second pull-up node Q2 to connect the second clock terminal CT2 to the second control node CN2. Accordingly, the second transmission clock signal ECK2 input to the second clock terminal CT2 may be supplied to the second control node CN2. Accordingly, during the second period st2, the pulse of the second transmission clock signal ECK2 supplied to the second control node CN2 may be reflected in the voltage of the second pull-up node Q2 through the second capacitor C2. In other words, the amount of change in voltage due to the pulse of the second transmission clock signal ECK2 may be reflected in the voltage of the second pull-up node Q2 through the second capacitor C2. Accordingly, during the second period st2, the voltage of the second pull-up node Q2 may be decreased to the second gate-on voltage VGL2 and then restored to the gate-on voltage VGL.

Since the first pull-up node Q1 is connected to the second pull-up node Q2 through the tenth switching transistor ST10, the voltage of the first pull-up node Q1 may be reduced to the third gate-on voltage VGL3, and then restored to the gate-on voltage VGL, similar to the voltage of the second pull-up node Q2. The third pull-up node Q3 is connected to the first pull-up node Q1 through the eleventh switching transistor ST11, but the gate-on voltage VGL of the third pull-up node Q3 does not fluctuate as much as the voltage of the first pull-up node Q1, so that the amount of change in the voltage of the first output terminal OUT1 can be reflected in the voltage of the third pull-up node Q3 through the first capacitor C1. Accordingly, the voltage of the third pull-up node Q3 may be gradually decreased, similar to the voltage of the first scan clock signal SWPCK 1.

The eighth switching transistor ST8 is turned on by the gate-on voltage VGL of the second emission clock signal ECK2 of the second clock terminal CT2 to connect the third control node CN3 to the pull-down node QB. In addition, the ninth switching transistor ST9 is turned on by the gate-on voltage VGL of the first pull-up node Q1 to connect the pull-down node QB to the gate-off voltage terminal VGHT. Accordingly, the gate off voltage VGH of the gate off voltage terminal VGHT may be supplied to the third control node CN3 and the pull-down node QB.

During the second period ST2, the first, second, fifth, seventh, and first pull-down transistors ST1, ST2, ST5, ST7, PD1, and PD2 may be turned off.

The operation of the kth stage STAk during the third and fifth periods st3 and st5 may be the same or substantially the same as the operation of the kth stage STAk during the first period st1. In addition, the operation of the kth stage STAk during the fourth and sixth periods st4 and st6 may be the same or substantially the same as the operation of the kth stage STAk during the second period st 2. Therefore, redundant description of the operation of the kth stage STAk during the third to sixth periods st3 to st6 will not be repeated.

Then, as shown in fig. 15 and 18, during the seventh period ST7, the start signal VST having the gate-off voltage VGH or the previous stage bit signal CR may be input to the start terminal ST of the k-th stage STAk, the first emission clock signal ECK1 having the gate-on voltage VGL may be input to the first clock terminal CT1 of the k-th stage STAk, the second emission clock signal ECK2 having the gate-off voltage VGH may be input to the second clock terminal CT2 of the k-th stage STAk, and the first scan clock signal SWPCK1 having the gate-off voltage VGH may be input to the third clock terminal CT3 of the k-th stage STAk.

The first switching transistor ST1 is turned on by the first transmission clock signal ECK1 having the gate-on voltage VGL to connect the first pull-up node Q1 to the start terminal ST. Accordingly, the gate off voltage VGH of the start signal VST or the previous stage bit signal CR may be supplied to the first pull-up node Q1.

The fifth switching transistor ST5 is turned on by the gate-on voltage VGL of the first control node CN1 to connect the gate-off voltage terminal VGHT to the second control node CN2. Accordingly, the gate-off voltage VGH of the gate-off voltage terminal VGHT may be supplied to the second control node CN2.

The tenth switching transistor ST10 is turned on by the gate-on voltage VGL of the gate-on voltage terminal VGLT to connect the second pull-up node Q2 to the first pull-up node Q1. Accordingly, the gate off voltage VGH of the first pull-up node Q1 may be supplied to the second pull-up node Q2.

The eleventh switching transistor ST11 is turned on by the gate-on voltage VGL of the gate-on voltage terminal VGLT to connect the first pull-up node Q1 to the third pull-up node Q3. Accordingly, the gate off voltage VGH of the first pull-up node Q1 may be supplied to the third pull-up node Q3.

During the seventh period ST7, the third, fourth, sixth, eighth, ninth, and ninth switching transistors ST3, ST4, ST6, ST8, ST9, the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, and the second pull-down transistor PD2 may be turned off.

Then, as shown in fig. 15 and 19, during the eighth period ST8, the start signal VST having the gate-off voltage VGH or the previous stage bit signal CR may be input to the start terminal ST of the kth stage STAk, the first emission clock signal ECK1 having the gate-off voltage VGH may be input to the first clock terminal CT1 of the kth stage STAk, the second emission clock signal ECK2 having the gate-on voltage VGL may be input to the second clock terminal CT2 of the kth stage STAk, and the first scan clock signal SWPCK1 having the gate-off voltage VGH may be input to the third clock terminal CT3 of the kth stage STAk.

The seventh switching transistor ST7 is turned on by the gate-on voltage VGL of the fourth control node CN4 to connect the third control node CN3 to the second clock terminal CT2. In addition, the eighth switching transistor ST8 is turned on by the gate-on voltage VGL of the second emission clock signal ECK2 of the second clock terminal CT2 to connect the third control node CN3 to the pull-down node QB. Accordingly, the third control node CN3 and the pull-down node QB may be connected to the second clock terminal CT2. Accordingly, the gate turn-on voltage VGL of the second emission clock signal ECK2 input to the second clock terminal CT2 may be supplied to the third control node CN3 and the pull-down node QB.

The first pull-down transistor PD1 is turned on by the gate-on voltage VGL of the pull-down node QB to connect the first output terminal OUT1 to the gate-off voltage terminal VGHT. Accordingly, the gate-off voltage VGH of the gate-off voltage terminal VGHT may be supplied to the first output terminal OUT1.

The second pull-down transistor PD2 is turned on by the gate-on voltage VGL of the pull-down node QB to connect the second output terminal OUT2 to the gate-off voltage terminal VGHT. Accordingly, the gate off voltage VGH of the gate off voltage terminal VGHT may be supplied to the second output terminal OUT2.

During the eighth period ST8, the first, second, third, fourth, sixth, ninth and first pull-up transistors ST1, ST2, ST3, ST4, ST6, ST9, PU1 and PU2 may be turned off.

As described above, the kth stage STAk may concurrently (e.g., may simultaneously) output the kth frequency sweep signal SWPk and the kth PWM emission signal PWEMk. Accordingly, the area of the scan driver 110 may be reduced by integrating and implementing a stage for outputting the kth frequency sweep signal SWPk and a stage for outputting the kth PWM emission signal PWEMk as one stage.

Fig. 20 is a perspective view illustrating a display device according to an embodiment.

Referring to fig. 20, the display device 10 is a device displaying moving images and/or still images, and may be used as a display screen of various suitable products, such as televisions, laptop computers, monitors, billboards, and internet of things (IOT) devices, for example, and various suitable portable electronic devices, such as mobile phones, smart phones, tablet Personal Computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable Multimedia Players (PMPs), navigation devices, and Ultra Mobile Personal Computers (UMPCs), for example.

The display device 10 includes a display panel 100, a scan driver 110, a source driving circuit 210, and a source circuit board 500.

The display panel 100 may be formed in a rectangular shape in a plan view, and may have a long side extending in a first direction DR1 (e.g., an X-axis direction) and a short side extending in a second direction DR2 (e.g., a Y-axis direction) crossing the first direction DR1 (e.g., the X-axis direction). Corners where the long sides extending in the first direction DR1 (e.g., the X-axis direction) intersect the short sides extending in the second direction DR2 (e.g., the Y-axis direction) may be rounded (e.g., curved) with a suitable curvature (e.g., a predetermined curvature), or may be right-angled. The shape of the display panel 100 in plan view is not limited to a rectangular shape, and may have any suitable shape (e.g., such as a polygonal shape other than a rectangular shape, a circular shape, or an elliptical shape). The display panel 100 may be formed to be flat or substantially flat, but the present disclosure is not limited thereto. For example, the display panel 100 may include curved portions formed at left and right ends of the display panel 100 and having a constant curvature or a variable curvature. In addition, the display panel 100 may be formed to be flexible such that the display panel 100 may be bent, folded, and/or rolled.

The display panel 100 may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may occupy most of the area of the display panel 100. The display area DA may be disposed at the center of the display panel 100. The subpixels RP, GP, and BP may be disposed at (e.g., in or on) the display area DA to display an image in a third direction DR3 perpendicular to the first and second directions DR1 and DR 2. Each of the sub-pixels RP, GP, and BP may include an inorganic light emitting element having an inorganic semiconductor as a light emitting element for emitting light.

The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. For example, the non-display area NDA may be disposed to surround the display area DA (e.g., around the periphery of the display area DA). The non-display area NDA may be an edge area of the display panel 100.

The scan driver 110 may be disposed at (e.g., in or on) the non-display area NDA. Although fig. 20 shows that the scan driver 110 is disposed at opposite sides of the display area DA (e.g., left and right sides of the display area DA), the present disclosure is not limited thereto. For example, in some embodiments, the scan driver 110 may be disposed at one side of the display area DA.

In addition, the display pad may be disposed at (e.g., in or on) the non-display area NDA so as to be connected to the source circuit board 500. The display pad may be disposed on an edge of one side of the display panel 100. For example, the display pad may be disposed on an edge of the lower side of the display panel 100.

The source circuit board 500 may be disposed on a display pad disposed on an edge of one side of the display panel 100. The source circuit board 500 may be attached to the display pad using a conductive adhesive member (e.g., such as an anisotropic conductive film). Accordingly, the source circuit board 500 may be electrically connected to the signal lines of the display panel 100. Each of the source circuit boards 500 may be a flexible printed circuit board, a printed circuit board, or a flexible film (e.g., such as a chip on film).

The source driver 200 may include a source driving circuit 210. The source driving circuit 210 may generate a data voltage, and may supply the data voltage to the display panel 100 through the source circuit board 500.

Each of the source driving circuits 210 may be formed as an Integrated Circuit (IC), and may be attached to the source circuit board 500. The source driving circuit 210 may be attached to the display panel 100 in a Chip On Glass (COG) manner, a Chip On Plastic (COP) manner, or an ultrasonic bonding manner.

The control circuit board 600 may be attached to the source circuit board 500 by a conductive adhesive member (e.g., such as an anisotropic conductive film). The control circuit board 600 may be electrically connected to the source circuit board 500. The control circuit board 600 may be a flexible printed circuit board or a printed circuit board.

Each of the timing controller 300 and the power supply unit 400 may be formed as an Integrated Circuit (IC), and may be attached to the control circuit board 600. The timing controller 300 may supply the digital video DATA and the timing signal TS to the source driving circuit 210. The power supply unit 400 may generate and output voltages for driving the subpixels RP, GP, and BP of the display panel 100 and the source driving circuit 210.

Fig. 21 is a plan view illustrating a display device according to another embodiment.

The display device according to another embodiment shown in fig. 21 is different from the display device 10 according to the embodiment shown in fig. 20 in that: in fig. 21, the display panel 100 does not include the non-display area NDA so that the scan driver 110 may be disposed at (e.g., in or on) the display area DA and the source circuit board 500 on which the active driving circuit 210 is mounted may be disposed on the rear surface of the display panel 100. Accordingly, hereinafter, the difference between the embodiment of fig. 20 and the embodiment of fig. 21 may be mainly described in more detail, and redundant description thereof may not be repeated.

Referring to fig. 21, the scan driver 110 may be disposed at (e.g., in or on) the display area DA. The scan driver 110 may not overlap the subpixels RP, GP, and BP, and may be disposed between the subpixels RP, GP, and BP.

The source circuit board 500 may be disposed on the rear surface of the display panel 100. In this case, the display pad connected to the source circuit board 500 may be disposed on the rear surface of the display panel 100. In addition, pad connection electrodes passing through the display panel 100 and respectively connected to the display pads may be disposed at (e.g., in or on) the display area DA of the display panel 100.

Referring to fig. 22, the tiled display device TD may include a plurality of

display devices

11, 12, 13, and 14. For example, the tiled display device TD may include a first display device 11, a second display device 12, a third display device 13 and a fourth display device 14.

The plurality of

display devices

11, 12, 13, and 14 may be arranged in a lattice shape. For example, the first and

second display devices

11 and 12 may be disposed along the first direction DR 1. The first display device 11 and the third display device 13 may be disposed along the second direction DR 2. The third display device 13 and the fourth display device 14 may be disposed along the first direction DR 1. The second display device 12 and the fourth display device 14 may be disposed along the second direction DR 2.

The number and arrangement of the plurality of display devices in the tiled display device TD are not limited to those shown in fig. 22. The number and arrangement of the display devices in the tiled display device TD may be determined according to the size of each of the display devices and the size and shape of the tiled display device TD.

The plurality of

display devices

11, 12, 13, and 14 may have the same or substantially the same size as each other, but the present disclosure is not limited thereto. For example, the plurality of

display devices

11, 12, 13, and 14 may have different sizes from each other.

Each of the plurality of

display devices

11, 12, 13, and 14 (e.g., in a plan view) may have a rectangular shape having long sides and short sides. The plurality of

display devices

11, 12, 13, and 14 may be disposed such that long sides or short sides are connected to each other. Some or all of the plurality of

display devices

11, 12, 13, and 14 may be disposed at an edge of the tiled display device TD, and may form one side of the tiled display device TD. At least one of the plurality of

display devices

11, 12, 13, and 14 may be disposed at least one corner of the tiled display device TD, and may form two adjacent sides of the tiled display device TD. At least one of the plurality of

display devices

11, 12, 13, and 14 may be surrounded by (e.g., around the periphery of) the other display devices.

The tiled display device TD may include a seam portion SM disposed between the plurality of

display devices

11, 12, 13 and 14. For example, the seam portions SM may be disposed between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, between the second display device 12 and the fourth display device 14, and between the third display device 13 and the fourth display device 14.

The seam part SM may include a coupling member or an adhesive member. In this case, the plurality of

display devices

11, 12, 13, and 14 may be connected to each other by a coupling member or an adhesive member of the seam part SM.

When the scan driver 110 is disposed at (e.g., in or on) the display area DA and the source circuit board 500 is disposed on the rear surface of the display panel 100 as shown in fig. 21, the non-display area NDA where the sub-pixels RP, GP, and BP are not disposed (e.g., in or on) may be removed or reduced in each of the plurality of

display devices

11, 12, 13, and 14, and thus, the visual recognition of the seam portion SM in the tiled display device TD may be reduced (e.g., minimized) or prevented. Accordingly, it is possible to prevent or substantially prevent the images of the plurality of

display devices

11, 12, 13, and 14 from being viewed discontinuously regardless of the seam portion SM, and therefore, it is possible to improve the immersive sensation of the images of the tiled display device TD.

Although a few embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made to the embodiments without departing from the spirit and scope of the disclosure. It will be understood that the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments, unless described otherwise. Thus, it will be apparent to one of ordinary skill in the art that features, characteristics, and/or elements described in connection with the specific embodiments may be used alone or in combination with features, characteristics, and/or elements described in connection with other embodiments unless specifically stated otherwise. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific embodiments disclosed herein and that various modifications to the disclosed embodiments, as well as other example embodiments, are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A swept frequency signal driver, comprising:

a plurality of stages configured to sequentially output a plurality of transmission signals to a plurality of transmission lines and a plurality of sweep signals to a plurality of sweep signal lines,

wherein the plurality of stages includes a kth stage configured to output a kth transmit signal of the plurality of transmit signals to a kth transmit line of the plurality of transmit lines and a kth sweep signal of the plurality of sweep signals to a kth sweep signal line of the plurality of sweep signal lines, where k is a natural number greater than zero, the kth stage including:

a first pull-up node;

a second pull-up node;

a third pull-up node;

a node connection circuit between the first pull-up node and the second pull-up node and between the first pull-up node and the third pull-up node;

a first output circuit configured to output a swept clock signal of a swept clock terminal to a first output terminal connected to the kth swept signal line when the third pull-up node has a gate-on voltage; and

a second output circuit configured to output a gate-on voltage to a second output terminal connected to the kth emission line when the second pull-up node has the gate-on voltage, and

wherein the pulse of the k-th swept frequency signal is linearly changed from a gate-off voltage to a gate-on voltage.

2. The swept frequency signal driver of claim 1, wherein a pulse width of the kth transmit signal is greater than a pulse width of the kth swept frequency signal.

3. The swept frequency signal driver of claim 1, wherein the kth stage further comprises:

a pull-down node electrically disconnected from the first, second, and third pull-up nodes, and

wherein each of the first output circuit and the second output circuit is configured to output a gate-off voltage when the pull-down node has a gate-on voltage.

4. The swept frequency signal driver of claim 3, wherein the first output circuit comprises:

a first pull-up transistor comprising a gate electrode connected to the third pull-up node, a first electrode connected to the first output terminal, and a second electrode connected to the swept clock terminal;

a first pull-down transistor including a gate electrode connected to the pull-down node, a first electrode connected to a gate-off voltage terminal configured to receive the gate-off voltage, and a second electrode connected to the first output terminal; and

a first capacitor between the third pull-up node and the first output terminal.

5. A swept frequency signal driver as claimed in claim 3, wherein the second output circuit comprises:

a second pull-up transistor including a gate electrode connected to the second pull-up node, a first electrode connected to the second output terminal, and a second electrode connected to a gate-on voltage terminal configured to receive the gate-on voltage; and

a second pull-down transistor including a gate electrode connected to the pull-down node, a first electrode connected to a gate-off voltage terminal configured to receive the gate-off voltage, and a second electrode connected to the second output terminal.

6. The swept frequency signal driver of claim 3, wherein the kth stage further comprises:

a pull-up node control circuit configured to supply a start signal or a carry signal of a start terminal to the first pull-up node according to a first transmit clock signal input to a first transmit clock terminal.

7. The swept frequency signal driver of claim 6, wherein the pull-up node control circuit comprises:

a first transistor including a gate electrode connected to the first transmit clock terminal, a first electrode connected to the first pull-up node, and a second electrode connected to the start terminal.

8. The swept frequency signal driver of claim 6, wherein the k-th stage further comprises:

a first control node control circuit configured to supply the gate-on voltage to a first control node according to the first transmit clock signal and supply the first transmit clock signal to the first control node according to a voltage of the first pull-up node.

9. The swept frequency signal driver of claim 8, wherein the first control node control circuit comprises:

a second transistor including a gate electrode connected to the first transmit clock terminal, a first electrode connected to the first control node, and a second electrode connected to a gate-on voltage terminal configured to receive the gate-on voltage;

a third transistor including a second electrode, a gate electrode connected to the first pull-up node, and a first electrode connected to the first transmission clock terminal; and

a fourth transistor including a gate electrode connected to the first pull-up node, a first electrode connected to the second electrode of the third transistor, and a second electrode connected to the first control node.

10. The swept frequency signal driver of claim 8, wherein the k-th stage further comprises:

a second control node control circuit configured to supply a gate-off voltage to a second control node when the first control node has the gate-on voltage, and to supply a second transmit clock signal of a second transmit clock terminal to the second control node when the second pull-up node has the gate-on voltage.

11. The swept frequency signal driver of claim 10, wherein the second control node control circuit comprises:

a fifth transistor including a gate electrode connected to the first control node, a first electrode connected to a gate-off voltage terminal configured to receive the gate-off voltage, and a second electrode connected to the second control node;

a sixth transistor including a gate electrode connected to the second pull-up node, a first electrode connected to the second control node, and a second electrode connected to the second transmit clock terminal; and

a second capacitor between the second pull-up node and the second control node.

12. The swept frequency signal driver of claim 10, wherein the node connection circuit is further located between the first control node and a third control node, and

wherein the k-th stage further comprises:

a pull-down node control circuit configured to supply the gate-on voltage of the second transmit clock signal to the pull-down node when the third control node has a gate-on voltage and the second transmit clock signal of the second transmit clock terminal has a gate-on voltage.

13. The swept frequency signal driver of claim 12, wherein the pull-down node control circuit is further configured to supply a gate-off voltage to the pull-down node when the first pull-up node has a gate-on voltage.

14. The swept frequency signal driver of claim 13, wherein the pull-down node control circuit comprises:

a seventh transistor including a gate electrode connected to the third control node, a first electrode connected to the second transmission clock terminal, and a second electrode connected to a fourth control node;

an eighth transistor including a gate electrode connected to the second emission clock terminal, a first electrode connected to the fourth control node, and a second electrode connected to the pull-down node;

a ninth transistor including a gate electrode connected to the first pull-up node, a first electrode connected to a gate-off voltage terminal configured to receive the gate-off voltage, and a second electrode connected to the pull-down node;

a third capacitor between the third control node and the fourth control node; and

a fourth capacitor between the pull-down node and the gate off voltage terminal.

15. The swept frequency signal driver of claim 12, wherein the node connection circuitry comprises:

a tenth transistor including a gate electrode connected to a gate-on voltage terminal configured to receive the gate-on voltage, a first electrode connected to the first pull-up node, and a second electrode connected to the second pull-up node;

an eleventh transistor including a gate electrode connected to the gate-on voltage terminal, a first electrode connected to the first pull-up node, and a second electrode connected to the third pull-up node; and

a twelfth transistor including a gate electrode connected to the gate-on voltage terminal, a first electrode connected to the third control node, and a second electrode connected to the first control node.

16. A display device, comprising:

a display panel including a plurality of data lines, a plurality of sweep signal lines and a plurality of pulse width modulation emission lines crossing the plurality of data lines, and a plurality of subpixels connected to the plurality of data lines, the plurality of sweep signal lines, and the plurality of pulse width modulation emission lines;

a source driver configured to apply a plurality of data voltages to the plurality of data lines; and

a swept frequency signal driver comprising a plurality of stages configured to sequentially output a plurality of pulse width modulated transmit signals to the plurality of pulse width modulated transmit lines and a plurality of swept frequency signals to the plurality of swept frequency signal lines,

wherein:

the plurality of stages including a kth stage configured to output a kth pulse width modulated transmit signal of the plurality of pulse width modulated transmit signals to a kth pulse width modulated transmit line of the plurality of pulse width modulated transmit lines and a kth sweep signal of the plurality of sweep signals to a kth sweep signal line of the plurality of sweep signal lines, where k is a natural number greater than zero,

the pulse of the kth pulse width modulated transmission signal comprises a gate-on voltage,

the pulse of the k-th frequency sweep signal is linearly changed from a gate-off voltage to a gate-on voltage, and

the pulse width of the k pulse width modulation transmitting signal is larger than that of the k sweep frequency signal.

17. The display device according to claim 16, further comprising:

a transmission signal driver configured to sequentially output a plurality of pulse amplitude modulation transmission signals to a plurality of pulse amplitude modulation transmission lines crossing the plurality of data lines,

wherein a pulse of a k-th pulse amplitude modulation transmission signal of the plurality of pulse amplitude modulation transmission signals, which is output to a k-th pulse amplitude modulation transmission line of the plurality of pulse amplitude modulation transmission lines, includes a gate-on voltage, and

the pulse width of the kth pulse amplitude modulation transmission signal is the same as the pulse width of the kth frequency sweep signal.

18. The display device of claim 17, wherein the pulse of the kth pulse width modulated transmit signal overlaps the pulse of the kth swept frequency signal and the pulse of the kth pulse amplitude modulated transmit signal.

19. The display device according to claim 17, wherein the kth stage comprises:

a first pull-up node, a second pull-up node and a third pull-up node;

a first output circuit configured to output a swept frequency clock signal of a swept frequency clock terminal to a first output terminal when the third pull-up node has a gate-on voltage, the first output terminal being connected to the kth swept frequency signal line; and

a second output circuit configured to output a gate-on voltage to a second output terminal connected to the kth pulse width modulation transmission line when the second pull-up node has the gate-on voltage.

20. The display device of claim 19, wherein the kth stage further comprises: