CN115861512A - Method and device for determining output point sequence for tessellation and storage medium - Google Patents
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Abstract
The application provides a method and a device for determining an output point sequence for tessellation and a storage medium, wherein the method for determining the output point sequence for tessellation comprises the following steps: determining a graph to be displayed; dividing each patch into N stitched portions; for each inner ring, obtaining a first sequence of output points of the inner ring at a first stitched portion, the first sequence of output points being stitched for an inner edge subdivision point of the inner ring on an inner edge of the first stitched portion and an outer edge subdivision point on an outer edge of the inner ring; for each inner ring, a second output point sequence of the inner ring at the second stitching portion is determined according to the arrangement order of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and the position mapping relationship between the subdivision point of the inner ring at the first stitching portion and the subdivision point of the inner ring at the second stitching portion. According to the technical scheme, the sewing operation in the surface subdivision process can be reduced, and the requirement on hardware resources is further reduced.
Description
Technical Field
The present application relates to the field of graphics processing, and in particular, to a method and an apparatus for determining an output point sequence for tessellation, and a storage medium.
Background
The Tessellation (tesselation) uses a Graphics Processing Unit (GPU) to accelerate hardware, so as to split the triangles of the existing graph into smaller and finer triangles, thereby greatly increasing the number of the triangles.
In the prior art, the tessellation technique would adapt to the appropriate tessellation Factor (Tess Factor) for a given patch. Based on the subdivision factor, the slice may be divided into a suitable number of rings and subdivision points on each ring. Wherein the subdivision factors include an Outer ring subdivision Factor (Outer Tess Factor, outer tf) and an Inner ring subdivision Factor (Inner Tess Factor, inner tf). The outer-loop subdivision factor is used to determine the degree of subdivision of the outermost loop of the patch, and the inner-loop subdivision factor is used to determine the degree of subdivision of all inner loops except the outermost loop of the patch. And performing a circle of sewing operation on all the subdivided points on each ring, namely connecting the subdivided points on the two edges of each ring in a triangular shape until the ring is sewn to the end and completing one round of iteration. And stopping all iterations after all the rings are sutured. After the patch stitching is finished, a whole output point sequence, also called triangle strip, can be obtained. Adjacent three points in the triangle strip represent the three vertices of the triangle.
In the prior art, the output point sequence is output after all the subdivision points are stitched, and the stitching operation has higher computational complexity and higher requirement on hardware resources. In addition, the number of triangles generated by the tessellation method may be large, and the number of vertices included in the output point sequence may be large, which may place a great strain on subsequent computations and storage.
Disclosure of Invention
The application provides a method and a device for determining an output point sequence for tessellation and a storage medium, which can reduce stitching operation in the tessellation process and further reduce the requirement on hardware resources.
In order to achieve the above object, the present application provides the following technical solutions:
in a first aspect, there is provided a method for determining a sequence of output points for a tessellation comprising: determining a graph to be displayed, wherein the outline of the graph is divided into a plurality of patches, each patch is provided with N edges, each patch is divided into a plurality of rings from inside to outside, and N is a positive integer greater than or equal to 3; dividing each panel into N stitching portions, each stitching portion being a triangle defined by a center point and an edge of the panel; obtaining, for each inner ring, a first sequence of output points of the inner ring at a first stitched portion, the first sequence of output points being stitched for an inner edge subdivision point of the inner ring on an inner edge and an outer edge subdivision point on an outer edge of the first stitched portion, the inner ring being a ring of the plurality of rings other than an outermost ring, the first stitched portion being selected from the N stitched portions; and for each internal ring, determining a second output point sequence of the internal ring at a second sewing part according to the arrangement sequence of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and the position mapping relation of the subdivision point of the internal ring at the first sewing part and the subdivision point at the second sewing part, wherein the second sewing part is other sewing parts except the first sewing part or the sewing part opposite to the first sewing part in position in the N sewing parts.
Optionally, an arrangement order of each second inner edge subdivision point and second outer edge subdivision point in the second output point sequence is consistent with an arrangement order of the corresponding first inner edge subdivision point and first outer edge subdivision point in the first output point sequence.
Optionally, the determining the second output point sequence of the inner ring at the second stitching portion includes: for a first inner edge subdivision point in the first output point sequence, determining an index of a corresponding second inner edge subdivision point in the second output point sequence according to the index of the first inner edge subdivision point and the first mapping relation; and for a first outer edge subdivision point in the first output point sequence, determining an index of a corresponding second outer edge subdivision point in the second output point sequence according to the index of the first outer edge subdivision point and the second mapping relation.
Optionally, the determining the second output point sequence of the inner ring at the second stitching portion includes: for a first inner edge refinement point in the first output point sequence, determining an index of a corresponding second inner edge refinement point in the second output point sequence according to the index of the first inner edge refinement point and the internal position offset; and for a first outer edge subdivision point in the first output point sequence, determining the index of a corresponding second outer edge subdivision point in the second output point sequence according to the index of the first outer edge subdivision point and the external position offset.
Optionally, the obtaining the first sequence of output points of the inner loop at the first stitched portion comprises: stitching the inner edge subdivision point on the inner edge of the first stitched portion and the outer edge subdivision point on the outer edge of the inner ring to obtain the first output point sequence.
Optionally, the stitching of the inner ring at the inner edge subdivision point on the inner edge and the outer edge subdivision point on the outer edge of the first stitched portion comprises: determining a sequence of outer edge subdivision points on the outer edge, a sequence of inner edge subdivision points on the inner edge, and a stitching order of the inner ring within the first stitched portion, and stitching the outer edge subdivision points and the inner edge subdivision points according to the stitching order, the stitching order representing an order of movement within the sequence of outer edge subdivision points and the sequence of inner edge subdivision points when stitched.
Optionally, the obtaining the first sequence of output points of the inner loop at the first stitched portion comprises: receiving a first sequence of output points from a tessellator stitched for the inner ring at an inner edge subdivision point on an inner edge and an outer edge subdivision point on an outer edge of a first stitched portion.
Optionally, when N is 3, the second sewn portion is another sewn portion except for the first sewn portion among the 3 sewn portions; and when N is 4, the second sewed portion is a sewed portion opposite to the first sewed portion in position among the 4 sewed portions.
Optionally, the number of subdivision points on each edge in each patch is the same.
Optionally, the determining the inner ring before the second output point sequence of the second stitching portion further comprises: and acquiring a first output point sequence from the cache.
Optionally, the method for determining the sequence of output points for tessellation further includes: for each inner loop, combining the first sequence of output points for that inner loop at the first stitching portion and the second sequence of output points for that inner loop at the second stitching portion to obtain a sequence of output points for that inner loop.
In a second aspect, the present application further discloses an output point sequence determination apparatus for tessellation, the output point sequence determination apparatus comprising: the image determining module is used for determining an image to be displayed, the outline of the image is divided into a plurality of patches, each patch is provided with N edges, each patch is divided into a plurality of rings from inside to outside, and N is a positive integer greater than or equal to 3; a dividing module for dividing each panel into N stitching portions, each stitching portion being a triangle defined by a center point and an edge of the panel; an obtaining module for obtaining, for each inner ring, a first sequence of output points of the inner ring at a first stitched portion, the first sequence of output points being stitched for an inner edge subdivision point on an inner edge of the first stitched portion and an outer edge subdivision point on an outer edge of the inner ring, an inner ring being a ring of the plurality of rings other than an outermost ring, the first stitched portion being selected from the N stitched portions; and the output point sequence determining module is used for determining a second output point sequence of the inner ring in a second sewing part according to the arrangement sequence of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and the position mapping relation of the subdivision point of the inner ring in the first sewing part and the subdivision point in the second sewing part, wherein the second sewing part is other sewing parts except the first sewing part or the sewing part opposite to the first sewing part in position in the N sewing parts.
In a third aspect, a computer-readable storage medium is provided, on which a computer program is stored, the computer program being executable by a processor to perform the method provided in the first aspect.
In a fourth aspect, a communication device is provided, comprising a memory and a processor, the memory having stored thereon a computer program executable on the processor, the processor executing the computer program to perform a method as provided by the first aspect.
In a fifth aspect, a computer program product is provided, on which a computer program is stored, the computer program being executable by a processor to perform any of the methods provided in the first or second aspect.
In a sixth aspect, an embodiment of the present application further provides a chip, where a computer program is stored on the chip, and when the computer program is executed by the chip, the steps of the method are implemented.
Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:
in the technical scheme of the application, for N sewing parts in each panel, only the part of the inner ring in the first sewing part can be subjected to sewing operation, and a first output point sequence of the inner ring in the first sewing part is obtained; for the portion of the inner ring at the second stitched portion, a second output point sequence may be obtained according to a position mapping relationship of the subdivision point of the inner ring at the first stitched portion and the subdivision point at the second stitched portion. According to the technical scheme, the method and the device for tessellation can reduce stitching operation, namely reduce the number of subdivision points needing stitching, and accordingly reduce the requirements of the tessellation process on hardware resources. In addition, after the number of the subdivided points required to be stitched is reduced, the number of the subdivided points in the output point sequence required to be transmitted by the tessellator performing the stitching operation is also reduced, thereby reducing the data transmission bandwidth.
Furthermore, the technical scheme of the application realizes the mapping from the first output point sequence to the second output point sequence by utilizing the regularity of the distribution of each internal ring at the subdivided positions of the stitching parts and the consistency of the stitching sequence, thereby reducing the stitching operation and the data transmission bandwidth.
Drawings
FIG. 1 is a flow chart of a method for determining a sequence of output points for a tessellation according to an embodiment of the present application;
fig. 2 is a schematic view of a portion of a seam in a panel according to an embodiment of the present disclosure;
FIG. 3 is a schematic view of another panel inner seam portion provided by an embodiment of the present application;
fig. 4 is a schematic diagram of a specific application scenario provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of another specific application scenario provided in an embodiment of the present application;
FIG. 6 is a diagram illustrating another specific application scenario provided by an embodiment of the present application;
FIG. 7 is a block diagram of an apparatus for tessellation according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an output point sequence determination apparatus for tessellation according to an embodiment of the present application.
Detailed Description
As described in the background art, in the prior art, the output point sequence is output after all the minutiae stitching is completed, and the stitching operation has high computational complexity and high requirements on hardware resources. In addition, the number of triangles generated by the tessellation method may be large, and the number of vertices included in the output point sequence may be large, which may place a great deal of stress on subsequent calculations and storage.
In the technical scheme of the application, for N sewing parts in each panel, only the part of the inner ring in the first sewing part can be subjected to sewing operation, and a first output point sequence of the inner ring in the first sewing part is obtained; for the portion of the inner ring at the second stitched portion, a second output point sequence may be obtained according to a position mapping relationship of the subdivision point of the inner ring at the first stitched portion and the subdivision point at the second stitched portion. According to the technical scheme, the method and the device for tessellation can reduce stitching operation, namely reduce the number of subdivision points needing stitching, and accordingly reduce the requirements of the tessellation process on hardware resources. In addition, after the number of the subdivided points required to be stitched is reduced, the number of the subdivided points in the output point sequence required to be transmitted by the tessellator performing the stitching operation is also reduced, thereby reducing the data transmission bandwidth.
Further, for a first inner edge refinement point in the first output point sequence, determining an index of a corresponding second inner edge refinement point according to the index of the first inner edge refinement point and the internal position offset; and for a first outer edge subdivision point in the first output point sequence, determining the index of a corresponding second outer edge subdivision point according to the index of the first outer edge subdivision point and the external position offset. According to the technical scheme, the mapping from the first output point sequence to the second output point sequence is realized by utilizing the regularity of distribution of each internal ring at the subdivided point position of each stitching part and the consistency of the stitching sequence, so that the stitching operation is reduced, and the data transmission bandwidth is reduced.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below.
Referring to fig. 1, the method provided by the present application includes:
step 101: determining a graph to be displayed, wherein the outline of the graph is divided into a plurality of patches, each patch is provided with N edges, each patch is divided into a plurality of rings from inside to outside, and N is a positive integer greater than or equal to 3;
step 102: dividing each panel into N stitched portions, each stitched portion being a triangle defined by a center point and an edge of the panel;
step 103: obtaining, for each inner ring, a first sequence of output points of the inner ring at a first stitched portion, the first sequence of output points being stitched for an inner edge subdivision point of the inner ring on an inner edge and an outer edge subdivision point on an outer edge of the first stitched portion, the inner ring being a ring of the plurality of rings other than an outermost ring, the first stitched portion being selected from the N stitched portions;
step 104: and for each internal ring, determining a second output point sequence of the internal ring at a second sewing part according to the arrangement sequence of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and the position mapping relation of the subdivision point of the internal ring at the first sewing part and the subdivision point at the second sewing part, wherein the second sewing part is other sewing parts except the first sewing part or the sewing part opposite to the first sewing part in position in the N sewing parts.
It should be noted that the sequence numbers of the steps in this embodiment do not represent a limitation on the execution sequence of the steps.
It will be appreciated that in a specific implementation, the output point sequence determination method for tessellation may be implemented in the form of a software program running on a processor integrated within a chip or chip module. The method may also be implemented by combining software and hardware, and the present application is not limited thereto.
In a specific implementation of step 101, a graphic to be displayed is determined, for example, the graphic is a graphic representing a three-dimensional object, and the graphic has an outline. Specifically, the graphic may be a previously generated graphic to be displayed. The graphics are processed by a tessellation technique, and each patch of the graphics outline can be further subdivided into smaller primitives. The output point sequences of all patches in the graph can be further processed and then displayed on a display interface, so that the graph has a display effect closer to the real world. In this embodiment, the patch is a closed N-polygon having N edges. For example, a patch may be a triangle, a quadrilateral, or any other type of polygon.
In particular, a patch may be a two-dimensional (2D) shape. In particular, a patch is a portion of the surface of the object to be rendered.
Further, each patch may be divided into a plurality of rings from inside to outside, with one or more subdivision points on the inner and outer edges of each ring. The plurality of rings may be concentrically shaped within the patch, the plurality of rings being shaped the same as the patch. For example, if the shape of the patch is a quadrilateral, the rings furthest from the center of the quadrilateral are the outermost rings, the other rings are the inner rings, and the inner rings are a series of rings with smaller dimensions. Similarly, if the shape of the patch is triangular, the ring furthest from the center of the triangle is the outermost ring, the other rings are the inner rings, and the inner rings are a series of rings having a smaller size. In a specific implementation, a patch can be divided into an appropriate number of rings and an appropriate number of subdivision points by configuring a subdivision factor (Tessfactor) for the patch.
In a specific implementation of step 102, a patch is divided into N stitched portions. For example, when a patch is quadrilateral, the patch is divided into four stitched portions; when a patch is triangular, the patch is divided into three stitched portions. Each of the stitching portions is a triangle defined by a center point and an edge of the panel.
Referring to fig. 2, the patch has a quadrilateral shape, and the quadrilateral shape is divided into four stitching portions P1, P2, P3, and P4. The stitch portion P1 is a triangle defined by the side L1 of the quadrangle and the center point O, the stitch portion P2 is a triangle defined by the side L2 of the quadrangle and the center point O, the stitch portion P3 is a triangle defined by the side L3 of the quadrangle and the center point O, and the stitch portion P4 is a triangle defined by the side L4 of the quadrangle and the center point O.
Accordingly, referring to fig. 3, the patch is a triangle, and the triangle is divided into three stitching portions P1, P2, and P3. The stitching portion P1 is a triangle defined by the side L1 and the center point O, the stitching portion P2 is a triangle defined by the side L2 and the center point O, and the stitching portion P3 is a triangle defined by the side L3 and the center point O.
The position distribution of the subdivision points of the same inner ring in different sewing parts has regularity, in other words, the position distribution of the subdivision points of the same inner ring in different sewing parts has mapping relation. Then, knowing the stitching result (i.e., the output point sequence) of the inner loop in one or two adjacent stitching portions, the output point sequence of the inner loop in the other stitching portion can be obtained by calculation.
Therefore, in the specific implementation of step 103 and step 104, a first output point sequence of the inner ring at the first seam portion is obtained first, and a second output point sequence of the inner ring at the second seam portion is determined according to the arrangement order of the inner edge subdivision point and the outer edge subdivision point in the first output point sequence and the position mapping relationship between the subdivision point of the inner ring at the first seam portion and the subdivision point of the inner ring at the second seam portion.
When the shape of the surface sheet is triangular, the second sewing part is the other sewing parts except the first sewing part in the three sewing parts; when the shape of the face sheet is a quadrangle, the second sewn portion is a sewn portion that is positionally opposite to the first sewn portion among the four sewn portions.
Further, the first output point sequence includes a first inner edge subdivision point and a first outer edge subdivision point which are sequentially arranged, and the second output point sequence includes a second inner edge subdivision point and a second outer edge subdivision point which are sequentially arranged. The second inner edge subdivision point corresponds to the first inner edge subdivision point and the second outer edge subdivision point corresponds to the first outer edge subdivision point. The arrangement order of each second inner edge subdivision point and second outer edge subdivision point in the second output point sequence is consistent with the arrangement order of the corresponding first inner edge subdivision point and first outer edge subdivision point in the first output point sequence. In other words, the stitching sequence of the inner loops at the first stitched portion is the same as the stitching sequence of the inner loops at the second stitched portion.
In this embodiment, the second output point sequence is obtained by the above calculation instead of the stitching operation, so that the number of the subdivision points that need to perform the stitching operation can be reduced, thereby reducing the complexity and the calculation amount of the stitching as a whole, and reducing the requirement of the tessellation process on hardware resources.
In one embodiment of steps 103 and 104, the first sequence of output points and the second sequence of output points may be obtained for the inner rings one by one and calculated. For example, for the inner loop 301, the inner loop 302, and the inner loop 303 in fig. 4, the calculation of the second sequence of output points for the inner loop 301 may begin after the first sequence of output points for the inner loop 301 is obtained; starting to calculate a second sequence of output points for the inner loop 302 after obtaining the first sequence of output points for the inner loop 302; the calculation of the second sequence of output points of the inner loop 303 is started after the first sequence of output points of the inner loop 303 is obtained.
In another embodiment of step 103 and step 104, after the first output point sequences of all the inner loops are obtained, the second output point sequences of the inner loops may be calculated together. For example, for the inner rings 301, 302, and 303 in fig. 4, the calculation of the second output point sequence of the inner ring 301, the second output point sequence of the inner ring 302, and the second output point sequence of the inner ring 303 may be started after all the first output point sequences of the inner rings 301, 302, and 303 are obtained.
In one non-limiting embodiment of the present application, the positional mapping includes a first mapping of the inner ring at a first inner edge subdivision point of the first stitched portion and the inner ring at a second inner edge subdivision point of the second stitched portion, and a second mapping of the inner ring at a first outer edge subdivision point of the first stitched portion and the inner ring at a second outer edge subdivision point of the second stitched portion. Then, for a first inner edge refinement point in the first output point sequence, determining an index of a corresponding second inner edge refinement point in the second output point sequence according to the index of the first inner edge refinement point and the first mapping relation; and for the first outer edge subdivision point in the first output point sequence, determining the index of the corresponding second outer edge subdivision point in the second output point sequence according to the index of the first outer edge subdivision point and the second mapping relation.
In a specific implementation, the first mapping relationship and the second mapping relationship may refer to mapping relationships between positions of the subdivision points. The position of the subdivision point may be expressed in coordinates or in a position index. The first mapping and the second mapping may be a mapping between the coordinates of the subdivision points or a mapping between the indices of the subdivision points.
Specifically, referring to fig. 3 and 4, taking the inner ring 301 as an example, the first inner edge subdivision point of the inner ring 301 in the first stitched portion P1 is {18, 19, 20, 21, 22}, and the second inner edge subdivision point of the inner ring 301 in the second stitched portion P3 is {26, 27, 28, 29, 18}, and the first mapping relationship between the first inner edge subdivision point and the second inner edge subdivision point means that the subdivision point 18 corresponds to the subdivision point 26, the subdivision point 19 corresponds to the subdivision point 27, and so on, the subdivision point 22 corresponds to the subdivision point 18.
Accordingly, the index of the inner ring 301 at the first outer edge subdivision point of the first stitching portion P1 is {0,1,2,3,4,5,6}, the index of the inner ring 301 at the second outer edge subdivision point of the second stitching portion P3 is {12, 13, 14, 15, 16, 17,0}, and the second mapping relationship between the first outer edge subdivision point and the second outer edge subdivision point means that subdivision point 0 corresponds to subdivision point 12, subdivision point 1 corresponds to subdivision point 13, and so on, subdivision point 6 corresponds to subdivision point 0.
In another non-limiting embodiment of the present application, the position mapping relationship includes an inner position offset of the inner ring at the first inner edge subdivision point of the first stitch portion and the second inner edge subdivision point of the second stitch portion, where indices of the subdivision points are consecutive. Then, for a first inner edge refinement point in the first sequence of output points, the index of the corresponding second inner edge refinement point may be determined in accordance with the index of the first inner edge refinement point and the internal position offset.
Accordingly, where the indices of the subdivision points in the first and second outer edge subdivision points are consecutive, the positional mapping includes an outer positional offset of the inner ring at the first outer edge subdivision point of the first stitch portion from the second outer edge subdivision point of the second stitch portion. Specifically, for a first outer edge subdivision point in the first output point sequence, the index of a corresponding second outer edge subdivision point is determined according to the index of the first outer edge subdivision point and the external position offset.
A detailed description of the implementation of step 104 is provided below in conjunction with fig. 4.
Taking the inner ring 301 as an example, the index of the first outer edge subdivision point of the inner ring 301 at the first stitched portion P1 is {0,1,2,3,4,5,6}, the index of the first inner edge subdivision point is {18, 19, 20, 21, 22}, and the first output point sequence is {0,1, 18, 19,1,2, 19, 20,2,3, 20,4, 21,5, 22,6}. The stitching effect is shown in figure 4.
The inner ring 301 has an index of {6,7,8,9, 10, 11, 12} at the second outer edge subdivision point of the second suture part P2, and an index of {22, 23, 24, 25, 26} at the second inner edge subdivision point. The amount of internal positional offset of the first inner edge subdivision point from the second inner edge subdivision point is 4, and the amount of external positional offset of the first outer edge subdivision point from the second outer edge subdivision point is 6. Then for the first sequence of output points {0,1, 18, 19,1,2, 19, 20,2,3, 20,4, 21,5, 22,6},0 being the index of the first outer edge subdivision point, the outer position offset 6 is added, obtaining the index of the second inner edge subdivision point 6;1 is the index of the first outer edge subdivision point, the external position offset 6 is added to obtain the index 7 of the second inner edge subdivision point; 18 is the index of the first inner edge refinement point, the inner position offset 4 is added to obtain the index of the second inner edge refinement point 22, and so on to obtain the second output point sequence {6,7, 22, 23,7,8, 23, 24,8,9, 24, 10, 25, 11, 26, 12}.
The inner ring 301 has an index of {12, 13, 14, 15, 16, 17,0} at the second outer edge subdivision point of the second sewn portion P3, and an index of {26, 27, 28, 29, 18} at the second inner edge subdivision point. Then for the first sequence of output points {0,1, 18, 19,1,2, 19, 20,2,3, 20,4, 21,5, 22,6},0 is the index of the first outer edge subdivision point, then the index of the corresponding second outer edge subdivision point is 12;1 is the index of the first outer edge subdivision point, its corresponding index of the second inner edge subdivision point 13; the index of the second inner edge refinement point corresponding to the indexer with 18 being the first inner edge refinement point is 26, and so on, to obtain a second output point sequence {12, 13, 26, 27, 13, 14, 27, 28, 14, 15, 28, 16, 29, 17, 18,0}.
The final stitching effect of the inner loop 301 is shown in figure 5.
It should be noted that, in the above embodiment, the first sewn portion is taken as the sewn portion P1 as an example, the first sewn portion may be the sewn portion P2, and correspondingly, the second sewn portions are the sewn portions P1 and P3; or the first stitching portion may be the stitching portion P3, and the second stitching portion may be the stitching portion P2 and the stitching portion P3, which is not limited in this application.
Referring to fig. 4 and 6 together, for the inner ring 302, the index of the inner ring 302 at the first outer edge subdivision point of the first stitching portion P1 is {22, 21, 20, 19, 18}, the index of the first inner edge subdivision point is {32, 31, 30}, and the first output point sequence is {22, 21, 32, 31, 21, 20, 31, 19, 30, 18}.
The index of the inner ring 302 at the second outer edge subdivision point of the second stitching portion P2 is 26, 25, 24, 23, 22, and the index of the second inner edge subdivision point is 34, 33, 32. The amount of the inner position offset of the first inner edge subdivision point from the second inner edge subdivision point is 2, and the amount of the outer position offset of the first outer edge subdivision point from the second outer edge subdivision point is 4. Then after calculation a second output point sequence of 26, 25, 34, 33, 25, 24, 33, 23, 32, 22 is obtained.
The index of the inner ring 302 at the second outer edge subdivision point of the third stitching portion P3 is 18, 29, 28, 27, 26, and the index of the second inner edge subdivision point is 30, 35, 34. After calculation, a second output point sequence of {18, 29, 30, 35, 29, 28, 35, 27, 34, 26} is obtained.
For the inner ring 303, the index of the inner ring 303 at the first outer edge subdivision point of the first stitched portion P1 is {30, 31, 32}, the index of the first inner edge subdivision point is {36}, and the first output point sequence is {30, 31, 36, 32}.
The index of the inner ring 303 at the second outer edge subdivision point of the second stitching portion P2 is 32, 33, 34, and the index of the second inner edge subdivision point is 36. The calculation yields a second output point sequence of 32, 33, 36, 34.
The inner ring 303 has an index of {34, 35, 30} at the second outer edge subdivision point of the third suture part P3, and an index of {36} at the second inner edge subdivision point. The calculation yields a second output point sequence of 34, 35, 36, 30.
The final stitching effect of the inner loops 301, 302 and 303 is shown in figure 6.
The above method is explained below with reference to fig. 2.
Unlike the previous embodiment, the patch shown in fig. 2 is a quadrilateral. In the quadrangle, the distribution of the subdivided points on the sides has the same regularity, and therefore, the output point sequence of the stitched part positionally opposite to the first stitched part can be determined from the first output point sequence of the inner ring at the first stitched part.
Specifically, referring to fig. 2, a first output point sequence of the inner loop 201 at the first sewn portion P1 is obtained, and a second output point sequence of the inner loop 201 at the second sewn portion P3 can be determined based on the first output point sequence. Accordingly, a first sequence of output points of the inner loop 201 at the first stitched portion P2 is obtained, from which a second sequence of output points of the inner loop 201 at the second stitched portion P4 can be determined. The inner loop 202 is obtained in a similar manner at the output point sequence of each stitching portion and will not be described further herein.
Compared with the prior art that the four stitching parts of the patch need to be stitched, the stitching method and the stitching device only need to carry out stitching operation on the stitching part P1 and the stitching part P2, and the stitching part P3 and the stitching part P4 do not need to carry out stitching operation, so that the stitching complexity and the calculation amount are reduced on the whole, and the requirements of the tessellation process on hardware resources are reduced.
Fig. 7 illustrates a block diagram of an apparatus for tessellation. The apparatus includes a hull shader 701, a tessellator 702, and a domain shader 703. Among other things, hull shader 701 is used to determine subdivision factors for a patch to divide the patch into a suitable number of rings and a suitable number of subdivision points. Tessellator 702 is used to perform a stitching operation on a patch of patches to obtain a sequence of output points. The domain shader 703 is used to interpolate the output point sequence of the patch to obtain the coordinates of each point.
In a particular embodiment, the various steps of the output point sequence determination method described above may be performed by tessellator 702.
In this embodiment, tessellator 702 may perform stitching operations on inner edge subdivision points on the outermost ring and outer edge subdivision points on the outer edge, as well as on inner edge subdivision points of each inner ring within the first stitched portion and outer edge subdivision points on the outer edge. While no stitching operation need be performed for each inner ring at the inner edge subdivision point within the second stitched portion and at the outer edge subdivision point on the outer edge. This is because tessellator 702 may compute a sequence of output points for each inner loop at the second stitching portion in conjunction with the first sequence of output points and the positional mapping between the tessellation points.
Compared with the prior art, the tessellator 702 in the embodiment of the present application needs fewer stitched subdivision points, thereby reducing the requirements of the tessellation process on hardware resources.
In another embodiment, the domain shader 703 may perform the steps of the output point sequence determination method described above.
In this embodiment, tessellator 702 may perform a stitching operation on an inner edge subdivision point on the outermost ring and an outer edge subdivision point on the outer edge, and on an inner edge subdivision point within the first stitched portion and an outer edge subdivision point on the outer edge for each inner ring. Tessellator 702 transmits the output point sequence for the outermost ring, as well as the first output point sequence for each inner ring within the first stitching portion, to domain shader 703.
The domain shader 703 may calculate a sequence of output points for each inner ring at the second stitched portion by combining the first sequence of output points and the position mapping relationship between the refinement points.
Compared with the prior art, the tessellator 702 in the embodiment of the present application needs fewer stitched subdivision points, thereby reducing the requirements of the tessellation process on hardware resources. In addition, the amount of data transmitted from tessellator 702 to domain shader 703 is also reduced, reducing the data transmission bandwidth.
For example, in contrast to the prior art where tessellator 702 needs to transmit all output point sequences for the same ring to domain shader 703, when a patch is triangular in shape, tessellator 702 need only transmit 1/3 of the output point sequences in the same ring to domain shader 703, and the remaining output point sequences can be computed by domain shader 703.
Further, the domain shader 703 may store the first sequence of output points in a cache upon receiving the first sequence of output points for each inner ring within the first stitching portion. And when calculating the second output point sequence, obtaining the first output point sequence from the buffer.
For more specific implementation manners of the embodiments of the present application, please refer to the foregoing embodiments, which are not described herein again.
Referring to fig. 8, fig. 8 shows an output point sequence determining apparatus 80 for tessellation, and the output point sequence determining apparatus 80 for tessellation may include:
the image determining module 801 is configured to determine an image to be displayed, an outline of the image is divided into a plurality of patches, each patch has N edges, each patch is divided into a plurality of rings from inside to outside, and N is a positive integer greater than or equal to 3;
a dividing module 802 for dividing each patch into N stitched portions, each stitched portion being a triangle defined by a center point and an edge of the patch;
an obtaining module 803, configured to obtain, for each inner ring, a first output point sequence of the inner ring at a first stitched portion, the first output point sequence being stitched for an inner edge subdivision point of the inner ring on an inner edge of the first stitched portion and an outer edge subdivision point on an outer edge of the inner ring, the inner ring being a ring of the plurality of rings other than an outermost ring, the first stitched portion being selected from the N stitched portions;
an output point sequence determining module 804, configured to determine, for each inner ring, a second output point sequence of the inner ring at a second stitched portion according to an arrangement order of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and a position mapping relationship between the subdivision point of the inner ring at the first stitched portion and the subdivision point at the second stitched portion, where the second stitched portion is a stitched portion other than the first stitched portion or a stitched portion opposite in position to the first stitched portion among the N stitched portions.
According to the embodiment of the application, the stitching operation can be reduced, namely the number of the subdivision points needing stitching is reduced, so that the requirement of the tessellation process on hardware resources is reduced. In addition, after the number of the subdivided points required to be stitched is reduced, the number of the subdivided points in the output point sequence required to be transmitted by the tessellator performing the stitching operation is also reduced, thereby reducing the data transmission bandwidth.
In one non-limiting embodiment, the positional mapping includes a first mapping of the inner ring at a first inner edge subdivision point of the first stitch portion and the inner ring at a second inner edge subdivision point of the second stitch portion, and a second mapping of the inner ring at a first outer edge subdivision point of the first stitch portion and the inner ring at a second outer edge subdivision point of the second stitch portion. For a first inner edge subdivision point in the first output point sequence, determining an index of a corresponding second inner edge subdivision point in the second output point sequence according to the index of the first inner edge subdivision point and the first mapping relation; and determining the index of the corresponding second outer edge subdivision point in the second output point sequence according to the index of the first outer edge subdivision point and the second mapping relation for the first outer edge subdivision point in the first output point sequence.
The technical scheme of the application realizes the mapping from the first output point sequence to the second output point sequence by utilizing the regularity of the distribution of each internal ring at the subdivision point position of each stitching part and the consistency of the stitching sequence, thereby reducing the stitching operation and the data transmission bandwidth.
In a specific implementation, the output dot sequence determining device 80 for tessellation may correspond to a Chip having an output dot sequence determining function in a terminal device, such as a System-On-a-Chip (SOC), a baseband Chip, and the like; or the terminal equipment comprises a chip module with an output point sequence determination function; or to a chip module having a chip with data processing function, or to a terminal device.
Other relevant descriptions of the output point sequence determination device 80 can refer to the relevant descriptions in the foregoing embodiments, and are not repeated here.
Each module/unit included in each apparatus and product described in the above embodiments may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device and product applied to or integrated with the chip module, each module/unit included in the device and product may be implemented by hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least part of the modules/units may be implemented by a software program running on a processor integrated inside the chip module, and the rest (if any) part of the modules/units may be implemented by hardware such as a circuit; for each device and product applied to or integrated in the terminal device, each module/unit included in the device and product may be implemented by hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal device, or at least a part of the modules/units may be implemented by a software program running on a processor integrated in the terminal device, and the rest (if any) part of the modules/units may be implemented by hardware such as a circuit.
The embodiment of the application also discloses a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium, and when the computer program runs, the steps of the method shown in fig. 1 can be executed. The storage medium may include a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic or optical disk, and the like. The storage medium may further include a non-volatile (non-volatile) memory or a non-transitory (non-transient) memory, etc.
The "plurality" appearing in the embodiments of the present application means two or more.
The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. The procedures or functions according to the embodiments of the present application are wholly or partially generated when the computer instructions or the computer program are loaded or executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not imply any order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus, and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately and physically included, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods described in the embodiments of the present application.
Although the present application is disclosed above, the present application is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and it is intended that the scope of the present disclosure be defined by the appended claims.
Claims (14)
1. A method for determining a sequence of output points for a tessellation comprising:
determining a graph to be displayed, wherein the outline of the graph is divided into a plurality of patches, each patch is provided with N edges, each patch is divided into a plurality of rings from inside to outside, and N is a positive integer greater than or equal to 3;
dividing each panel into N stitched portions, each stitched portion being a triangle defined by a center point and an edge of the panel;
obtaining, for each inner ring, a first sequence of output points of the inner ring at a first stitched portion, the first sequence of output points being stitched for an inner edge subdivision point of the inner ring on an inner edge and an outer edge subdivision point on an outer edge of the first stitched portion, the inner ring being a ring of the plurality of rings other than an outermost ring, the first stitched portion being selected from the N stitched portions;
and for each internal ring, determining a second output point sequence of the internal ring at a second suture part according to the arrangement sequence of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and the position mapping relation of the subdivision point of the internal ring at the first suture part and the subdivision point of the internal ring at a second suture part, wherein the second suture part is other suture parts except the first suture part in the N suture parts or the suture parts opposite to the first suture part in position.
2. A method for tessellating output point sequence determination according to claim 1, wherein an order of arrangement of each second inner edge subdivision point and second outer edge subdivision point in the second output point sequence coincides with an order of arrangement of corresponding first inner edge subdivision point and first outer edge subdivision point in the first output point sequence.
3. The method of claim 1, wherein the positional mapping comprises a first mapping of a first inner edge subdivision point of the inner ring at a first stitch portion to a second inner edge subdivision point of the inner ring at a second stitch portion, and a second mapping of a first outer edge subdivision point of the inner ring at the first stitch portion to a second outer edge subdivision point of the inner ring at the second stitch portion, the determining the second sequence of output points of the inner ring at the second stitch portion comprises:
for a first inner edge subdivision point in the first output point sequence, determining an index of a corresponding second inner edge subdivision point in the second output point sequence according to the index of the first inner edge subdivision point and the first mapping relation;
and for a first outer edge subdivision point in the first output point sequence, determining an index of a corresponding second outer edge subdivision point in the second output point sequence according to the index of the first outer edge subdivision point and the second mapping relation.
4. The method of claim 1, wherein the positional mapping includes an inner positional offset of the inner ring at a first inner edge subdivision point of the first stitched portion relative to a second inner edge subdivision point of the second stitched portion and an outer positional offset of the inner ring at a first outer edge subdivision point of the first stitched portion relative to a second outer edge subdivision point of the second stitched portion, and wherein determining the second sequence of output points of the inner ring at the second stitched portion comprises:
for a first inner edge subdivision point in the first output point sequence, determining an index of a corresponding second inner edge subdivision point in the second output point sequence according to the index of the first inner edge subdivision point and the internal position offset;
and for a first outer edge subdivision point in the first output point sequence, determining the index of a corresponding second outer edge subdivision point in the second output point sequence according to the index of the first outer edge subdivision point and the external position offset.
5. The method of claim 1 wherein obtaining the first sequence of output points for the inner ring at the first stitched portion comprises:
stitching the inner edge subdivision point on the inner edge of the first stitched portion and the outer edge subdivision point on the outer edge of the inner ring to obtain the first output point sequence.
6. The output point sequence determination method for tessellation of claim 5, wherein stitching the inner edge subdivision point on the inner edge and the outer edge subdivision point on the outer edge of the first stitched portion for the inner ring comprises:
determining a sequence of outer edge subdivision points on an outer edge, a sequence of inner edge subdivision points on an inner edge, and a stitching order of the inner ring within the first stitched portion, and stitching the outer edge subdivision points and the inner edge subdivision points in the stitching order, the stitching order representing an order of movement within the sequence of outer edge subdivision points and the sequence of inner edge subdivision points when stitching.
7. The method of claim 1, wherein said obtaining the first sequence of output points for the inner ring at the first stitched portion comprises:
receiving a first sequence of output points from a tessellator stitched for the inner ring at an inner edge subdivision point on an inner edge and an outer edge subdivision point on an outer edge of a first stitched portion.
8. The method of claim 7, wherein the first sequence of output points is stored in a cache, and wherein determining the inner ring further comprises, prior to the second sequence of output points for the second stitched portion:
and acquiring the first output point sequence from the buffer.
9. A method for tessellation of output point sequence determination according to claim 1, wherein, when N is 3, the second stitched portion is the other of the 3 stitched portions except the first stitched portion; and when N is 4, the second sewed portion is a sewed portion opposite to the first sewed portion in position among the 4 sewed portions.
10. A method for output point sequence determination for tessellation according to claim 1, characterized in that the number of tessellation points on each edge in each patch is the same.
11. The method of any of claims 1 to 10, further comprising:
for each inner loop, combining the first sequence of output points for that inner loop at the first stitching portion and the second sequence of output points for that inner loop at the second stitching portion to obtain a sequence of output points for that inner loop.
12. An apparatus for determining a sequence of output points for a tessellation, comprising:
the image determining module is used for determining an image to be displayed, the outline of the image is divided into a plurality of patches, each patch is provided with N edges, each patch is divided into a plurality of rings from inside to outside, and N is a positive integer greater than or equal to 3;
a dividing module for dividing each patch into N stitched portions, each stitched portion being a triangle defined by a center point and an edge of the patch;
an obtaining module for obtaining, for each inner ring, a first output point sequence of the inner ring at a first stitched portion, the first output point sequence being stitched for an inner edge subdivision point on an inner edge and an outer edge subdivision point on an outer edge of the inner ring at the first stitched portion, the inner ring being a ring of the plurality of rings other than an outermost ring, the first stitched portion being selected from the N stitched portions;
and an output point sequence determining module, configured to determine, for each inner ring, a second output point sequence of the inner ring at a second stitched portion according to an arrangement order of the first inner edge subdivision point and the first outer edge subdivision point in the first output point sequence and a position mapping relationship between the subdivision point of the inner ring at the first stitched portion and the subdivision point of the inner ring at the second stitched portion, where the second stitched portion is a stitched portion other than the first stitched portion or a stitched portion opposite in position to the first stitched portion in the N stitched portions.
13. A computer-readable storage medium, characterized in that it stores a computer program which, when being executed by a processor, carries out the steps of the method for determining a sequence of output points for a tessellation according to any one of claims 1 to 10.
14. A terminal device, characterized in that it comprises a memory and a processor, said memory having stored thereon a computer program being executable on said processor, when executing said computer program, performing the steps of the output point sequence determination method for tessellation according to any of claims 1 to 10.
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