CN102096948A - Meshsing method suitable for graphics hardware - Google Patents
Meshsing method suitable for graphics hardware Download PDFInfo
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Abstract
The invention discloses a meshing method suitable for graphics hardware, which belongs to the field of tessellation design methods suitable for graphics hardware and is proposed aiming to solve the problem on hardware implementation efficiency when the surface of a graph is subdivided into smaller polygons in graph tessellation acceleration processing. In the meshing method provided by the invention, a curved surface patch is decomposed into an internal rectangular meshing part for surface patch and a bounding area meshing part through meshing, multiplication and division operations consuming longer time for hardware implementation are decreased, and fixed point integer addition and comparison operations are adopted for the hardware implementation. The meshing method is mainly used for a meshing processing unit for tessellation in a graph processor and is favorable for effectively improving hardware implementation efficiency.
Description
1 technical field
The present invention proposes branch that a kind of suitable graphic hardware realizes (Tessellator) method of formatting, and can realize the function of surface subdivision efficiently.The branch that the present invention the proposes method of formatting avoids taking the multiplication and division operation of more ground of hardware resource as far as possible, is fit to employing graphic hardware circuit and realizes, belongs to the surface subdivision method for designing field that is applicable to graphic hardware.
Graphics process needs huge computing power, realizes the real-time generation of figure.In three-dimensional applications or the scene of game, in order to obtain exquisiteness, real display effect after usually the body surface branch being formatted, produces tens thousand of millions of polygons that arrive, and is generally triangle, dyes processing such as pinup picture again.Realize that the polygon of such enormous amount handles in real time, its performance requirement is higher, needs the support of various graphics hardware accelerators, comprising the hardware supported that curve and curved surface are calculated.
What graphic hardware was drawn is the most basic pel, i.e. point, straight line and polygon (normally triangle), and a level and smooth curved surface is by using a large amount of small polygons to simulate.Surface subdivision (Tessellation) is exactly a curved surface to be divided format to produce a series of polygonal technology.In graphic system early, surface subdivision realizes that by software up-to-date graphic process unit has then comprised the hardware of finishing surface subdivision, thereby has improved the speed of curved surface rendering.
2 background technologies
The thought of surface subdivision can be traced back to the polygon chamfer algorithm that the 1950's, G.Rham proposed, and 1974, the curve divided method that Chaikin proposes.Catmull in 1978 and Clark, Doo and Sabin are generalized to arbitrary topology with three times and secondary uniform B-spline surfaces respectively, have proposed famous Catmull-Clark segmentation and Doo-Sabin algorithm of subdivision.The Loop of Washington, DC university in 1987 has invented famous Loop segmentation pattern, and this method is still one of the most frequently used segmentation pattern so far; Nineteen ninety, Dyn etc. have proposed butterfly (Butterfly) segmentation on interpolation triangle gridding summit; In the same year, Kobbelt has proposed the Kobbelt segmentation on interpolation quadrilateral summit; 1997, Peters and Reif provided the middle limit segmentation based on quadrilateral mesh; 2000, Kobbelt provided the triangular gridding subdivision pattern of antithesis again
Segmentation, Labsik and Greiner have proposed interpolation on this basis
Segmentation; 2002, Loop provided three fens segmentation forms based on triangle gridding; Stam in 2003 and Loop have proposed the hybrid subdivision based on triangle gridding and quadrilateral mesh.
The most significant variation is exactly to increase surface subdivision (Tessellation) function in Direct11 and OpenGL 4.0, and just this function will be realized by graphic process unit (GPU).Realize the surperficial refinement of LOD (Level Of Detail) like this by graphic hardware, can reach very true fine and smooth picture effect, bring into play the performance of hardware simultaneously again as much as possible.
Realize i.e.: Hull Shader (shell tinter), Tessellator (branch format processing unit) and Domain Shader (territory tinter) by three functional modules in DirectX 11 mean cambers segmentations (Tessellation) function.In DirectX 11, Hull Shader and Domain Shader are programmable tinters, and Tessellator then is the accelerator of being realized by the mounting hardware algorithm fully.
Fig. 1 .Direct3D 11 pipeline organization synoptic diagram
As shown in Figure 1, Hull Shader is responsible for collecting the parameter information of figure curved surface, is used for defining the parametric variable of curved surface as reference mark etc.HS produces a series of dough sheet (surface patches) and corresponding with it LOD information according to the curved surface expression formula that is generated by the reference mark.
Tessellator is a fixed function module, and it does not need the control point information of curved surface, and its input is dough sheet and corresponding LOD information.Tessellator is subdivided into several quadrilaterals or triangle according to LOD information with dough sheet.If quadrilateral also can further resolve into two triangles.These vertexs of a triangle are accompanied by their parameter coordinate five equilibrium information of formatting in dough sheet and send into the next stage processing.
Domain Shader carries out individual processing according to the parameter coordinate in the dough sheet to each vertex of a triangle, and calculates from its subsidiary branch is formatted information.Domain Shader can calculate the pairing information in each summit, comprising: coordinate data, texture coordinate etc., and this summit and corresponding vertex information transmitted to next stage.
Each module is carried out various graphic operations according to vertex information among the DirectX 11 of back, comprise: operations such as projective transformation, three-dimensional are cut out, the viewport transform, pel assembling, rasterisation, pixel dyeing and blend of colors finally present desired curved surface on screen.
Though the method for surface subdivision is a lot, because a lot of multiplication and division operations is arranged, the hardware implementation efficiency is lower, the method for our proposition, and the multiplication and division operation is avoided in main addition and the comparison operation of adopting the fixed point integer as far as possible, is applicable to the hardware realization.
3 summary of the invention
The objective of the invention is to propose a kind of method that in graphic process unit, is applicable to hard-wired highly effective curved face segmentation.The present invention is directed to the Tessellator in Direct 11 pipeline organizations, propose the core implementation method of this module.
The input of Tessellator is the dough sheet (surface patches) of curved surface, and corresponding with it LOD information.Each dough sheet all is to be made of the regular rectangular shape of inside and outside irregular border, as shown in Figure 2.
Fig. 2 dough sheet structural representation
The internal rule rectangle of dough sheet can be divided into a lot of little rectangular nodes according to LOD information.As shown in Figure 2, the height LOD value LOD of regular rectangular shape in the dough sheet
H=5, width LOD value LOD
W=10, so regular rectangular shape can be divided into 50 rectangular nodes in the dough sheet.Four borders of dough sheet have constituted quadrilateral, and the LOD value on every limit can have nothing in common with each other.As shown in Figure 2, the LOD value LOD of left margin
F=8, the LOD value LOD of right margin
R=7, the LOD value LOD of coboundary
T=8, the LOD value LOD of lower boundary
B=5.
In the methods of the invention, be by from left to right to the grid vertex of regular rectangular shape in the dough sheet, order from top to bottom is numbered.To the borderline summit of dough sheet is from by the lower left corner, is numbered along clockwise direction.Divide the specific implementation method of the method for formatting can be divided into two branches: the branch of regular rectangular shape is formatted and the branch of dough sheet borderline region is formatted in the dough sheet.Below be specifying of two branching methods.
3.1 the branch of regular rectangular shape is formatted in the dough sheet
The lattice of regular rectangular shape is divided into two steps in the dough sheet.At first be the internal rule rectangle of dough sheet will be divided into several rectangular blocks (rectangle), comprise several rectangular nodes (mesh) in each rectangular block.This step requires to reduce the rectangular block quantity that transmits to next stage as far as possible, can guarantee that again the operand of next step processing is suitable simultaneously.
Fig. 3 dough sheet internal rule rectangle is divided into the rectangular block synoptic diagram
As shown in Figure 3, each rectangular block be by two row three row totally 6 rectangular nodes constitute, so each rectangular block comprises 12 grid vertexes.In order to make division methods easy, the order that regulation is divided from left to right, is carried out successively for to make progress the end of from.May be different at rectangular block topmost with other rectangular blocks with rightmost rectangular block, as shown in Figure 3.The false code of this step is as follows:
During superincumbent false code is described, LOD
WAnd LOD
HBe respectively the width and the height LOD value of dough sheet internal rule rectangle.And bw and bh are respectively the width value and the height value of rectangular block.Superincumbent method all is integer operation, and has only addition and compare operation do not have multiplication and division in describing, and makes hardware realize simplicity of design.
It is less important handles each rectangular block.Promptly from rectangular block, isolate rectangular node, and each rectangular node is divided into two triangles.The false code of specific implementation method is as follows:
Superincumbent false code though used multiplying, can be used n* (LOD in describing
H+ 1) and (n+1) * (LOD
H+ 1) such two simple counters are realized accumulating operation.Therefore, can in realizing, hardware not use multiplier yet.Next the Build_Triangle step is the vertex of a triangle coordinate, from being converted to parameter coordinate dough sheet { u, v, w}, and calculate the corresponding data message of formatting that divides at the node serial number of internal rule rectangle originally.
In Tessellate Mesh step, each circulation can both obtain a rectangular block.And in the Generate_Rectangle step, each circulation can both be divided into two triangles to a rectangular node.In internal rule rectangle segmentation, these two steps LOD that circulates altogether
W* LOD
HInferior, all have only fixed-point number addition and compare operation at every turn, therefore total algorithm complex is O (LODw*LOD
H).Again because the quantity of rectangular node is LODw*LOD in the regular rectangular shape in the dough sheet
HIndividual, so this method performance is optimum.
3.2 dough sheet borderline region branch is formatted
The dough sheet borderline region branch method of formatting shows complicated slightly, and purpose is will be with the border of dough sheet and the white space between the internal rule rectangle with triangle " stitching ", as shown in Figure 2.Only need fixed-point number additive operation and compare operation in the method in most cases, multiplying only need be used when initial and once get final product.Dough sheet borderline region branch is formatted needs two steps.At first four borderline regions are handled respectively, comprised some parameter informations of initialization etc., the false code of the specific implementation of this step is as follows:
During superincumbent false code is described, respectively to four limits of dough sheet, from the left side, in the direction of the clock, the branch that the carries out borderline region successively processing of formatting.Wherein, Ns is the borderline node index value of dough sheet, N
eBe the node index value on regular rectangular shape border in the dough sheet, as shown in Figure 2.
The processing of formatting is divided on the border of its less important opposite sheet and the border of regular rectangular shape on the other side, and promptly triangle " stitching " is handled.The false code of this step specific implementation is as follows:
During superincumbent false code is described, in most cases have only fixed-point number addition and comparison operation.When this step is initial, need use the fixed-point number multiplication one time,, therefore, also multiplication result can be passed by Hull Shader and come, can save Multiplier Design at this like this owing to be the multiplying of given parameter.Next in the Make_Triangle step,, be converted to parameter coordinate in dough sheet { u, v, w}, and calculate the corresponding data message of formatting that divides from original node index value inner and outer boundary with the vertex of a triangle coordinate.
In the Tessellate_External step, successively four borderline regions are carried out initialization process.And in the Border_Stitching step, every circulation primary all can obtain a triangle, and LOD altogether circulates
E+ LOD
IInferior, so the computation complexity of this method is O (LOD
E+ LOD
I).Again because the triangle number of every border correspondence is LOD
E+ LOD
IIndividual, so the performance of this method is optimum.
4 description of drawings
Fig. 1 .Direct3D 11 pipeline organization synoptic diagram
Fig. 2. the dough sheet structural representation
Fig. 3. dough sheet internal rule rectangle is divided into the rectangular block synoptic diagram
Fig. 4. divide the method hardware of formatting to realize synoptic diagram
5 embodiments
5.1 hardware configuration design
Adopt the branch of our bright proposition to format the designed hardware configuration of disposal route as shown in Figure 4.In this hardware configuration, Tessellator inside at first receives the dough sheet information of bringing from Hull Shader with the Branch module, comprises the width and the height LOD value of the internal rule rectangle of dough sheet, and the information such as LOD value on 4 borders of dough sheet.Handle these data messages in the Branch inside modules, then the data message packing is divided into two branch roads and transmits.Processing that the branch that these two branch roads carry out the internal rule rectangle of dough sheet is respectively formatted and the branch of dough sheet borderline region is formatted.
Fig. 4 branch method hardware of formatting is realized synoptic diagram
In the branch of the internal rule rectangle of dough sheet was formatted this branch, the Tessellate_Mesh module received the width of internal rule rectangle of the dough sheet that transmits from the Branch module and the LOD value (LOD of height
WAnd LOD
H), and the width of rectangular block and height value (bw and bh).In the Tessellat_Mesh inside modules is handled, the internal rule rectangle of dough sheet is divided into several rectangular blocks.In Tessellat_Mesh inside modules state machine, each beat can both obtain a rectangular block, then this rectangular block is transmitted to next stage.
The Generate_Rectangle module receive the rectangular block that transmits from the Tessellate_Mesh module start point information (i, j) and the width elevation information (w, h).In the Generate_Rectangle inside modules is handled, at first rectangular block is decomposed into several rectangular nodes (mesh), and then single rectangular node is divided into two triangles.In Generate_Rectangle inside modules state machine, each beat can both obtain two triangles, then these two vertex of a triangle information is transmitted to next stage.
The Build_Triangle module receives the vertex of a triangle data message (V0, V1, V2) that sends from the Generate_Rectangle module.Because a beat has two triangles and sends, therefore design two Build_Triangle modules and receive information.During the Build_Triangle inside modules is handled, with the vertex of a triangle coordinate, from being converted to parameter coordinate dough sheet { u, v, w}, and calculate the corresponding data message of formatting that divides at the node serial number of internal rule rectangle originally.In Generate_Rectangle inside modules state machine, each beat can both calculate the parameter coordinate on an Atria summit, and the branch that will comprise this information then data of formatting transmit to next stage Domain Shader.
In the branch on dough sheet border is formatted this branch, the Tessellate_External module receives the boundary information of the dough sheet that transmits from the Branch module, the width and the height LOD value that comprise the internal rule rectangle of dough sheet, and the information such as LOD value on 4 borders of dough sheet.In the Tessellate_External inside modules is handled, calculate 4 border branches parameters needed of formatting, as information such as inner and outer boundary start node index value and step-lengths.In the internal state machine of Tessellate_External module, each beat can calculate a borderline region branch needed primary data information of formatting, and transmits to next stage then.
The Border_Stitching module receives the inside and outside border LOD value (LOD that sends from the Tessellate_External module
IAnd LOD
E), and step-length (stride), inside and outside border start node index value (N
eAnd N
s).In the Border_Stitching module, with inside and outside borderline region with triangle " stitching " one by one.In Border_Stitching module status machine, each beat can both obtain a triangle, and three index values of summit in inside and outside border, then this information is transmitted to next stage.
The Make_Triangle module receive from leg-of-mutton three summits that the Border_Stitching module transmits the data messages such as index value inner and outer boundary (Ne, Ns, Ne/Ns+1).In the Make_Triangle inside modules is handled,, be converted to parameter coordinate in dough sheet { u, v, w}, and calculate the corresponding data message of formatting that divides from original node index value inner and outer boundary with the vertex of a triangle coordinate.In Make_Triangle inside modules state machine, each beat can both calculate the parameter coordinate on an Atria summit, and the branch that will comprise this information then data of formatting transmit to next stage Domain Shader.
Hardware configuration according to the designed Tessellator of the bright method of we adopts pipeline work.Under the streamline full load situation, each beat can be exported 3 triangles.In specific implementation, most computings all are fixed-point number addition and compare operation.Have only the minority computing need use multiply operation in the method, can avoid by some modes, as previously mentioned.This method has taken into full account the realization of hardware when design, than being easier to improve the computing concurrency.
5.2 simulation result checking
Write corresponding C Language Simulation program according to the inventive method, respectively the internal rule rectangle of dough sheet and dough sheet borderline region have been carried out dividing and formatted.The height LOD value LOD of regular rectangular shape in the dough sheet of the internal rule rectangle of setting dough sheet
H=5, width LOD value LOD
W=10.It highly is 2 that each rectangular block initially is made as, and width is 3.The internal rule rectangle branch of dough sheet formatted, and the result is as shown in table 1 in institute:
The branch of the table 1 dough sheet internal rule rectangle result that formats
As shown in table 1, regular rectangular shape at first is divided into rectangular block in the dough sheet, further rectangular block is divided into rectangular node then, and each rectangular node is divided into two triangles again.Demonstrate rectangular block and its triangle that comprises of division place among Fig. 5.
Set the LOD value on four borders of dough sheet, the LOD value LOD of left margin
F=8, the LOD value LOD of right margin
R=7, the LOD value LOD of coboundary
T=8, the LOD value LOD of lower boundary
B=5.Divide the gained result that formats as shown in table 2 to the dough sheet borderline region:
The table 2 dough sheet borderline region branch result that formats
As shown in table 2, the borderline region of dough sheet along clockwise direction, divides successively and formats from left margin.Each borderline region all is to form with triangle " stitching ".Each leg-of-mutton three summit is provided by the node index value of outer boundary and inner boundary respectively.
By the software emulation checking, further illustrate the correctness and the validity of the inventive method.Surface subdivision is an important indicator weighing graphic process unit design performance quality.The bright method of we has proposed effective implementation method at the branch problem of formatting in the surface subdivision, and very right hardware is realized, can effectively improve the graphic process unit performance.
Claims (1)
1. the branch of the suitable graphic hardware method of formatting, this method comprises that the inner rectangular branch is formatted and the borderline region branch two parts of formatting, in partition process (except initialization time) only used the addition and the comparison operation of fixed point integer, and can be during interior partitive case according to the hardware configuration division that walks abreast, divide the result who formats to comprise orderly vertex index and relevant parameters coordinate { u, v}; Wherein the borderline region branch implementation method of formatting is: the LOD value on dough sheet border is multiplied each other with the LOD value of corresponding internal rule square boundary, with the condition of this product as the judgement loop termination, and the node index value is by step-length alternately growth successively separately on node index value and the inner rectangular border on the dough sheet border, and step-length is the fixed point integer; The inner rectangular branch implementation method of formatting is: the internal rule rectangle of dough sheet at first is divided into several rectangular blocks, then each rectangular block is divided into some rectangular nodes, at last each rectangular node is divided into two triangles.
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| CN102999945A (en) * | 2011-09-15 | 2013-03-27 | 北京进取者软件技术有限公司 | Mesh surface area division method for modeling of embossment model |
| CN104933225A (en) * | 2015-05-25 | 2015-09-23 | 中国科学院过程工程研究所 | Method for realizing computational fluid dynamics large-scale real-time simulation |
| CN108597590A (en) * | 2018-05-08 | 2018-09-28 | 上海嘉奥信息科技发展有限公司 | The arbitrary layer data display methods of volume data based on GPU operations and system |
| CN114494651A (en) * | 2022-04-18 | 2022-05-13 | 龙芯中科技术股份有限公司 | Tessellation processing method, tessellation processing device, electronic device and storage medium |
| CN115861512A (en) * | 2023-01-31 | 2023-03-28 | 南京砺算科技有限公司 | Method and device for determining output point sequence for tessellation and storage medium |
| CN116597109A (en) * | 2023-01-13 | 2023-08-15 | 东莘电磁科技(成都)有限公司 | Complex three-dimensional curved surface co-grid generation method |
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| CN102999945A (en) * | 2011-09-15 | 2013-03-27 | 北京进取者软件技术有限公司 | Mesh surface area division method for modeling of embossment model |
| CN102999945B (en) * | 2011-09-15 | 2016-01-06 | 北京进取者软件技术有限公司 | A kind of grid surface region partitioning method for embossment model modeling |
| CN104933225A (en) * | 2015-05-25 | 2015-09-23 | 中国科学院过程工程研究所 | Method for realizing computational fluid dynamics large-scale real-time simulation |
| CN104933225B (en) * | 2015-05-25 | 2018-01-09 | 中国科学院过程工程研究所 | The method for realizing the extensive real-time Simulation of Fluid Mechanics Computation |
| CN108597590A (en) * | 2018-05-08 | 2018-09-28 | 上海嘉奥信息科技发展有限公司 | The arbitrary layer data display methods of volume data based on GPU operations and system |
| CN114494651A (en) * | 2022-04-18 | 2022-05-13 | 龙芯中科技术股份有限公司 | Tessellation processing method, tessellation processing device, electronic device and storage medium |
| CN116597109A (en) * | 2023-01-13 | 2023-08-15 | 东莘电磁科技(成都)有限公司 | Complex three-dimensional curved surface co-grid generation method |
| CN116597109B (en) * | 2023-01-13 | 2023-12-22 | 东莘电磁科技(成都)有限公司 | Complex three-dimensional curved surface co-grid generation method |
| CN115861512A (en) * | 2023-01-31 | 2023-03-28 | 南京砺算科技有限公司 | Method and device for determining output point sequence for tessellation and storage medium |
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