CN115858432A - Access method, device, electronic equipment and readable storage medium - Google Patents

Access method, device, electronic equipment and readable storage medium Download PDF

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Publication number
CN115858432A
CN115858432A CN202310186880.5A CN202310186880A CN115858432A CN 115858432 A CN115858432 A CN 115858432A CN 202310186880 A CN202310186880 A CN 202310186880A CN 115858432 A CN115858432 A CN 115858432A
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address
bit
access
operation mode
address space
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CN115858432B (en
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李丹
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Shanghai Lichi Semiconductor Co ltd
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Shanghai Lichi Semiconductor Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses an access method, an access device, an electronic device and a readable storage medium, wherein the method comprises the following steps: acquiring an access request sent by an APB main module, wherein the access request comprises an access address and a control signal; the access address comprises a virtual address and a real address; the virtual address is used for representing a bit operation mode of an address space register appointed bit domain corresponding to the real address; determining an access type according to the control signal; determining a corresponding bit operation mode according to the virtual address; and accessing the specified bit domain of the address space register corresponding to the actual address according to the determined access type and the determined bit operation mode. According to the method and the device, the bit operation mode of the address space register designated bit field corresponding to the actual address can be determined only by analyzing the virtual address in the access address, so that the specific bit operation of the address space register designated bit field is realized, an additional address decoding unit is not required to be configured, and the design cost of the SOC system can be reduced.

Description

Access method, device, electronic equipment and readable storage medium
Technical Field
The present application relates to the field of system-on-chip technologies, and in particular, to an access method, an access device, an electronic device, and a readable storage medium.
Background
Peripheral Bus (APB) peripherals are used as a part of a System On Chip (SOC) System, and mainly access configuration registers inside the peripherals through the APB to complete information interaction between a processor and the peripherals. With the increase of application scenarios, from the software application side, a specific bit operation is often required to be performed on a specified bit field of the same address space inside the peripheral device to implement a specific application scenario. However, since the bit domain function definitions and register attributes of the configuration register corresponding to a single address space inside the peripheral are often diverse and different, in order to meet the requirement of an application scenario for performing specific bit operations on a specified bit domain of the same address space, currently, it is commonly adopted that, in the stage of designing an APB peripheral hardware circuit, a plurality of address spaces are allocated to specific function registers, and bit operations that software expects to execute are distinguished by different address spaces. However, a plurality of address spaces are allocated to a specific function register to realize specific bit operation of a designated bit field, and for the specific function register, an additional address decoding unit needs to be configured to decode different address spaces, so that the design cost of the SOC system is increased, and because the address decoding unit needs to occupy the area of the SOC system, different bit access requirements can be realized only for a part of registers.
Disclosure of Invention
In view of the above, embodiments of the present application provide an access method, an access apparatus, an electronic device, and a readable storage medium, so as to solve at least the above technical problems in the prior art.
According to a first aspect of the present application, an embodiment of the present application provides an access method, which is applied to an APB peripheral, where the access method includes: acquiring an access request sent by an APB main module, wherein the access request comprises an access address and a control signal; the access address comprises a virtual address and a real address; the virtual address is used for representing a bit operation mode of an address space register appointed bit domain corresponding to the real address; determining an access type according to the control signal; determining a corresponding bit operation mode according to the virtual address; and accessing the specified bit domain of the address space register corresponding to the actual address according to the determined access type and the determined bit operation mode.
Optionally, the bit operation modes include: normal read and write operations, 1 bit setting operations, 0 bit setting operations, and bit conversion operations.
Optionally, determining a corresponding bit operation mode according to the virtual address includes:
and determining a corresponding bit operation mode according to the virtual address and the mapping relation between the virtual address and the bit operation mode.
Optionally, accessing the specified bit field of the address space register corresponding to the real address according to the determined access type and the determined bit operation mode, including:
if the access type is read access, performing read access on the specified bit domain of the address space register corresponding to the actual address in the first clock cycle;
and if the access type is write access, determining data to be written in the address space register designated bit domain corresponding to the actual address in a first clock cycle according to the bit operation mode, and writing the data to be written in the address space register designated bit domain corresponding to the actual address in a second clock cycle.
Optionally, determining data to be written to the address space register specified bit domain corresponding to the real address in the first clock cycle according to the bit operation mode includes:
if the bit operation mode is normal read-write operation, determining that the data to be written in the designated bit domain of the address space register corresponding to the actual address is the written data carried in the access request in a first clock cycle;
and if the bit operation mode is 1-bit setting operation, 0-bit setting operation or bit conversion operation, performing read access on the address space register corresponding to the actual address in a first clock cycle to obtain the storage data of each bit domain of the address space register corresponding to the actual address, and determining the data to be written in the specified bit domain of the address space register corresponding to the actual address based on the bit operation mode, the storage data of each bit domain and the write-in data carried in the access request.
Optionally, the access method further includes:
determining the current value of a register based on the storage data of each bit field of an address space register corresponding to the actual address;
determining an expected value of a register based on the write-in data carried in the access request;
based on the current value and the desired value, a difference in the values of the registers before and after the 1-bit-set operation, the 0-bit-set operation, or the shift bit operation is determined.
Optionally, the access method further includes:
and storing the storage data of each bit field of the address space register corresponding to the real address so as to restore the data of the address space register corresponding to the real address.
According to a second aspect of the present application, an embodiment of the present application provides an access apparatus, which is applied to an APB peripheral, and the access apparatus includes:
the acquisition module is used for acquiring an access request sent by the APB main module, wherein the access request comprises an access address and a control signal; the access address comprises a virtual address and a real address; the virtual address is used for representing a bit operation mode of an address space register appointed bit domain corresponding to the real address;
the first determining module is used for determining the access type according to the control signal;
a second determining module, configured to determine a corresponding bit operation mode according to the virtual address;
and the access module is used for accessing the specified bit domain of the address space register corresponding to the actual address according to the determined access type and the determined bit operation mode.
According to a third aspect of the present application, an embodiment of the present application provides an electronic device, including:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of accessing as in the first aspect or any of the embodiments of the first aspect.
According to a fourth aspect of the present application, an embodiment of the present application provides a computer-readable storage medium, where computer instructions are stored, and the computer instructions are configured to cause a computer to execute the access method according to the first aspect or any implementation manner of the first aspect.
According to the access method, the access device, the electronic device and the readable storage medium provided by the embodiment of the application, the virtual address is added into the access address of the access request of the APB main module, and is used for representing the bit operation mode of the address space register appointed bit field corresponding to the actual address, so that the bit operation mode of the address space register appointed bit field corresponding to the actual address can be determined only by analyzing the virtual address in the access address, and further the specific bit operation of the address space register appointed bit field corresponding to the actual address is realized without configuring an additional address decoding unit, and the design cost of an SOC (system on chip) system can be reduced; the bit operation mode of the designated bit domain of the address space register corresponding to the actual address is determined in a virtual address mode, the logic cost is low, and the method can be expanded to the whole APB peripheral register and is not limited to a part of registers; and because the decoding process of an additional address decoding unit is not needed, the access speed of the APB peripheral equipment can be improved, and the rapid access of the APB peripheral equipment register bit operation can be realized.
The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.
Drawings
Fig. 1 is a schematic flowchart of an access method in an embodiment of the present application;
fig. 2 is a block diagram of an APB peripheral device according to an embodiment of the present application;
FIG. 3 is a timing diagram illustrating access to an APB peripheral in an embodiment of the present application;
FIG. 4 is a schematic structural diagram of an access device according to an embodiment of the present application;
fig. 5 is a schematic diagram of a hardware structure of an electronic device in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the present application provides an access method, which is applied to an APB peripheral, and the access method is shown in fig. 1 and includes:
s101, obtaining an access request sent by an APB main module, wherein the access request comprises an access address and a control signal; the access address comprises a virtual address and a real address; the virtual address is used to characterize the bit mode of operation for the address space register specified bit field corresponding to the real address.
In this embodiment, the APB master sends an access request to the APB peripheral through the APB. The APB master may be an APB bridge. The access request includes an access address and a control signal. The access address includes a virtual address and a real address. The APB master may send an access address to the APB peripheral through an address bus in the APB. The virtual address can be set at the upper position of the address bus, and the real address is set at the lower position of the address bus. And, the number of bits occupied by the virtual address can be set as required, for example, one bit, two bits, three bits, etc. For example, virtual addresses are provided on the two upper bits of the address bus and real addresses are provided on the other bits of the address bus. Of course, the virtual address may be set on the lower bits of the address bus, and the real address may be set on the upper bits of the address bus, according to actual requirements.
The APB master may send control signals to the APB peripherals over a control bus in the APB. The control signals mainly include a bus select signal (psel), a bus enable signal (enable), and a bus direction signal (write).
In some embodiments, the bit operation modes include: normal read and write operations, 1 bit set operations, 0 bit set operations, and switch bit operations.
Specifically, the normal read/write operation refers to performing a normal read/write operation on the current address space register. A1-bit operation refers to performing a 1-bit operation on the current address space register specifying bit field. The set 0 bit operation refers to performing a clear 0 bit operation on the current address space register specified bit field. The convert bit operation refers to performing a 1 to 0 or 0 to 1 convert bit operation on the current address space register specified bit field.
In this embodiment, the setting bit operation mode includes normal read/write operation, 1-bit setting operation, 0-bit setting operation, and bit conversion operation, which not only can quickly perform 1-bit setting operation, 0-bit clearing operation, and bit conversion operation on the specified bit field of the current address space register with little logic cost, but also enables the access method to support normal read/write access to the register.
And S102, determining the access type according to the control signal.
In the present embodiment, the access type includes read access and write access. The access type can be determined according to the bus direction signal in the control signal. When the bus direction signal is high, the access type is write access, and when the bus direction signal is low, the access type is read access.
S103, determining a corresponding bit operation mode according to the virtual address.
In this embodiment, the virtual address may be resolved according to a virtual address resolution rule, and a bit operation mode corresponding to the virtual address is determined.
It should be noted that the execution sequence of step S102 and step S103 is not unique, step S102 and step S103 may be executed simultaneously, step S102 may be executed first, or step S103 may be executed first.
And S104, accessing the specified bit domain of the address space register corresponding to the actual address according to the determined access type and the determined bit operation mode.
In this embodiment, after the access type and the bit operation mode are determined, the address space register corresponding to the real address based on the access type and the bit operation mode may be accessed. For example, if the access type is read access, the stored data in the address space register corresponding to the real address can be directly read. If the access type is write access and the bit operation mode is a set 1 bit operation, the set 1 bit operation may be performed on the real address space register specified bit field.
According to the access method provided by the embodiment of the application, the virtual address is added into the access address of the access request of the APB main module, and the virtual address is used for representing the bit operation mode of the address space register designated bit field corresponding to the actual address, so that the bit operation mode of the address space register designated bit field corresponding to the actual address can be determined only by analyzing the virtual address in the access address, further the specific bit operation of the address space register designated bit field corresponding to the actual address is realized, an additional address decoding unit is not required to be configured, and the design cost of an SOC (system on chip) system can be reduced; the bit operation mode of the designated bit domain of the address space register corresponding to the actual address is determined in a virtual address mode, the logic cost is low, and the method can be expanded to the whole APB peripheral register and is not limited to a part of registers; and because the decoding process of an additional address decoding unit is not needed, the access speed of the APB peripheral equipment can be improved, and the rapid access of the APB peripheral equipment register bit operation can be realized.
In an alternative embodiment, step S103, determining the corresponding bit operation mode according to the virtual address includes:
and determining a corresponding bit operation mode according to the virtual address and the mapping relation between the virtual address and the bit operation mode.
In specific implementation, a mapping relationship between a virtual address and a bit operation mode may be preconfigured, for example, if the virtual address is 00, the bit operation mode is a normal read/write operation, which indicates that a normal read/write operation is performed on the current address space register. If the virtual address is 01, the bit mode is a set 1 bit operation, which means that a set 1 bit operation is performed on the specified bit field of the current address space register. The virtual address is 10, the bit operation mode is a set 0 bit operation, indicating that a clear 0 bit operation is performed on the current address space register specified bit field, and the virtual address is 11, the bit operation mode is a convert bit operation, indicating that a convert bit operation is performed on the current address space register specified bit field.
After the virtual address is obtained, the corresponding bit operation mode can be determined according to the mapping relation between the virtual address and the bit operation mode.
In this embodiment, by configuring the mapping relationship between the virtual address and the bit operation mode, the bit operation mode of the address space register specified bit field corresponding to the real address can be obtained in a simpler manner of virtual address mapping.
According to the characteristics of the APB, the total transmission period is two clock cycles. The first clock cycle is a Start (SETUP) state and the second clock cycle is an ENABLE state. The inventor of the application finds that when APB accesses to APB peripherals at present, no matter read access or write access is carried out in the second clock cycle, and the first clock cycle is idle. And aiming at write access, the data to be written in the designated bit area of the address space register corresponding to the actual address is calculated through the calculation resources according to the decoding result of the decoding unit in the second clock period, and the calculation resource requirement is high.
Therefore, the inventor of the present application thinks that if the access type is read access, the storage data in the address space register corresponding to the real address can be directly read in the first clock cycle, so as to complete the read access to the APB peripheral in advance. If the access type is write access, the access request can carry write data, the storage data in the address space register corresponding to the real address is read in the first clock cycle, and then the data to be written in the designated bit domain of the address space register corresponding to the real address is determined based on the write data carried in the access request and the read storage data, so that the demand on computing resources is reduced. The write data carried in the access request may be data determined based on the peripheral data width of the APB, the bit operation mode, and the designated bit field. For example, the data width of the APB peripheral is 32 bits (bit), the bit operation mode is set to 1-bit operation, the bit fields are designated as the 2 nd bit and the 4 th bit, the write data is composed of 32 bits, the values of the 2 nd bit and the 4 th bit are 1, and the values of the other bits are 0.
Therefore, in an alternative embodiment, in step S104, according to the determined access type and the determined bit operation mode, accessing the address space register specified bit field corresponding to the real address includes:
if the access type is read access, performing read access on the specified bit domain of the address space register corresponding to the actual address in the first clock cycle;
and if the access type is write access, determining data to be written in the address space register designated bit domain corresponding to the actual address in a first clock cycle according to the bit operation mode, and writing the data to be written in the address space register designated bit domain corresponding to the actual address in a second clock cycle.
In specific implementation, for write access, determining data to be written to an address space register designated bit domain corresponding to a real address in a first clock cycle according to a bit operation mode includes:
if the bit operation mode is normal read-write operation, determining that the data to be written in the designated bit domain of the address space register corresponding to the actual address is the written data carried in the access request in a first clock cycle;
and if the bit operation mode is 1-bit setting operation, 0-bit setting operation or bit conversion operation, performing read access on the address space register corresponding to the actual address in a first clock cycle to obtain the storage data of each bit domain of the address space register corresponding to the actual address, and determining the data to be written in the specified bit domain of the address space register corresponding to the actual address based on the bit operation mode, the storage data of each bit domain and the write-in data carried in the access request.
In this embodiment, the APB master may send write data to the APB peripheral via the data bus.
In this embodiment, if the bit operation mode is normal read-write operation, the specified bit fields of the address space register corresponding to the real address are all the bit fields of the current address space register, and the data to be written in the specified bit fields of the address space register corresponding to the real address is the write-in data carried in the access request. For example, pwdata _ real [31 ] = pwdata [31 ].
In this embodiment, if the bit operation mode is a set 1 bit operation, a set 0 bit operation, or a converted bit operation, when determining, in the first clock cycle, to-be-written data in a specified bit field of an address space register corresponding to the real address based on the written data carried in the access request, the stored data in each bit field of the address space register corresponding to the real address may be read first, and then the carried written data and the stored data are operated based on the bit operation mode, so as to determine to-be-written data in the specified bit field of the address space register corresponding to the real address.
For example, if the bit operation mode is a set-1 bit operation, the storage data and the write data carried in the access request may be subjected to an or operation, and the data to be written in the address space register specified bit field corresponding to the real address may be determined. As pwdata _ real [31 ] = pwdata [31 ] | prdata _ reg [31 ]; the pwdata _ real [31 ] is data to be written in all bit regions of the address space register corresponding to the real address, the pwdata [31 ] is write data carried in the access request, and the prdata _ reg is data stored in each bit region of the address space register corresponding to the real address.
In one implementation, the data to be written in the specified bit field of the address space register corresponding to the real address can be calculated based on the data to be written in all bit fields of the address space register corresponding to the real address and the stored data in all bit fields of the address space register corresponding to the real address.
In one implementation, data to be written in all bit fields of the address space register corresponding to the real address is determined, that is, data to be written in the specified bit field of the address space register corresponding to the real address is determined.
In this embodiment, the address space register corresponding to the real address is read and accessed in the first clock cycle to obtain the stored data of each bit field of the address space register corresponding to the real address, and then the data to be written in the specified bit field of the address space register corresponding to the real address is determined based on the bit operation mode, the stored data of each bit field, and the written data carried in the access request.
For further explanation of the access method of the present application, the following description will be given taking an APB with a data width of 32 bits and an address space of 64KB as an example.
As shown in fig. 2, the APB peripheral includes an APB protocol parser, a virtual address space parser, a write data controller, and a register table.
The APB protocol analyzer is used for analyzing the control signals from the APB main module and distinguishing the access state. The control signals include psel, enable, and pwrite. The access state includes a system initialization state (IDLE), a SETUP state, and an ENABLE state.
The virtual address space resolver is used to resolve an access address paddr [17 ] from the APB master, the access address including a real address and a virtual address, the real address being paddr [15 ] and the virtual address being paddr [ 17. The virtual address space parser parses the upper virtual address paddr [17 ] in the access address to determine the corresponding bit operation mode write _ access _ mode [1 ]:
00-normal read-write operation, which means normal read-write operation is performed on the current address space register;
01- - - - > 1 bit setting operation, which means that 1 bit setting operation is executed to the specified bit domain of the current address space register;
10-setting a0 bit operation, which represents that the 0 bit clearing operation is executed on the specified bit domain of the current address space register;
11- -translate bit operation, which means that the translate bit operation is performed on the current address space register specified bit field.
During the SETUP state phase, the APB protocol parser parses the pwrite signal to determine the current access type. If the register is a write access (trigger), determining whether a SETUP stage initiates a read access (read _ access _ trigger) to the register according to the result of the virtual address space parser; if the register is accessed by reading, the register is accessed by reading (read _ access) initiated in the SETUP stage, and the register is accessed by reading _ access _ trigger and the read _ access through an OR gate (OR 2).
In the ENABLE phase, the APB protocol parser initiates a write access (write _ access) to the register based on the actual address and control signals parsed by the SETUP phase.
In the ENABLE stage, the APB protocol resolver determines the register access response according to the current load state and the access authority of the APB peripheral.
The write data controller is used for determining the data to be written of the current bit operation according to the bit operation mode analyzed by the virtual address space analyzer:
the bit operation mode is 00- - - - - > data to be written pwdata _ real [31 ] = pwdata [31 ]; wherein, pwdata [ 31;
the bit operation mode is 01- - - - - > data to be written pwdata _ real [31 ] = pwdata [31 ]; here, prdata _ reg [31 ] is stored data read from the register.
The bit operation mode is 10 — data to be written pwdata _ real [31 ] = pwdata [31 ];
the bit operation mode is 11- > data to be written pwdata _ real [31 ] = pwdata [31 ].
The register table is used for selecting a desired address space register according to the paddr [15 ] address signals, and determining to execute read access (rd _ en) or write access (wr _ en) to the current address space register according to the enable signals.
The timing diagram is shown in fig. 3:
pclk is the clock signal. psel, able, and pwrite are control signals. paddr [ 17. pwdata [31 ". prdata _ reg [31 ] is stored data read from the register, and 32' -a 000A represents 32-bit data. pwdata _ real [31 ] is data to be written, and 32' F000F represents data of 32 bits. pready is a handshake signal, and 1' bx represents a switching jump instruction.
At time T0, the APB peripheral is in an IDLE state.
At time T1, the APB peripheral receives an access request from the APB master, and enters a SETUP state. A pwrite of 1 indicates that a write access is initiated at this time, and in the SETUP state, the upper virtual address paddr [ 17.
And (3) at the moment T2, enabling the APB peripheral equipment to enter an ENABLE state, calculating data to be written by combining the read storage data in the SETUP state and the resolved bit operation mode, and initiating write access to an address space to be written.
And at the time of T3, completing the APB peripheral write access and returning to the IDLE state.
In an optional embodiment, the access method further comprises:
determining the current value of a register based on the storage data of each bit field of an address space register corresponding to the actual address;
determining an expected value of a register based on the write-in data carried in the access request;
based on the current value and the desired value, a difference in the values of the registers before and after the 1-bit-set operation, the 0-bit-set operation, or the shift bit operation is determined.
In this embodiment, the expected value may be loaded into the write data in the access request.
In this embodiment, a direct comparison of the current and expected values of the registers may be achieved by performing a read access to the address space register corresponding to the real address in the first clock cycle.
In an optional embodiment, the access method further comprises:
and storing the storage data of each bit field of the address space register corresponding to the actual address so as to restore the data of the address space register corresponding to the actual address.
In this embodiment, for some functional registers that may be automatically deactivated by hardware, by performing read access to an address space register corresponding to a real address in a first clock cycle and storing read storage data, data before write access may be photographed while performing write access to a specified bit field, so that data restoration may be performed on the address space register corresponding to the real address when necessary.
An embodiment of the present application provides an access apparatus, which is applied to an APB peripheral, and as shown in fig. 4, the access apparatus includes:
an obtaining module 41, configured to obtain an access request sent by an APB master module, where the access request includes an access address and a control signal; the access address comprises a virtual address and a real address; the virtual address is used for representing a bit operation mode of an address space register appointed bit domain corresponding to the real address;
a first determining module 42, configured to determine an access type according to the control signal;
a second determining module 43, configured to determine a corresponding bit operation mode according to the virtual address;
and the access module 44 is configured to access the address space register specified bit domain corresponding to the real address according to the determined access type and the determined bit operation mode.
According to the access device provided by the embodiment of the application, the virtual address is added into the access address of the access request of the APB main module, and the virtual address is used for representing the bit operation mode of the address space register designated bit field corresponding to the actual address, so that the bit operation mode of the address space register designated bit field corresponding to the actual address can be determined only by analyzing the virtual address in the access address, further the specific bit operation of the address space register designated bit field corresponding to the actual address is realized, an additional address decoding unit is not required to be configured, and the design cost of an SOC (system on chip) system can be reduced; the bit operation mode of the designated bit domain of the address space register corresponding to the actual address is determined in a virtual address mode, the logic cost is low, and the method can be expanded to the whole APB peripheral register and is not limited to a part of registers; and because the decoding process of an additional address decoding unit is not needed, the access speed of the APB peripheral equipment can be improved, and the rapid access of the APB peripheral equipment register bit operation can be realized.
In an alternative embodiment, the bit operation modes include: normal read and write operations, 1 bit setting operations, 0 bit setting operations, and bit conversion operations.
In an optional embodiment, the second determining module is configured to determine the corresponding bit operation mode according to the virtual address and a mapping relationship between the virtual address and the bit operation mode.
In an optional embodiment, the access module is configured to perform, in a first clock cycle, a read access to a specified bit field of an address space register corresponding to the actual address if the access type is the read access; and if the access type is write access, determining data to be written in the address space register designated bit domain corresponding to the actual address in a first clock cycle according to the bit operation mode, and writing the data to be written in the address space register designated bit domain corresponding to the actual address in a second clock cycle.
In an optional embodiment, the access module is configured to determine, in a first clock cycle, to-be-written data in an address space register specified bit domain corresponding to the actual address as write data carried in the access request if the bit operation mode is a normal read-write operation; and if the bit operation mode is 1-bit setting operation, 0-bit setting operation or bit conversion operation, performing read access on the address space register corresponding to the actual address in a first clock cycle to obtain the storage data of each bit field of the address space register corresponding to the actual address, and determining the data to be written in the specified bit field of the address space register corresponding to the actual address based on the bit operation mode, the storage data of each bit field and the write-in data carried in the access request.
In an optional embodiment, the access device further comprises:
the third determining module is used for determining the current value of the register based on the storage data of each bit field of the address space register corresponding to the actual address; determining the expected value of the register based on the write-in data carried in the access request; based on the current value and the desired value, a difference in the values of the registers before and after the 1-bit-set operation, the 0-bit-set operation, or the shift bit operation is determined.
In an optional embodiment, the access device further comprises:
and the storage module is used for storing the storage data of each bit field of the address space register corresponding to the actual address so as to restore the data of the address space register corresponding to the actual address.
According to an embodiment of the present application, an electronic device and a readable storage medium are also provided.
FIG. 5 illustrates a schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.
As shown in fig. 5, the apparatus 500 comprises a computing unit 501 which may perform various appropriate actions and processes in accordance with a computer program stored in a Read Only Memory (ROM) 502 or a computer program loaded from a storage unit 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The calculation unit 501, the ROM 502, and the RAM 503 are connected to each other by a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.
A number of components in the device 500 are connected to the I/O interface 505, including: an input unit 506 such as a keyboard, a mouse, or the like; an output unit 507 such as various types of displays, speakers, and the like; a storage unit 508, such as a magnetic disk, optical disk, or the like; and a communication unit 509 such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The computing unit 501 may be a variety of general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The computing unit 501 executes the respective methods and processes described above, such as the access method. For example, in some embodiments, the access method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 500 via ROM 502 and/or communications unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the access method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the access method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server combining a blockchain.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present application may be executed in parallel, sequentially, or in different orders, and the present invention is not limited thereto as long as the desired results of the technical solutions disclosed in the present application can be achieved.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An access method applied to an APB peripheral, the method comprising:
obtaining an access request sent by an APB main module, wherein the access request comprises an access address and a control signal; the access address comprises a virtual address and a real address; the virtual address is used for representing a bit operation mode of an address space register designated bit field corresponding to the actual address;
determining an access type according to the control signal;
determining a corresponding bit operation mode according to the virtual address;
and accessing the specified bit domain of the address space register corresponding to the actual address according to the determined access type and the determined bit operation mode.
2. The access method according to claim 1, wherein the bit operation mode comprises:
normal read and write operations, 1 bit set operations, 0 bit set operations, and switch bit operations.
3. The method of claim 1, wherein said determining a corresponding bit operation mode based on said virtual address comprises:
and determining a corresponding bit operation mode according to the virtual address and the mapping relation between the virtual address and the bit operation mode.
4. The method according to claim 1, wherein said accessing an address space register specified bit field corresponding to a real address according to the determined access type and the determined bit operation mode comprises:
if the access type is read access, performing read access on an address space register designated bit domain corresponding to the actual address in a first clock cycle;
and if the access type is write access, determining data to be written in an address space register appointed bit domain corresponding to the actual address in a first clock cycle according to the bit operation mode, and writing the data to be written in the address space register appointed bit domain corresponding to the actual address in a second clock cycle.
5. The method according to claim 4, wherein said determining data to be written to the address space register specified bit field corresponding to the real address in the first clock cycle according to the bit operation mode comprises:
if the bit operation mode is normal read-write operation, determining that the data to be written in the designated bit domain of the address space register corresponding to the actual address is the written data carried in the access request in a first clock cycle;
and if the bit operation mode is 1-bit setting operation, 0-bit setting operation or bit conversion operation, performing read access on the address space register corresponding to the actual address in a first clock cycle to obtain the storage data of each bit field of the address space register corresponding to the actual address, and determining the data to be written in the specified bit field of the address space register corresponding to the actual address based on the bit operation mode, the storage data of each bit field and the write-in data carried in the access request.
6. The access method according to claim 5, further comprising:
determining the current value of a register based on the storage data of each bit field of an address space register corresponding to the actual address;
determining the expected value of the register based on the write-in data carried in the access request;
based on the current value and the expected value, a difference in values of registers before and after a 1-bit-set operation, a 0-bit-set operation, or a toggle bit operation is determined.
7. The access method according to claim 5, further comprising:
and storing the storage data of each bit field of the address space register corresponding to the real address so as to restore the data of the address space register corresponding to the real address.
8. An access device for use with an APB peripheral, the device comprising:
the APB master module is used for sending an access request to the APB master module; the access address comprises a virtual address and a real address; the virtual address is used for representing a bit operation mode of an address space register designated bit field corresponding to the actual address;
the first determining module is used for determining the access type according to the control signal;
a second determining module, configured to determine a corresponding bit operation mode according to the virtual address;
and the access module is used for accessing the specified bit domain of the address space register corresponding to the actual address according to the determined access type and the determined bit operation mode.
9. An electronic device, comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the access method of any one of claims 1-7.
10. A computer-readable storage medium storing computer instructions for causing a computer to perform the access method of any one of claims 1 to 7.
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