CN115857819A

CN115857819A - Data storage method, data reading method and device

Info

Publication number: CN115857819A
Application number: CN202211623776.XA
Authority: CN
Inventors: 胡广江
Original assignee: SHENZHEN HEGUANG MEASUREMENT CONTROL TECHNOLOGY CO LTD
Current assignee: SHENZHEN HEGUANG MEASUREMENT CONTROL TECHNOLOGY CO LTD
Priority date: 2022-12-16
Filing date: 2022-12-16
Publication date: 2023-03-28

Abstract

The data storage method reads data in a flash memory chip into a cache region of an intelligent chip by using a minimum addressing unit, namely a plurality of bytes as a unit. And in a cache region of the intelligent chip, replacing the data with the corresponding length from the initial address by the target data. And writing the replaced data in the cache region of the intelligent chip into the flash memory chip by taking a plurality of bytes as a unit. Therefore, the target data can be stored in the flash memory chip by taking one byte as a unit, and the storage space in the flash memory chip is fully utilized. The data reading method is characterized in that data in the flash memory chip is read into a cache region of the intelligent chip by taking a plurality of bytes as units. In the cache area of the intelligent chip, data with the target length from the initial address is directly read into the storage chip. Therefore, the occupation of the data of the redundant bytes on the storage space of the storage chip can be reduced.

Description

Data storage method, data reading method and device

Technical Field

The present application belongs to the technical field of data storage, and in particular, to a data storage method, a data reading method, and a data reading device.

Background

Along with the requirement of the single chip microcomputer for data storage is higher and higher, more and more single chip microcomputers use flash memory (flash memory) chips to store data, and therefore the data cannot be lost when the single chip microcomputers are powered off.

At present, the data read-write process of a flash memory chip includes: the singlechip acquires the initial address of the data and the length (namely the number of occupied bytes) of the data. When the initial address of the data is a multiple of four, the singlechip judges whether the length of the data is less than or equal to the maximum storage length of the flash memory chip. If so, the singlechip reads data from the flash memory chip, or the singlechip writes the data into the flash memory chip for storage.

However, since the minimum addressing unit of the flash memory chip is four bytes, when the length of the data is less than four bytes, the single chip still needs to occupy four bytes in the flash memory chip when writing the data into the flash memory chip for storage, which causes idle bytes in the flash memory chip and wastes the storage space of the flash memory chip. When the single chip microcomputer reads the data with less than four bytes from the flash memory chip, the data with four bytes still needs to be read, and the read data with four bytes contains the data with other unnecessary bytes, so that the storage space of the single chip microcomputer is wasted.

Disclosure of Invention

The embodiment of the application provides a data storage method, a data reading method and a data reading device, which can solve the problem of waste of storage space of a flash memory chip.

In a first aspect, an embodiment of the present application provides a data storage method, where the data storage method includes:

step 101, acquiring target data and an initial address, wherein the initial address is used for indicating an initial position of the target data stored in a flash memory chip;

step 102, determining a first address of the flash memory chip according to the starting address, wherein the first address is less than or equal to the starting address and is a multiple of the minimum addressing unit of the flash memory chip, or the first address is address 0;

103, reading first data which starts from a first address and has the length of the minimum addressing unit of the flash memory chip in the flash memory chip into a cache region of the intelligent chip;

104, in the first data, replacing the data which starts from the starting address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip with the second data which starts from the starting address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the target data to obtain the replaced first data;

and 105, writing the replaced first data in the cache region of the intelligent chip into the flash memory chip, updating the initial address to be an address adjacent to the tail address of the second data stored in the flash memory chip, and continuing to execute the steps 102 to 105 until all target data are stored in the flash memory chip.

In one possible implementation, the data storage method includes:

when the initial address is not a multiple of the minimum addressing unit of the flash memory chip, the first address is smaller than the initial address and is a multiple of the minimum addressing unit of the flash memory chip, or the first address is address 0;

when the start address is a multiple of the minimum addressing unit of the flash memory chip, the first address is equal to the start address and is a multiple of the minimum addressing unit of the flash memory chip, or the first address is address 0.

In a possible implementation manner, before determining the first address of the flash memory chip according to the start address, the data storage method further includes:

and when the length of the target data is larger than the maximum storage length of the flash memory chip, prompting that the target data cannot be stored in the flash memory chip.

According to the embodiment of the application, the data in the flash memory chip is read into the cache region of the intelligent chip through the intelligent chip, the data corresponding to the data section is replaced by the target data in the cache region of the intelligent chip, and the replaced data is written into the flash memory chip for storage, so that the technical problem that the data cannot be written into the flash memory chip for storage in a byte unit is solved, and the technical effect of completely utilizing the storage space of the flash memory chip is achieved.

In a second aspect, an embodiment of the present application provides a data reading method, where the data reading method includes:

step 201, obtaining a target length and an initial address, wherein the target length is the number of bytes of data needing to be read from the flash memory chip, and the initial address is used for indicating an initial position of the data with the target length read from the flash memory chip;

step 202, determining a first address of the flash memory chip according to the starting address, wherein the first address is less than or equal to the starting address and is a multiple of a minimum addressing unit of the flash memory chip, or the first address is address 0;

step 203, reading first data which starts from a first address and has the length of the minimum addressing unit of the flash memory chip in the flash memory chip into a cache region of the intelligent chip;

step 204, in the first data, reading second data which starts from the initial address and has a length less than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip into the memory chip;

step 205, updating the starting address to an address adjacent to the last address of the second data stored in the flash memory chip, and continuing to execute the steps 202 to 205 until the length of the data in the memory chip is the target length

In one possible implementation manner, the data reading method includes:

In a possible implementation manner, before determining the first address of the flash memory chip according to the start address, the data reading method further includes:

when the target length is larger than the maximum reading length of the flash memory chip, the situation that the target data cannot be read from the flash memory chip is prompted.

In a third aspect, embodiments of the present application provide a data storage device, where the data storage device is configured to perform the method in the first aspect or any possible implementation manner of the first aspect. In particular, the data storage device may comprise means for performing the method of the first aspect described above or any possible implementation manner of the first aspect.

In a fourth aspect, embodiments of the present application provide a data reading apparatus, where the data reading apparatus is configured to perform the method in the second aspect or any possible implementation manner of the second aspect. In particular, the data reading apparatus may comprise means for performing the method of the second aspect or any possible implementation manner of the second aspect.

In a fifth aspect, an embodiment of the present application provides a processor, which includes a memory, a controller, and a computer program stored in the memory and executable on the controller, and the controller implements the first aspect or any possible implementation manner of the first aspect and the method in any possible implementation manner of the second aspect or the second aspect when executing the computer program.

A sixth aspect provides a computer-readable storage medium having stored therein a computer-executable program or instructions which, when run on a computer, cause the computer to perform the method of the first aspect or any of the possible implementations of the first aspect and of the second aspect or any of the possible implementations of the second aspect.

It is understood that the beneficial effects of the second to sixth aspects can be seen from the description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a block diagram schematically illustrating a structure of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a data storage method according to an embodiment of the present application;

FIG. 3 is a schematic block diagram illustrating a data storage method according to an embodiment of the present disclosure;

FIG. 4 is a schematic flow chart illustrating a data storage method according to an embodiment of the present application;

fig. 5 is a schematic flowchart of a data reading method according to an embodiment of the present application;

FIG. 6 is a schematic block diagram illustrating a data reading method according to an embodiment of the present disclosure;

fig. 7 is a schematic flowchart of a data reading method according to an embodiment of the present application;

FIG. 8 is a block diagram schematically illustrating a data storage device according to an embodiment of the present application;

fig. 9 is a block diagram schematically illustrating a structure of a data reading apparatus according to an embodiment of the present application;

description of reference numerals:

100-an electronic device; 101-a smart chip; 102-a flash memory chip; 103-memory chip.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

Referring to fig. 1, fig. 1 is a schematic block diagram illustrating a structure of an electronic device according to an embodiment of the present disclosure. As shown in fig. 1, the electronic device 100 of the embodiment of the present application may include: a smart chip 101 and a plurality of chips for storage electrically connected to the smart chip 101. A cache area is provided in the smart chip 101.

For example, the electronic device 100 may include: digital cameras, recording pens, game consoles, mobile phones, digital televisions, or the like, which are capable of automatically storing data.

The smart chip 101 is used for implementing control management of a plurality of chips for storage through programming. In other words, the smart chip 101 may transmit the control signal to the plurality of chips for storage, so that the smart chip 101 may control the plurality of chips for storage to perform an operation corresponding to the control signal. Therefore, the smart chip 101 can satisfy different data storage requirements of the electronic device 100 by controlling and managing a plurality of chips for storage. For example, data storage requirements may include: temporary storage, permanent storage, or fast storage, etc.

For example, the control signals may include: a data read signal, a data write signal, or a data erase signal, etc.

Specifically, the smart chip 101 may transmit a data read signal to the plurality of chips for storage, so that the smart chip 101 may read data corresponding to the control signal from the plurality of chips for storage. Alternatively, the smart chip 101 may transmit a data write signal to a plurality of chips for storage, so that the smart chip 101 may write data corresponding to the control signal into the plurality of chips for storage. Still alternatively, the smart chip 101 may transmit a data erase signal to the plurality of chips for storage, so that the smart chip 101 may erase data corresponding to the control signal from the plurality of chips for storage.

Wherein, the intelligent chip 101 can be a single chip microcomputer. For example, the single chip microcomputer may include: STM32 single-chip microcomputer, MSP430 ultra-low power consumption single-chip microcomputer or MC1S-51 series single-chip microcomputer.

Considering that the buffer of the smart chip 101 can only temporarily store data, the data stored in the buffer of the smart chip 101 will disappear after the electronic device 100 is powered off. Therefore, the electronic device 100 can read data from the buffer of the smart chip 101 to a plurality of chips for storage, so that the data does not disappear after the electronic device 100 is powered off.

It is considered that the electronic apparatus 100 directly performs modification operations such as replacement, overwriting and the like on data stored in the plurality of chips for storage, which is slow and may cause loss of data stored in the plurality of chips for storage. Therefore, the electronic device 100 can read and store the data stored in the plurality of chips for storage into the cache area of the smart chip 101, so that the smart chip 101 can perform modification operations such as quick replacement and coverage on the data stored in the cache area of the smart chip 101.

In addition, the cache area of the smart chip 101 according to the embodiment of the present application is also divided into storage areas in units of bytes. The minimum addressing unit of the cache of the smart chip 101 is one byte.

The plurality of chips for storing are used for responding to the control signal of the smart chip 101 and implementing various functions such as reading, writing, replacing or erasing corresponding to the control signal.

As shown in fig. 1, the plurality of chips for storage may include: flash memory chip 102 and memory chip 103, etc.

Both the flash memory chip 102 and the memory chip 103 are electrically connected to the smart chip 101.

The flash memory chip 102 is a non-volatile memory. The flash memory chip 102 can realize fast storage of data, and the data stored in the flash memory chip 102 does not disappear after the electronic device 100 is powered off.

In addition, in the flash memory chip 102 according to the embodiment of the present application, the storage area of the flash memory chip 102 is divided by using a plurality of bytes as an addressing unit. The plurality of bytes may include: the first byte, the second byte, the third byte, \ 8230and the Nth byte, wherein N is a positive integer greater than or equal to 1. The address corresponding to the first byte is address 0, the address corresponding to the second byte is address 1, the address corresponding to the third byte is address 2, \\ 8230, and the address corresponding to the Nth byte is address N-1.

It should be understood that each byte of the plurality of bytes may store 8 bits of data. The 8-bit data stored in each byte may be the same data or different data.

It can be seen that the total number N of bytes in the flash memory chip 102 can be used to represent the maximum storage length of the flash memory chip 102, and can also be used to represent the maximum read length of the flash memory chip 102.

For example, the memory area of the flash memory chip 102 may be divided by four bytes as the minimum addressing unit in the flash memory chip 102. Based on this, when the smart chip 101 writes data into the flash memory chip 102, it is necessary to write data in units of four bytes. Alternatively, when the smart chip 101 reads data from the flash memory chip 102, the data needs to be read in units of four bytes.

Considering that the maximum storage length of the flash memory chip 102 is limited, the electronic device 100 may be further provided with other memory chips 103 for storing data.

The memory chip 103 is used to ensure that the electronic device 100 has a sufficient memory space.

For example, the memory chip 103 is a charged erasable programmable read only memory (E1 lE1C1tri C1A1lly E1rA1sA1B1lE1progrA1mmA1B1lE1 rE1A1D1 only mE1 memory, E1 PROM).

Based on the above description, the following describes in detail a specific implementation process performed by the smart chip 101 to write data into the flash memory chip 102, with reference to fig. 2 to 4.

Referring to fig. 2, fig. 2 is a schematic flowchart illustrating a data storage method according to an embodiment of the present disclosure. As shown in fig. 2, a data storage method according to an embodiment of the present application includes:

step 101, acquiring target data and a start address.

Wherein the target data is data to be stored in the flash memory chip 102.

The target data may include one or more data, and the target data may further include null data. For example, the target data may include: data such as photos, text, documents, audio, video, etc.

Since the flash memory chip 102 divides the storage area by taking a plurality of bytes as an addressing unit, correspondingly, the target data can also be divided into a plurality of bytes of data by taking a byte as a unit in advance.

The start address is used to indicate the start position of the target data stored in the flash memory chip 102. The starting address may be a multiple of the smallest addressing unit in the flash chip 102 that is not the flash chip 102. For example, in the case where the minimum addressing unit of the flash memory chip 102 is four bytes, the start address may be address 2.

In some embodiments, the smart chip 101 may obtain target data and a start address stored in other devices.

The other devices are devices having a storage function and connected to the smart chip 101 in a communication manner.

In another embodiment, the smart chip 101 may receive target data and a start address input by a user, thereby acquiring the target data and the start address.

In addition, the smart chip 101 may obtain a target address. The target address is used to indicate a location where any one of the target data is stored in the flash memory chip 102.

Thus, the smart chip 101 may determine the start address based on the target address.

Specifically, the smart chip 101 may determine a start address of first data in the target data according to the target address and a length of data between any one of the target data and the first data. Thereby, the smart chip 101 is caused to obtain the start address.

Considering that the start address may not be a multiple of the minimum addressing unit of the flash memory chip 102, the smart chip 101 needs to determine an address that is a multiple of the minimum addressing unit of the flash memory chip 102 according to the start address.

Step 102, determining a first address of the flash memory chip according to the starting address.

The first address is less than or equal to the start address and is a multiple of the minimum addressing unit of the flash memory chip 102, or the first address is address 0. Address 0 is the address corresponding to the first byte in the flash chip 102.

When the start address is a multiple of the minimum addressing unit of the flash memory chip 102, the smart chip 101 may directly determine the start address as the first address of the flash memory chip 102.

Alternatively, when the start address is address 0, the smart chip 101 may directly determine address 0 as the first address of the flash memory chip 102.

It is contemplated that the smart chip 101 may perform a process of determining the first address of the flash memory chip 102 based on the start address a plurality of times.

For the case that the intelligent chip 101 determines the first address for the first time, when the starting address is smaller than the minimum addressing unit of the flash memory chip 102, the intelligent chip 101 may determine, according to the starting address, that the first address smaller than the starting address in the flash memory chip 102 is address 0.

For example, when the starting address is address 2 and the minimum addressing unit of the flash chip 102 is four bytes, the smart chip 101 may determine that the first address smaller than address 2 is address 0.

When the start address is greater than the minimum addressing unit of the flash chip 102 and is not a multiple of the minimum addressing unit of the flash chip 102, the smart chip 101 may determine, according to the start address, a first address in the flash chip 102 that is smaller than the start address and is a multiple of the minimum addressing unit of the flash chip 102.

The first address determined by the smart chip 101 to be smaller than the start address and to be a multiple of the minimum addressing unit of the flash chip 102 may include one or more addresses. At this time, the smart chip 101 may select the first address closest to the start address, so that the data written into the flash memory chip 102 by the smart chip 101 for the first time includes the target data, thereby improving the storage efficiency of the target data.

For example, the starting address is address 9, the minimum addressing unit of the flash chip 102 is four bytes, and the smart chip 101 may determine that addresses that are smaller than address 9 and that are multiples of 4 are address 8 and address 4.

If the smart chip 101 writes data into the flash chip 102 starting from address 4, the first written data is stored in the flash chip 102 in 4 bytes corresponding to addresses 4 to 8. Since the start address of the target data is address 9, the data written for the first time does not include the target data. It can be seen that, taking address 4 as the first address, one time of invalid storage is required. Based on this, the smart chip 101 determines the address 8 closest to the address 9 as the first address.

Specifically, the intelligent chip 101 may perform a remainder operation on the numerical value of the start address and a multiple of the minimum addressing unit of the flash memory chip 102 to obtain the address threshold. The intelligent chip 101 may subtract the value of the start address from the address threshold to obtain the value of the first address. The smart chip 101 may determine the first address according to a value of the first address.

For example, the starting address is address 5, and the minimum addressing unit of the flash memory chip 102 is four bytes. The intelligent chip 101 performs a remainder operation on the numerical values 5 and 4 of the address 5 to obtain an address threshold value of 1. The intelligent chip 101 subtracts the value 5 from the value 1 to obtain the value of the first address as 4, so the first address is the address 4.

For the case where the smart chip 101 determines the first address each time after the first time, the start address is a multiple of the minimum addressing unit of the flash memory chip 102. At this time, the smart chip 101 may directly determine the start address as the first address of the flash memory chip 102.

Step 103, reading the first data which starts from the first address and has the length of the minimum addressing unit of the flash memory chip into the cache region of the intelligent chip.

The first data is data already stored in the flash memory chip 102. Null data may exist in the first data.

The smart chip 101 may send a data read signal to the flash memory chip 102. After the flash chip 102 receives the data read signal, the smart chip 101 may read the first data having a length of the minimum addressing unit of the flash chip 102, starting from the first address of the flash chip 102.

Thus, the smart chip 101 may write the first data in the flash chip 102, which starts from the first address and has a length of the minimum addressing unit of the flash chip 102, into the buffer of the smart chip 101.

And 104, in the first data, replacing the data which starts from the starting address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip with the second data which starts from the starting address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the target data to obtain the replaced first data.

Wherein the length of the second data is less than or equal to the length of the target data.

The smart chip 101 may obtain second data of the target data, which starts from the start address and has a length less than or equal to the minimum addressing unit of the flash memory chip 102. The smart chip 101 may replace, in the first data, data starting from the start address and having a length less than or equal to the minimum addressing unit of the flash memory chip 102 in the cache region of the smart chip 103 with second data starting from the start address and having a length less than or equal to the minimum addressing unit of the flash memory chip 102 in the target data.

Thus, the smart chip 101 may obtain the replaced first data in the cache of the smart chip 101.

Wherein the end address is a location where the last byte of data in the second data is stored in the flash memory chip 102.

The smart chip 101 may read the replaced first data in the buffer of the smart chip 103.

Based on this, the smart chip 101 may transmit a data write signal to the flash memory chip 102. After the flash chip 102 receives the data write signal, the smart chip 101 may write the replaced first data in the buffer of the smart chip 101 into the flash chip 102 for storage.

Thus, the smart chip 101 may determine that the replaced first data in the cache area of the smart chip 101 is stored in the flash memory chip 102. Since the replaced first data in the cache area of the smart chip 101 includes the second data in the target data, based on the above description, the smart chip 101 can store the second data in the target data in the flash memory chip 102 by using one byte as an addressing unit.

It is contemplated that the second data may include all of the target data. Alternatively, the second data may include only partial data of the target data. Therefore, after storing the second data of the target data into the flash memory chip 102, the smart chip 101 may determine whether the target data is all stored into the flash memory chip 102.

In some embodiments, the smart chip 101 may determine whether the target data is stored in the flash memory chip 102 according to the length of the target data and the length of the second data.

Based on this, the smart chip 101 may determine that the target data has been entirely stored in the flash memory chip 102 when it is determined that the length of the second data is equal to the length of the target data.

The smart chip 101 may determine that the target data is not all stored in the flash memory chip 102 when it is determined that the length of the second data is less than the length of the target data. At this time, the smart chip 101 may update the start address to an address adjacent to the end address where the second data is stored in the flash memory chip 102. Thus, the smart chip 101 may continue to perform steps 102-105, storing the remaining data adjacent to and after the second data in the target data until the target data is all stored in the flash memory chip 102.

In summary, the smart chip 101 can store all the target data into the flash memory chip 102 in one byte as an addressing unit.

According to the data storage method, the target data and the starting address are obtained. Based on the starting address, a first address of the flash memory chip may be determined. The first data which starts from the first address and has the length of the minimum addressing unit of the flash memory chip can be read into the cache region of the intelligent chip, so that the first data which is stored in the flash memory chip in the minimum addressing unit, namely a plurality of bytes, can be translated into the cache region of the intelligent chip to be stored in the unit of one byte.

Therefore, in the first data, the data which is started from the starting address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip can be replaced by the second data which is started from the starting address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the target data, the replaced first data is obtained, and the second data in the target data can be stored in the cache region of the intelligent chip in a byte unit.

Then, the replaced first data in the cache region of the intelligent chip can be written into the flash memory chip, the replaced first data stored by the minimum addressing unit, namely a plurality of bytes, can be written into the flash memory chip, so that the second data in the replaced first data is still written into the flash memory chip by taking one byte as a unit, and the storage of the second data starting from any starting address which is not a multiple of the minimum addressing unit of the flash memory chip can be realized. When the second data is not all the target data, the start address can be updated to be an address adjacent to the end address of the second data stored in the flash memory chip, and the target data is continuously stored until all the target data are stored in the flash memory chip, so that the target data of a plurality of bytes which are not the minimum addressing unit of the flash memory chip can be stored.

Therefore, when the initial address does not accord with the storage rule of the flash memory chip, namely the initial address is not the multiple of the minimum addressing unit of the flash memory chip or the address 0, the data can be written into the flash memory chip by taking one byte as the unit for storage, thereby avoiding the occurrence of idle bytes in the flash memory chip and realizing the complete utilization of the storage space of the flash memory chip.

Based on the above description, the smart chip 101 may need to perform one or more storage operations to store all the target data in the flash memory chip 102.

For the case where the smart chip 101 stores the target data into the flash memory chip 102 only once, the start address is not a multiple of the minimum addressing unit of the flash memory chip 102.

When the start address is not a multiple of the minimum addressing unit of the flash memory chip 102, the first address is smaller than the start address and is a multiple of the minimum addressing unit of the flash memory chip 102, or the first address is address 0.

For the case that the target data can be completely stored in the flash memory chip 102 only by the smart chip 101 performing multiple times of storage, when the smart chip 101 performs the first storage in the multiple times of storage, the start address is not a multiple of the minimum addressing unit of the flash memory chip 102. The smart chip 101 may determine the first address as a start address at each time of storage after the first storage, the start address being a multiple of a minimum addressing unit of the flash memory chip 102.

When the start address is a multiple of the minimum addressing unit of the flash memory chip 102, the first address is equal to the start address and is a multiple of the minimum addressing unit of the flash memory chip 102, or the first address is address 0.

Based on the above description, the smart chip 101 needs to determine whether the flash memory chip 102 can store the target data before executing step 102.

In some embodiments, the smart chip 101 may determine whether the target data can be stored in the flash memory chip 102 according to the length of the target data and the maximum storage length of the flash memory chip 102.

When the intelligent chip 101 determines that the length of the target data is greater than the maximum storage length of the flash memory chip 102, it indicates that the target data cannot be stored in the flash memory chip 102.

When the intelligent chip 101 determines that the length of the target data is smaller than the maximum storage length of the flash memory chip 102, steps 101 to 105 may be executed to store the target data in the flash memory chip 102.

Based on the descriptions of fig. 1 and fig. 2, a specific implementation process of a data storage method provided by the embodiment of the present application is illustrated in the following with reference to fig. 3 and fig. 4.

As shown in fig. 3, the target data includes data A1, data A2, data A3, data A4, and data A5. The starting address of the target data is address 2, i.e. the location where the data A1 needs to be written into the flash memory chip 102 is address 2.

As shown in fig. 3, the flash memory chip 102 includes data B1, data B2, \8230;, and data Bn. Each of the n data occupies a byte of storage space in the flash memory chip 102, i.e., the units of data B1, data B2, \ 8230, data Bn, etc. are bytes.

The minimum addressing unit of the flash memory chip 102 is four bytes. The maximum storage length N of the flash memory chip 102 and the address corresponding to each byte in the flash memory chip 102 may refer to the above description of the flash memory chip 102, which is not repeated herein.

For the convenience of explaining the data storage process, the buffer areas of the flash memory chip 102 and the smart chip 101 in fig. 3 are present twice.

Referring to fig. 4, fig. 4 is a schematic flowchart illustrating a data storage method according to an embodiment of the present disclosure. As shown in fig. 4, a data storage method according to an embodiment of the present application includes:

step 11, the target data and address 2 as shown in fig. 3 are obtained.

Step 12, judging whether the target data exceeds the maximum storage length of the flash memory chip 102.

If yes, go to step 13. If not, executing step 14-step 20.

And step 13, prompting that the target data cannot be stored in the flash memory chip 102.

Step 14, according to the address 2, determining that the first address in the flash memory chip 102 is the address 0, that is, determining the first address closest to the address 2 in the flash memory chip 102.

Step 15, reading the first data which is in the flash memory chip 102, starts from the address 0 and has the length of four bytes, into the cache area of the intelligent chip 101. As shown in fig. 3, the data B1 to B4 in the flash memory chip 102 are read into the buffer area of the smart chip 101.

And step 16, in the first data, replacing the data which starts from the address 2 and has the length of two bytes in the cache area of the intelligent chip 101 with the second data which starts from the address 2 and has the length of two bytes in the target data to obtain the replaced first data in the cache area of the intelligent chip 101. As shown in fig. 3, data A1 and data A2 are replaced with data B3 and data B4 in the buffer of the smart chip 101, respectively.

And step 17, writing the replaced first data in the cache region of the intelligent chip 101 into the flash memory chip 102. As shown in fig. 3, the data B1, the data B2, the data A1 and the data A2 in the buffer area of the smart chip 101 are correspondingly written into the flash memory chip 102.

At this time, the smart chip 101 writes only data a and data B of the target data into the flash memory chip 102 for storage. Data C, data D, and data E in the target data have not been written into the flash memory chip 102. Therefore, the smart chip 101 can execute steps 18-21, and continue to write the data C, the data D, and the data E in the target data into the flash memory chip 102 for storage.

And step 18, updating the initial address to be the address 4.

Step 19, reading the first data with the length of four bytes in the flash memory chip 102 from the address 4 into the cache area of the intelligent chip 101. As shown in fig. 3, data B5 to B8 in the flash memory chip 102 are read into the buffer of the smart chip 101.

And 20, replacing the data with the length of three bytes starting from the address 4 in the cache region of the intelligent chip 101 with the second data with the length of three bytes starting from the address 4 in the target data to obtain the replaced first data in the cache region of the intelligent chip 101. As shown in fig. 3, data B5, data B6, and data B7 in the buffer of the smart chip 101 are replaced with data A3, data A4, and data A5 in the target data, respectively.

Step 21, writing the replaced first data in the cache area of the intelligent chip 101 into the flash memory chip 102. As shown in fig. 3, the data A4, the data A5, and the data B8 in the buffer area of the smart chip 101 are correspondingly written into the flash memory chip 102.

Thus, the smart chip 101 can write all the data of the target data into the flash memory chip 102 for storage.

It can be seen that the smart chip 101 can successfully write the target data of the start address which is not a multiple of 4, i.e. address 2, into the flash memory chip 102 for storage. Moreover, the smart chip 101 only occupies the five bytes of the third byte to the seventh byte in the flash memory chip 102, but does not occupy the eight bytes of the memory space in the flash memory chip 102 when storing the target data in the flash memory chip 102.

In summary, the data storage method of the present application stores data in the cache region of the smart chip 101 by taking one byte as a unit. And then, the data in the cache area of the intelligent chip 101 is packaged into data which is written into the flash memory chip 102 by taking four bytes as a unit for storage. Therefore, when the intelligent chip 101 writes the data into the flash memory chip 102 for storage, the storage rule of the flash memory chip 102 for storing the data in units of four bytes does not need to be satisfied, and the storage rule that the initial address of the data stored in the flash memory chip 102 needs to be a multiple of 4 or is an address 0 does not need to be satisfied, so that idle bytes in the flash memory chip 102 are avoided, and the utilization rate of the storage space in the flash memory chip 102 is improved.

Based on the above description, the following describes in detail a specific implementation process of the smart chip 101 for reading data from the flash memory chip 102, with reference to fig. 5-7.

Referring to fig. 5, fig. 5 is a flowchart illustrating a data reading method according to an embodiment of the present disclosure. As shown in fig. 5, the data reading method according to the embodiment of the present application includes:

step 201, obtaining the target length and the start address.

The target length is the number of bytes of data to be read from the flash memory chip 102.

The start address is used to indicate a start position of reading data of a target length from the flash memory chip 102.

The way of the smart chip 101 acquiring the target length and the start address is the same as the way of the smart chip 101 acquiring the target data and the start address in step 101, and the specific implementation process may refer to the description of step 101, which is not described herein.

In addition, the data corresponding to the target length in the flash memory chip 102 may include null data.

Step 202, determining a first address of the flash memory chip according to the starting address.

The first address is less than or equal to the start address and is a multiple of the minimum addressing unit of the flash memory chip 102, or the first address is address 0.

The specific implementation process of step 202 may refer to the description of step 202, which is not described herein.

Step 203, reading the first data in the flash memory chip, which starts from the first address and has the length of the minimum addressing unit of the flash memory chip, into the cache area of the intelligent chip.

The specific implementation process of step 203 may refer to the description of step 203, which is not described herein.

Since the minimum addressing unit in the cache of the smart chip 101 is one byte, after the smart chip 101 reads the first data of the flash chip 102 starting from the first address and having the length of the minimum addressing unit of the flash chip 102 into the cache of the smart chip 101, the smart chip 101 can directly read the data of the target length in the cache of the smart chip 101.

And step 204, in the first data, reading second data which starts from the initial address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip into the memory chip.

The smart chip 101 may read second data in the cache area of the smart chip 101, which starts from the start address and has a length less than or equal to the minimum addressing unit of the flash memory chip 102.

Based on this, the smart chip 101 may send a data write signal to the memory chip 103. After the memory chip 103 receives the data write signal, the smart chip 101 may write the second data, which is in the buffer area of the smart chip 101 from the start address and has a length less than or equal to the minimum addressing unit of the flash memory chip 102, into the memory chip 103 for storage.

Thus, the smart chip 101 may determine that the second data, which starts from the start address and has a length less than or equal to the minimum addressing unit of the flash memory chip 102, in the cache area of the memory chip 103 where the smart chip 101 is stored.

Since the length of the second data may be less than or equal to the target length, the smart chip 101 needs to determine whether the length of the second data stored in the memory chip 103 is the target length.

The smart chip 101 may stop reading data from the flash memory chip 102 when it is determined that the length of the second data stored in the memory chip 103 is the target length. The smart chip 101 may continue to perform step 205 when it is determined that the length of the second data stored in the memory chip 103 is not the target length.

Step 205, updating the starting address to an address adjacent to the end address of the second data stored in the flash memory chip, and continuing to execute step 202 to step 205 until the length of the data in the memory chip is the target length.

The smart chip 101 may update the start address to an address adjacent to the end address where the second data is stored in the flash memory chip 102. Accordingly, the smart chip 101 may continue to perform steps 202-205, namely, continue to read the remaining data adjacent to and after the second data in the target data from the flash memory chip 102 and write the remaining data into the memory chip 103 until the length of the data in the memory chip 103 is the target length.

In summary, the smart chip 101 can read the data stored in the flash memory chip 102 into the memory chip 103 in units of one byte as an addressing unit.

According to the data reading method, the target length and the starting address are obtained. Based on the starting address, a first address of the flash memory chip may be determined. The first data which starts from the first address and is the minimum addressing unit of the flash memory chip in length can be read into the cache region of the intelligent chip, so that the first data stored in the flash memory chip in the minimum addressing unit, namely a plurality of bytes, can be translated into the cache region of the intelligent chip to be stored in a byte unit.

Then, in the first data, the second data which starts from the start address and has the length smaller than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip can be read into the storage chip, the second data which starts from the start address and is not multiple times of the minimum addressing unit of the flash memory chip can be read from the flash memory chip, and the read second data takes one byte as a unit and does not contain data stored in other bytes except the second data in the flash memory chip. When the length of the second data is not the target length, the starting address can be updated to be an address adjacent to the tail address of the second data stored in the flash memory chip, and the data can be continuously read from the flash memory chip, so that the data of the target length except the second data can be continuously read from the flash memory chip until the length of the data in the memory chip is the target length.

Therefore, when the initial address does not accord with the storage rule of the flash memory chip, namely the initial address is not the multiple of the minimum addressing unit of the flash memory chip or the address 0, the data stored in the flash memory chip can be successfully read into the storage chip by taking one byte as a unit, the data beyond the target length can not be read, and the occupation of the storage space of the storage chip is reduced.

As can be seen from the above description, the smart chip 101 may need to perform one reading or perform multiple readings to read all the data of the target length stored in the flash memory chip 102, i.e. the target data, into the memory chip 103.

For the case where the smart chip 101 reads data of a target length stored in the flash memory chip 102 all the way to the memory chip 103, the start address is not a multiple of the minimum addressing unit of the flash memory chip 102.

For the case that the intelligent chip 101 reads data of a target length stored in the flash memory chip 102 into the memory chip 103 all the time, the start address of the intelligent chip 101 is not a multiple of the minimum addressing unit of the flash memory chip 102 when the intelligent chip performs the first reading of the multiple readings. The smart chip 101 may determine the first address as a start address at each read after the first read, the start address being a multiple of a minimum addressing unit of the flash memory chip 102.

Based on the above description, before executing step 202, the smart chip 101 further needs to determine whether data of a target length can be read in the flash memory chip 102.

In some embodiments, the smart chip 101 may determine whether the data of the target length can be read in the flash memory chip 102 according to the target length and the maximum storage length of the flash memory chip 102.

When the target length is determined to be greater than the maximum read length of the flash memory chip 102, the smart chip 101 prompts that the target data cannot be read from the flash memory chip 102.

Based on the descriptions of fig. 1 and fig. 5, a specific implementation process of a data reading method provided by the embodiment of the present application is illustrated in the following with reference to fig. 6 and fig. 7.

As shown in fig. 6, the target length is 5 bytes. The starting address of the target length is address 5.

The minimum addressing unit of the flash memory chip 102 is four bytes. The maximum reading length N of the flash memory chip 102 and the address corresponding to each byte in the flash memory chip 102 may refer to the above description of the flash memory chip 102, which is not repeated herein.

Referring to fig. 7, fig. 7 is a schematic flowchart illustrating a data reading method according to an embodiment of the present disclosure. As shown in fig. 7, the data reading method according to the embodiment of the present application includes:

step 21, the target length and address 5 as shown in fig. 6 are obtained.

Step 22, determine whether the target length exceeds the maximum read length of the flash memory chip 102.

If yes, go to step 23. If not, step 24-step 30 are executed.

Step 23, prompting that the target data cannot be read from the flash memory chip 102.

Step 24, according to the address 5, determining that the first address in the flash memory chip 102 is the address 4, that is, determining the first address closest to the address 5 in the flash memory chip 102.

Step 25, reading the first data which is in the flash memory chip 102, starts from the address 4 and has the length of four bytes, into the cache area of the intelligent chip 101. As shown in fig. 6, data B5 to data B8 in the flash memory chip 102 are read into the buffer area of the smart chip 101.

And step 26, reading second data which starts from the address 5 and is three bytes in the cache area of the intelligent chip 101 in the first data into the memory chip 103. As shown in fig. 6, data B6 to B8 in the buffer area of the smart chip 101 are read into the memory chip 103.

At this time, the smart chip 101 reads only data corresponding to the target length of three bytes, i.e., the sixth byte to the eighth byte, stored in the flash memory chip 102, to the memory chip 103. Data corresponding to the target length of the two bytes, i.e., the ninth byte and the tenth byte, of the target length is not read into the memory chip 103. Therefore, the smart chip 101 may execute steps 27-29 to continue to read the data corresponding to the target length of the two bytes, i.e., the ninth byte and the tenth byte, stored in the flash memory chip 102 into the memory chip 103.

And step 27, updating the initial address to be the address 8.

Step 28, reading the first data which is in the flash memory chip 102, starts from the address 8 and is four bytes long, into the cache area of the smart chip 101. As shown in fig. 6, data B9 to data B12 in the flash memory chip 102 are read into the buffer area of the smart chip 101.

And step 29, in the first data, reading second data which is two bytes in length and starts from the address 8 in the cache area of the intelligent chip 101 into the memory chip 103. As shown in fig. 6, the data B9 and the data B10 in the buffer area of the smart chip 101 are read into the memory chip 103.

Thus, the smart chip 101 can read data of a target length stored in the flash memory chip 102 into the memory chip 103.

It can be seen that the smart chip 101 can read data from the flash chip 102 that is not a multiple of 4 of the starting address, i.e., the target length of address 5. When the smart chip 101 reads data of a target length of 5 bytes from the flash memory chip 102, data of other bytes in the flash memory chip 102 is not read.

In summary, the data reading method of the present application reads the data stored in the flash memory chip 102 into the cache area of the smart chip 101 in units of one byte. And then, reading the data in the buffer area of the smart chip 101 into the memory chip 103 by taking one byte as a unit. Therefore, when the intelligent chip 101 reads data from the flash memory chip 102, it is not necessary to satisfy a reading rule of the flash memory chip 102 for reading data in units of four bytes, and it is also not necessary to satisfy a reading rule that a start address of data of a read target length must be a multiple of 4 or is an address 0, thereby improving a utilization rate of a storage space in the storage chip 103.

Referring to fig. 8, fig. 8 is a schematic block diagram illustrating a structure of a data storage device according to an embodiment of the present application. As shown in fig. 8, the data storage device 300 of the present application may include:

an obtaining module 301, configured to obtain target data and a start address, where the start address is used to indicate a start position where the target data is stored in the flash memory chip 102;

a determining module 302, configured to determine a first address of the flash chip 102 according to the starting address, where the first address is smaller than or equal to the starting address and is a multiple of a minimum addressing unit of the flash chip 102, or the first address is address 0;

the storage module 303 is configured to read first data, which starts from a first address and is the minimum addressing unit of the flash memory chip 102, in the flash memory chip 102 into a cache area of the smart chip 101; in the first data, replacing data which starts from a start address and has a length smaller than or equal to the minimum addressing unit of the flash memory chip 102 in a cache region of the intelligent chip 101 with second data which starts from the start address and has a length smaller than or equal to the minimum addressing unit of the flash memory chip 102 in the target data to obtain replaced first data; writing the replaced first data in the cache region of the intelligent chip 101 into the flash memory chip 102, updating the initial address to an address adjacent to the last address of the second data stored in the flash memory chip 102, and continuing to execute the steps 102-105 until all the target data are stored in the flash memory chip 102.

In some embodiments, the determining module 302 is specifically configured to, when the starting address is not a multiple of the minimum addressing unit of the flash chip 102, determine that the first address is smaller than the starting address and is a multiple of the minimum addressing unit of the flash chip 102, or the first address is address 0; when the start address is a multiple of the minimum addressing unit of the flash memory chip 102, the first address is equal to the start address and is a multiple of the minimum addressing unit of the flash memory chip 102, or the first address is address 0.

In some embodiments, the determining module 302 is specifically configured to prompt that the target data cannot be stored in the flash memory chip 102 when the length of the target data is greater than the maximum storage length of the flash memory chip 102.

Referring to fig. 9, fig. 9 is a block diagram illustrating a structure of a data reading apparatus according to an embodiment of the present disclosure. As shown in fig. 9, the data reading apparatus 400 of the present application may include:

an obtaining module 401, configured to obtain a target length and a start address, where the target length is a number of bytes of data that needs to be read from the flash memory chip 102, and the start address is used to indicate a start position of the data of the target length read from the flash memory chip 102;

a determining module 402, configured to determine a first address of the flash chip 102 according to the starting address, where the first address is smaller than or equal to the starting address and is a multiple of a minimum addressing unit of the flash chip 102, or the first address is address 0;

a reading module 403, configured to read first data, which starts from a first address and is of a length of a minimum addressing unit of the flash memory chip 102, in the flash memory chip 102 into a cache area of the smart chip 101; reading second data which starts from a start address and has a length smaller than or equal to the minimum addressing unit of the flash memory chip 102 in the cache region of the intelligent chip 101 into the memory chip 103 in the first data; updating the starting address to an address adjacent to the end address of the second data stored in the flash memory chip 102, and continuing to execute the steps 202-205 until the length of the data in the memory chip 103 is the target length.

In some embodiments, the determining module 402 is specifically configured to, when the starting address is not a multiple of the minimum addressing unit of the flash chip 102, determine that the first address is smaller than the starting address and is a multiple of the minimum addressing unit of the flash chip 102, or the first address is address 0; when the start address is a multiple of the minimum addressing unit of the flash memory chip 102, the first address is equal to the start address and is a multiple of the minimum addressing unit of the flash memory chip 102, or the first address is address 0.

In some embodiments, the determining module 402 is specifically configured to prompt that the target data cannot be stored in the flash memory chip 102 when the length of the target data is greater than the maximum storage length of the flash memory chip.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other ways. For example, the above-described apparatus/network device embodiments are merely illustrative, and for example, the division of the above modules or units is only one logical function division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present application, and they should be construed as being included in the present application.

Claims

1. A method of data storage, the method comprising:

step 102, determining a first address of the flash memory chip according to the starting address, wherein the first address is less than or equal to the starting address and is a multiple of a minimum addressing unit of the flash memory chip, or the first address is address 0;

103, reading first data which starts from the first address and has the length of the minimum addressing unit of the flash memory chip in the flash memory chip into a cache region of an intelligent chip;

step 104, in the first data, replacing data which starts from the start address and has a length smaller than or equal to the minimum addressing unit of the flash memory chip in a cache region of the intelligent chip with second data which starts from the start address and has a length smaller than or equal to the minimum addressing unit of the flash memory chip in the target data to obtain replaced first data;

step 105, writing the replaced first data in the cache region of the intelligent chip into the flash memory chip, updating the initial address to be an address adjacent to the last address of the second data stored in the flash memory chip, and continuing to execute the step 102 to the step 105 until all the target data are stored in the flash memory chip.

2. The method of claim 1, wherein the method comprises:

when the starting address is not a multiple of the minimum addressing unit of the flash memory chip, the first address is smaller than the starting address and is a multiple of the minimum addressing unit of the flash memory chip, or the first address is address 0;

when the starting address is a multiple of the minimum addressing unit of the flash memory chip, the first address is equal to the starting address and is a multiple of the minimum addressing unit of the flash memory chip, or the first address is address 0.

3. The method of claim 2, wherein prior to determining the first address of the flash memory chip based on the starting address, the method further comprises:

4. A method of reading data, the method comprising:

step 201, obtaining a target length and an initial address, where the target length is the number of bytes of data to be read from a flash memory chip, and the initial address is used to indicate an initial position of the data of the target length read from the flash memory chip;

step 202, according to the initial address, determining a first address of the flash memory chip, wherein the first address is smaller than or equal to the initial address and is a multiple of a minimum addressing unit of the flash memory chip, or the first address is address 0;

step 203, reading first data which starts from the first address and has the length of the minimum addressing unit of the flash memory chip in the flash memory chip into a cache region of an intelligent chip;

step 204, in the first data, reading second data which starts from the initial address and has a length smaller than or equal to the minimum addressing unit of the flash memory chip in the cache region of the intelligent chip into a storage chip;

step 205, updating the starting address to an address adjacent to the last address of the second data stored in the flash memory chip, and continuing to execute steps 202 to 205 until the length of the data in the memory chip is the target length.

5. The method of claim 4, wherein the method comprises:

6. The method of claim 4, wherein prior to determining the first address of the flash memory chip based on the starting address, the method further comprises:

and when the target length is larger than the maximum reading length of the flash memory chip, prompting that the target data cannot be read from the flash memory chip.

7. A data storage device, characterized in that it comprises means for performing the method according to any one of claims 1-3.

8. A data reading apparatus comprising means for performing the method of any one of claims 4 to 6.

9. A processor comprising a memory, a controller and a computer program stored in the memory and executable on the controller, characterized in that the controller implements the method according to any of claims 1-6 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a controller, carries out the method according to any one of claims 1-6.