CN115842524A - Semiconductor circuit having a plurality of transistors - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor circuit including a transimpedance amplifier capable of converting an input current into a voltage with high accuracy. The semiconductor circuit of the present embodiment includes: a transimpedance amplifier TIA having a first input terminal to which a reference voltage VB is supplied, a second input terminal to which an input current is supplied, and a first output terminal, the transimpedance amplifier TIA converting an input current into an output voltage VINP and outputting the output voltage VINP from the first output terminal; and a transimpedance amplifier TIAr having a third input terminal to which a reference voltage VB is supplied, a fourth input terminal, and a second output terminal, and having the same circuit configuration as the transimpedance amplifier TIA, and outputting an output voltage VINN from the second output terminal.

Description

Semiconductor circuit having a plurality of transistors

This application is filed on the basis of Japanese patent application No. 2021-153422 (application date: 9/21/2021) and priority is claimed. The present application incorporates the entire contents of the base application by reference thereto.

Technical Field

The present invention relates to a semiconductor circuit including a Transimpedance Amplifier (Transimpedance Amplifier).

Background

It is known to have a transimpedance amplifier which converts an input current into a voltage.

Disclosure of Invention

The present embodiment provides a semiconductor circuit including a transimpedance amplifier capable of converting an input current into a voltage with high accuracy.

The semiconductor circuit of the present embodiment includes: a first transimpedance amplifier having a first input terminal to which a reference voltage is supplied, a second input terminal to which an input current is supplied, and a first output terminal that converts the input current into a first output voltage and outputs the first output voltage from the first output terminal; and a second transimpedance amplifier having a third input terminal to which the reference voltage is supplied, a fourth input terminal, and a second output terminal, and having the same circuit configuration as the first transimpedance amplifier, and outputting the second output voltage from the second output terminal.

Drawings

Fig. 1 is a circuit diagram showing a configuration of a semiconductor circuit according to a first embodiment.

Fig. 2 is a circuit diagram showing a configuration of a variable resistance circuit according to the first embodiment.

Fig. 3 is a circuit diagram showing a configuration of a switch circuit in the variable resistance circuit according to the first embodiment.

Fig. 4 is a circuit diagram showing another configuration example of the input/output unit in the first embodiment.

Fig. 5 is a diagram showing a relationship between an effective resistance value and a power supply voltage of the variable resistance circuit according to the first embodiment.

Fig. 6 is a circuit diagram showing a configuration of a semiconductor circuit according to a second embodiment.

Fig. 7 is a circuit diagram showing a configuration of a semiconductor circuit according to a third embodiment.

Fig. 8 is a circuit diagram showing a configuration of a semiconductor circuit according to a fourth embodiment.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the following description, the constituent elements having the same functions and configurations are given the same reference numerals. In the embodiments described below, apparatuses and methods for embodying the technical ideas of the embodiments are exemplified, and the materials, shapes, structures, arrangements, and the like of the constituent members are not limited to the embodiments described below.

The functional modules may be implemented as a combination of hardware, computer software, or both. The functional modules are not necessarily divided as in the following examples. For example, some of the functions may be performed by functional blocks different from the illustrated functional blocks. Furthermore, the illustrated functional modules may also be further divided into small functional sub-modules.

1. First embodiment

The semiconductor circuit of the first embodiment will be described below.

1.1 construction of semiconductor circuits

Fig. 1 is a circuit diagram showing a configuration of a semiconductor circuit according to a first embodiment. The semiconductor circuit 1 includes two transimpedance amplifiers TIA and TIAr, two input/output units IO and IOr for ESD (electrostatic discharge) destruction protection, a differential input analog-digital conversion circuit (also referred to as ADC) 11, and an input terminal WE.

An input current is input to the input terminal WE. The transimpedance amplifiers TIA and TIAr are circuits that convert input currents into voltages, respectively. Specifically, the present invention relates to a circuit that amplifies a current flowing through a transimpedance amplifier by impedance conversion and outputs the amplified current as a voltage signal. The transimpedance amplifier TIAr is a replica (replica) circuit of the transimpedance amplifier TIA.

The input/output unit IO is an ESD protection circuit that protects the semiconductor circuit 1 from a surge (surge) voltage such as static electricity entering from the input terminal WE or prevents malfunction due to the surge voltage. The input/output unit IOr is a replica circuit of the input/output unit IO.

The differential input analog-digital conversion circuit 11 outputs a digital signal from the two differentially input output voltages. That is, the analog-digital conversion circuit 11 receives two output voltages VINP and VINN from the transimpedance amplifiers TIA and TIAr, removes an in-phase signal between the output voltage VINP and the output voltage VINN, converts the same into a digital value, and outputs an output signal DOUT.

As described above, the transimpedance amplifier TIAr and the input/output unit IOr are replica circuits of the transimpedance amplifier TIA and the input/output unit IO. That is, the transimpedance amplifier TIAr and the input/output unit IOr have the same circuit configuration as the transimpedance amplifier TIA and the input/output unit IO. Specifically, the transimpedance amplifier TIAr has the same circuit elements as those of the transimpedance amplifier TIA. The circuit elements of the transimpedance amplifier TIAr have substantially the same circuit constants as the circuit elements of the transimpedance amplifier TIA. The input/output unit IOr has the same circuit elements as those of the input/output unit IO. The circuit elements of the input/output unit IOr have substantially the same circuit constants as those of the circuit elements of the input/output unit IO.

Hereinafter, a path including the input terminal WE, the input/output unit IO, and the transimpedance amplifier TIA is referred to as a measurement signal path. A path including the replica circuit, i.e., the input/output unit IOr and the transimpedance amplifier TIAr is referred to as an error (or analog) signal path.

1.1.1 Trans-impedance Amplifier construction

Next, the configuration of the transimpedance amplifiers TIA and TIAr will be described.

As shown in fig. 1, the transimpedance amplifier TIA includes an operational amplifier (or operational amplifier) OP, a variable resistance circuit VR, and a voltage source for supplying a reference voltage VB. The operational amplifier OP amplifies and outputs the input signal. The variable resistor circuit VR is a feedback resistor and is a circuit whose resistance value can be changed.

The transimpedance amplifier TIAr has an operational amplifier OPr, a variable resistance circuit VRr, and a voltage source that supplies a reference voltage VB. The operational amplifier OPr has the same circuit elements and circuit constants as the operational amplifier OP. The variable resistor circuit VRr has the same circuit elements and circuit constants as the variable resistor circuit VR.

The following describes the configurations of the variable resistor circuits VR and VRr.

Fig. 2 is a circuit diagram showing the configuration of the variable resistor circuit VR (or VRr). The negative input terminal (or the inverting input terminal) of the operational amplifier OP is connected in series to the output terminal of the operational amplifier OP via a switching circuit S0, resistors R1, R2, 8230, and Rn (n is a natural number equal to or greater than 1). A switch circuit S1 is connected between a node between the switch circuit S0 and the resistor R1 and a node between the resistor R1 and the resistor R2. A switch circuit S2 is connected between a node between the switch circuit S0 and the resistor R1 and a node between the resistor R2 and the resistor R3. Similarly, a switch circuit Sn is connected between a node between the switch circuit S0 and the resistor R1 and a node between the resistor Rn and the output terminal of the operational amplifier OP. The configuration of the variable resistance circuit VRr is the same as that of the variable resistance circuit VR described above.

Fig. 3 shows the configuration of the switching circuit S0 or Sn in the variable resistor circuit VR (or VRr). The switch circuit S0 or Sn includes a p-channel MOS electric field effect transistor (hereinafter, referred to as a pMOS transistor) T1 and an n-channel MOS electric field effect transistor (hereinafter, referred to as an nMOS transistor) T2.

The drain (or source) of the pMOS transistor T1 is connected to the source (or drain) of the nMOS transistor T2. The source (or drain) of the pMOS transistor T1 is connected to the drain (or source) of the nMOS transistor T2.

The control signal CS0 is input to the gate of the nMOS transistor T2 of the switching circuit S0. A control signal CS0b, which is an inversion signal of the control signal CS0, is input to the gate of the pMOS transistor T1 of the switching circuit S0. Further, the power supply voltage VDD is supplied to the back gate of the pMOS transistor T1 of the switch circuit S0. Then, ground voltage GND is supplied to the back gate of nMOS transistor T2 of switch circuit S0.

The control signal CSn is input to the gate of the nMOS transistor T2 of the switch circuit Sn. A signal CSnb which is an inversion signal of the control signal CSn is input to the gate of the pMOS transistor T1 of the switch circuit Sn. Further, the power supply voltage VDD is supplied to the back gate of the pMOS transistor T1 of the switch circuit Sn. Then, ground voltage GND is supplied to the back gate of nMOS transistor T2 of switch circuit Sn.

In such a variable resistance circuit VR, the resistance RTIA can be changed by setting the switch circuits S0 to Sn to the closed state (or the connected state) or the open state (or the disconnected state) by the control signals CS0 to CSn and CS0b to CSnb.

As described above, the variable resistor circuit VRr has the same circuit configuration as the variable resistor circuit VR. The control signals CS0 to CSn and CS0b to CSnb are input to the switching circuits S0 to Sn of the variable resistor circuit VRr in the same manner as the switching circuits of the variable resistor circuit VR. Thus, the resistance value RTIAr of the variable resistance circuit VRr is set to be substantially the same value as the resistance value RTIA of the variable resistance circuit VR.

In the variable resistor circuit VR, for example, a Junction-drain (Junction Leak) current Isw is generated in a pn Junction portion of the pMOS transistor T1 and the nMOS transistor T2 existing in the switching circuits S0 to Sn. Similarly, in the variable resistor circuit VRr, a junction leakage current Isw is generated in the pn junction of the pMOS transistor T1 and the nMOS transistor T2 existing in the switch circuits S0 to Sn.

Here, the variable resistance circuit VRr has the same circuit configuration as the variable resistance circuit VR. That is, the variable resistance circuit VRr has the same circuit elements and circuit constants as the variable resistance circuit VR. Specifically, each of the variable resistor circuits VR and VRr includes a pMOS transistor T1 and an nMOS transistor T2, and resistors R1 to Rn. The pMOS transistor T1 and nMOS transistor T2 and resistors R1 to Rn of the variable resistor circuit VRr have substantially the same circuit constants as the pMOS transistor T1 and nMOS transistor T2 and resistors R1 to Rn of the variable resistor circuit VR. Therefore, the leakage currents Isw generated in the variable resistance circuits VR and VRr, respectively, are substantially the same, that is, have substantially the same current value.

1.1.2 Structure of input/output part (ESD protection Circuit)

Next, the configuration of the input/output units IO and IOr will be described.

As shown in fig. 1, in the measurement signal path, the input/output unit IO is connected to the negative input terminal of the operational amplifier OP. The input/output unit IO includes diodes D1 and D2. Diode D1 is connected in the forward direction from a ground voltage node to which ground voltage GND is supplied to a node to which the negative input terminal is connected. The diode D2 is connected in the forward direction from the node of the negative input terminal to the power supply voltage node to which the power supply voltage VDD is supplied.

On the other hand, in the error signal path, the input/output unit IOr is connected to the negative input terminal of the operational amplifier OPr. The input/output unit IOr has the same circuit elements and circuit constants as the input/output unit IO. That is, the input/output unit IOr has diodes D1 and D2, similarly to the input/output unit IO. The diode D1 is connected in the forward direction from the ground voltage node to the node to which the negative input terminal is connected. The diode D2 is connected in the forward direction from the node of the negative input terminal to the power supply voltage node.

In the input/output unit IO, for example, a leakage current Iio occurs at a pn junction of the diodes D1 and D2 present in the input/output unit IO. Similarly, in the input/output section IOr, a leakage current Iio occurs in the pn junction of the diodes D1 and D2 present in the input/output section IOr.

Here, the input/output unit IOr has the same circuit configuration as the input/output unit IO. That is, the input/output unit IOr has the same circuit elements and circuit constants as the input/output unit IO. Specifically, the input/output units IO and IOr each have diodes D1 and D2. The diodes D1 and D2 of the input/output unit IOr have substantially the same circuit constant as the diodes D1 and D2 of the input/output unit IO. Therefore, leakage currents Iio generated in the input/output units IO and IO r are substantially the same, that is, have substantially the same current value.

Fig. 4 is a circuit diagram showing another configuration example of the input/output unit IO and IOr. The input/output unit IO may be composed of an nMOS transistor T3 and a pMOS transistor T4. The gate and drain of nMOS transistor T3 are connected to the ground voltage node, and the source of nMOS transistor T3 is connected to the negative input terminal of operational amplifier OP. The gate and drain of the pMOS transistor T4 are connected to the power supply voltage node, and the source of the pMOS transistor T4 is connected to the negative input terminal of the operational amplifier OP.

Similarly, the input/output unit IOr may be composed of an nMOS transistor T3 and a pMOS transistor T4. The gate and drain of nMOS transistor T3 are connected to the ground voltage node, and the source of nMOS transistor T3 is connected to the negative input terminal of operational amplifier OPr. The gate and drain of the pMOS transistor T4 are connected to the power supply voltage node, and the source of the pMOS transistor T4 is connected to the negative input terminal of the operational amplifier OPr.

In the configuration example shown in fig. 4, for example, a leakage current Iio is generated also in a junction portion between the nMOS transistor T3 and the pMOS transistor T4 existing in the input/output portion IO. Similarly, a leakage current Iio is generated at a junction of the nMOS transistor T3 and the pMOS transistor T4 existing in the input/output unit IOr.

Here, the nMOS transistor T3 and the pMOS transistor T4 of the input/output unit IOr have substantially the same circuit constants as the nMOS transistor T3 and the pMOS transistor T4 of the input/output unit IO. Therefore, leakage currents Iio generated in the input/output units IO and IOr are substantially the same, that is, have substantially the same current value.

Hereinafter, circuit connection in the semiconductor circuit 1 according to the first embodiment will be described.

As shown in fig. 1, the input terminal WE is connected to the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA. The input terminal WE is connected to the output terminal of the operational amplifier OP via the variable resistor circuit VR in the transimpedance amplifier TIA. An input/output unit IO is connected to a node between the negative input terminal and the input terminal WE of the operational amplifier OP.

A voltage source supplying the reference voltage VB is connected to a positive input terminal (or a non-inverting input terminal) of the operational amplifier OP. The output terminal of the operational amplifier OP is connected to the first input terminal of the differential input analog-digital conversion circuit 11.

The input/output unit IOr is connected to the negative input terminal of the operational amplifier OPr of the transimpedance amplifier TIAr. The negative input terminal of the operational amplifier OPr is connected to the output terminal of the operational amplifier OPr via the variable resistance circuit VRr in the transimpedance amplifier TIAr.

A voltage source supplying the reference voltage VB is connected to the positive input terminal of the operational amplifier OPr. The output terminal of the operational amplifier OPr is connected to the second input terminal of the differential input analog-digital conversion circuit 11.

1.2 operation of the semiconductor Circuit

The operation of the semiconductor circuit 1 according to the first embodiment will be described below. Here, an operation when the current output sensor SE is connected to the input terminal WE will be described.

When the operation of the current output sensor SE is started, the sensor current Isen flows in the current output sensor SE, and the reference voltage VB is supplied to the positive input terminal of the operational amplifier OP. Then, the voltages of the input terminal WE and the negative input terminal of the operational amplifier OP are set to the reference voltage VB supplied to the positive input terminal by the virtual short-circuit characteristic of the operational amplifier OP, and are stabilized.

Here, since the impedance of the negative input terminal of the operational amplifier OP is very high, the sensor current Isen flowing in the current output sensor SE flows from the output side of the operational amplifier OP through the variable resistance circuit VR and into the current output sensor SE. In this case, the output voltage VINP of the operational amplifier OP is set to a voltage obtained by adding the product of the resistance value RTIA of the variable resistance circuit VR and the sensor current Isen to the reference voltage VB.

Thus, the output voltage VINP of the operational amplifier OP is represented by the following expression (1).

VINP＝VB+RTIA·Isen (1)

In the circuit shown in fig. 1, as described above, the leakage current Iio occurs in the input/output unit IO, and the leakage current Isw occurs in the variable resistor circuit VR. If the leakage currents Iio and Isw are generated, the current flowing in the variable resistance circuit VR decreases. Therefore, an error occurs in the effective resistance value of the variable resistance circuit VR due to the error currents of the leakage currents Iio and Isw. In particular, as the power supply voltage VDD increases, the leakage current Isw generated in the switching circuits S0 to Sn of the variable resistor circuit VR increases. Therefore, the higher the power supply voltage VDD, the larger the error in the effective resistance value of the variable resistance circuit VR.

When the leakage currents Iio and Isw are considered, the equation (1) is expressed by the following equation (2).

VINP＝VB+RTIA·Isen-RTIA·(Iio+Isw) (2)

On the other hand, the output voltage VINN of the operational amplifier OPr in the transimpedance amplifier TIAr in the replica circuit (or the error signal path) is as follows.

In the input/output unit IOr and the variable resistance circuit VRr in the replica circuit, leakage currents Iio and Isw are generated in the same manner as in the input/output unit IO and the variable resistance circuit VR in the measurement signal path.

Thus, the output voltage VINN of the operational amplifier OPr is expressed by the following expression (3).

VINN＝VB-RTIA·(Iio+Isw) (3)

Here, the circuit elements and circuit constants of the input/output unit IOr and the variable resistance circuit VRr in the replica circuit are the same as those of the input/output unit IO and the variable resistance circuit VR in the measurement signal path. Therefore, the leakage currents Iio and Isw generated in the replica circuit are substantially the same as, i.e., substantially equal to, the leakage currents Iio and Isw generated in the measurement signal path.

The output voltage VINP and the output voltage VINN are input to the differential input analog-digital conversion circuit 11. The differential input analog-digital conversion circuit 11 obtains a voltage difference between the output voltage VINP and the output voltage VINN, further digitizes the voltage difference, and outputs an output signal DOUT. That is, the differential input analog-digital conversion circuit 11 removes the in-phase signal component between the output voltage VINP and the output voltage VINN, converts the voltage from which the in-phase signal component is removed into a digital value, and outputs the output signal DOUT.

Thus, the output signal DOUT is represented by the following expression (4) (= expression (2) -expression (3)).

DOUT＝D(VINP-VINN)＝D(RTIA·Isen) (4)

D (X) represents a value obtained by converting the analog value X into the digital value X.

Thus, an error in the effective resistance value of the variable resistance circuit VR due to the leak currents Iio and Isw can be removed, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

As described above, in the present embodiment, it is possible to reduce an error in the effective resistance value of the variable resistance circuit VR due to a leakage current generated in the input/output unit IO and the variable resistance circuit VR. Thus, the effective resistance value of the variable resistor circuit VR, which is a conversion gain in the transimpedance amplifier TIA, can be set constant regardless of the power supply voltage VDD. Fig. 5 shows the relationship between the effective resistance value of the variable resistance circuit VR and the power supply voltage VDD. As shown in fig. 5, even if the power supply voltage VDD changes, the effective resistance value of the variable resistance circuit VR does not change and is constant. Since the effective resistance value of the variable resistance circuit VR can be made constant, the transimpedance amplifier TIA can have high-precision current-voltage conversion characteristics.

1.3 effects of the first embodiment

According to the first embodiment, a semiconductor circuit including a transimpedance amplifier which can convert an input current into a voltage with high accuracy can be provided.

The following describes the effects of the first embodiment. In a transimpedance amplifier that converts an input current into a voltage, in order to convert a minute input current into a large output voltage and to make a conversion gain variable, it is necessary to install a resistor circuit having a very large resistance value and a switching circuit for switching the resistance value.

When a variable resistance circuit having a high resistance and a variable function is mounted on a semiconductor silicon substrate, there is a problem that a large error occurs in a conversion gain for converting a current in a transimpedance amplifier into a voltage due to a leakage current of a switching circuit for realizing a switching function and a leakage current of an input/output unit for ESD destruction protection.

The semiconductor circuit 1 according to the first embodiment includes a transimpedance amplifier TIAr and an input/output unit IOr having replica structures for the transimpedance amplifier TIA and the input/output unit IO. The transimpedance amplifier TIAr and the input/output unit IOr are circuits that accurately simulate the leakage currents Iio and Isw, which are important factors for the error of the variable frequency gain of the transimpedance amplifier TIA.

The differential input analog-digital conversion circuit 11 removes an error component from the output voltage VINP of the transimpedance amplifier TIA by obtaining a voltage difference between the output voltage VINP of the transimpedance amplifier TIA and the output voltage VINN of the transimpedance amplifier TIA. Then, the differential input analog-digital conversion circuit 11 converts the voltage from which the error component is removed into the output signal DOUT of a digital value.

In the first embodiment, the transimpedance amplifier TIAr and the input/output unit IOr of the error signal path are configured by replica circuits of the transimpedance amplifier TIA and the input/output unit IO of the measurement signal path. Therefore, when the power supply voltage VDD fluctuates and the leakage current fluctuates, particularly when the power supply voltage VDD becomes high and the leakage current increases, the leakage current in the error signal path also increases in accordance with the increase in the leakage current in the measurement signal path. In other words, the transimpedance amplifier TIAr and the input/output unit IOr have the same circuit elements and circuit constants as the transimpedance amplifier TIA and the input/output unit IO. Therefore, when the power supply voltage VDD fluctuates, the leakage current in the error signal path and the leakage current in the measurement signal path also fluctuate similarly, and these current amounts are substantially equal.

Further, even when the temperature fluctuates and the leakage current fluctuates, the leakage current in the error signal path also fluctuates similarly in accordance with the fluctuation of the leakage current in the measurement signal path. That is, when the temperature varies, the leakage current in the error signal path and the leakage current in the measurement signal path also vary similarly, and these current amounts are substantially equal.

Therefore, by obtaining the voltage difference between the output voltage VINP of the transimpedance amplifier TIA in the measurement signal path and the output voltage VINN of the transimpedance amplifier TIAr in the error signal path, it is possible to eliminate an error in the effective resistance value of the variable resistance circuit VR caused by a leakage current in the measurement signal path, and it is possible to maintain the effective resistance value of the variable resistance circuit VR at a predetermined value. Thus, in the semiconductor circuit 1 according to the first embodiment, the input current can be converted into a voltage with high accuracy regardless of variations in the power supply voltage VDD and the temperature.

As described above, according to the semiconductor circuit 1 of the first embodiment, a transimpedance amplifier that can convert an input current into a voltage with high accuracy can be realized. That is, a transimpedance amplifier having a high-precision current-voltage conversion characteristic can be realized.

The first embodiment described above is presented as an example, and is not intended to limit the scope of the invention. The first embodiment can be implemented in other various ways.

2. Second embodiment

The semiconductor circuit of the second embodiment will be described below. In the first embodiment, the output voltages of the transimpedance amplifiers TIA and TIAr are input to the differential-input analog-to-digital conversion circuit, but in the second embodiment, the output voltages of the transimpedance amplifiers TIA and TIAr are input to the single-ended input analog-to-digital conversion circuit via the differential-input/single-ended output conversion amplifier. In the second embodiment, the description will be given mainly on the difference from the first embodiment. Other configurations and operations not described are the same as those of the first embodiment.

2.1 construction of semiconductor circuits

Fig. 6 is a circuit diagram showing a configuration of a semiconductor circuit according to a second embodiment. The semiconductor circuit 2 includes two transimpedance amplifiers TIA and TIAr, two input/output units IO and IOr for ESD destruction protection, a differential input/single-ended output conversion amplifier (or differential input amplification circuit) OPd, a single-ended input analog-digital conversion circuit 12, and an input terminal WE.

The transimpedance amplifiers TIA and TIAr and the input/output units IO and IOr included in the semiconductor circuit 2 are the same as those in the first embodiment, and therefore description thereof is omitted.

The output terminal of the operational amplifier OP in the transimpedance amplifier TIA is connected to the negative input terminal of the differential input/single-ended output conversion amplifier OPd via the resistor Ra. The output terminal of the operational amplifier OPr in the transimpedance amplifier TIAr is connected to the positive input terminal of the output conversion amplifier OPd via the resistor Ra. A voltage source supplying the reference voltage VB is connected to the positive input terminal of the conversion amplifier OPd via a resistor Rb. The output terminal of the differential input/single-ended output conversion amplifier OPd is connected to the negative input terminal of the conversion amplifier OPd via a resistor Rb.

The output terminal of the differential input/single-ended output conversion amplifier OPd is connected to the input terminal of the analog-digital conversion circuit 12. Then, the output signal DOUT is output from the output terminal of the analog-digital conversion circuit 12 having a single-ended input.

2.2 operation of the semiconductor Circuit

The operation of the semiconductor circuit 2 according to the second embodiment will be described below.

The operation of the transimpedance amplifier TIA and the input/output unit IO in the measurement signal path and the operation of the transimpedance amplifier TIAr and the input/output unit IOr in the error signal path are the same as those in the first embodiment described above. Therefore, the output voltage VINP is output from the operational amplifier OP in the transimpedance amplifier TIA, and the output voltage VINN is output from the operational amplifier OPr in the transimpedance amplifier TIAr.

The output voltage VINP is input to the negative input terminal of the differential input/single-ended output conversion amplifier OPd, and the output voltage VINN is input to the positive input terminal of the conversion amplifier OPd. The conversion amplifier OPd obtains a voltage difference between the output voltage VINP and the output voltage VINN, and outputs the output voltage VOUT. That is, the conversion amplifier OPd removes the in-phase signal component between the output voltage VINP and the output voltage VINN, and outputs the output voltage VOUT from which the in-phase signal component is removed.

The analog-digital conversion circuit 12 converts the output voltage VOUT of the analog signal into a digital value, and outputs an output signal DOUT.

As described above, in the second embodiment, the error in the effective resistance value of the variable resistance circuit VR due to the leak currents Iio and Isw can be removed in the same manner as in the first embodiment, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

2.3 Effect of the second embodiment

According to the second embodiment, a semiconductor circuit including a transimpedance amplifier which can convert an input current into a voltage with high accuracy can be provided.

The semiconductor circuit 2 according to the second embodiment includes a transimpedance amplifier TIAr and an input/output unit IOr having replica structures with respect to the transimpedance amplifier TIA and the input/output unit IO. The transimpedance amplifier TIAr and the input/output unit IOr are circuits that accurately simulate the leakage currents Iio and Isw, which are important factors for the error of the variable frequency gain of the transimpedance amplifier TIA.

The differential input/single-ended output conversion amplifier OPd removes an error component from the output voltage VINP of the transimpedance amplifier TIA by obtaining a voltage difference between the output voltage VINP of the transimpedance amplifier TIA and the output voltage VINN of the transimpedance amplifier TIAr. Further, the analog-digital conversion circuit 12 converts the output voltage VOUT from which the error component is removed into an output signal DOUT of a digital value.

In the second embodiment, by obtaining the voltage difference between the output voltage VINP of the transimpedance amplifier TIA in the measurement signal path and the output voltage VINN of the transimpedance amplifier TIAr in the error signal path, an error in the effective resistance value of the variable resistance circuit VR caused by a leakage current in the measurement signal path can be removed, and the effective resistance value of the variable resistance circuit VR can be maintained at a predetermined value. Thus, in the semiconductor circuit 2 according to the second embodiment, the input current can be converted into a voltage with high accuracy regardless of variations in the power supply voltage VDD and the temperature.

The second embodiment described above is presented as an example, and is not intended to limit the scope of the invention. The second embodiment can be implemented in other various ways.

3. Third embodiment

The semiconductor circuit 3 of the third embodiment will be explained below. In the third embodiment, one transimpedance amplifier TIA is operated in a time-sharing manner, and the previous and subsequent output signals are subtracted, thereby removing an error component in the output voltage of the transimpedance amplifier TIA. In the third embodiment, the description will be given mainly on the difference from the first embodiment. Other configurations and operations not described are the same as those of the first embodiment.

3.1 construction of semiconductor circuits

Fig. 7 is a circuit diagram showing a configuration of a semiconductor circuit 3 according to a third embodiment. The semiconductor circuit 3 includes a transimpedance amplifier TIA, an input/output unit IO for ESD destruction protection, a single-ended analog-to-digital conversion circuit 12, a switch circuit 31, a memory circuit 32, a subtractor 33, and an input terminal WE.

The transimpedance amplifier TIA, the input/output unit IO, and the analog-digital conversion circuit 12 included in the semiconductor circuit 3 are the same as those of the first or second embodiment, and therefore, description thereof is omitted.

A switch circuit 31 is connected between the input terminal WE, the input/output unit IO, and the transimpedance amplifier TIA. The output terminal of the operational amplifier OP in the transimpedance amplifier TIA is connected to the input terminal of the analog-digital conversion circuit 12. The output terminal of the analog-digital conversion circuit 12 is connected to the subtractor 33 via the storage circuit 32. Further, the output terminal of the analog-digital conversion circuit 12 is connected to the subtractor 33 without via the memory circuit 32. Then, the output signal DOUT is output from the output terminal of the subtractor 33.

3.2 operation of the semiconductor Circuit

The operation of the semiconductor circuit 3 according to the third embodiment will be described below.

In the third embodiment, the output signal DOUT is obtained by subtracting the output obtained by operating the transimpedance amplifier TIA in a time-sharing manner, the operation when the switch circuit 31 is off (or disconnected), and the operation when the switch circuit 31 is on (or connected).

In the following description, the operation when the switch circuit 31 is off is referred to as "off-state operation", and the operation when the switch circuit 31 is on is referred to as "on-state operation". The off-state operation corresponds to the operation of the error signal path (or the replica circuit) in the first embodiment, and the on-state operation corresponds to the operation of the measurement signal path in the first embodiment.

First, the switching circuit 31 is set to the off state, and performs the off state operation. In the off-state operation, the output voltage VOUT1 of the operational amplifier OP in the transimpedance amplifier TIA is shown as follows.

A leakage current Iio is generated in the input/output unit IO, and a leakage current Isw is generated in the variable resistor circuit VR in the transimpedance amplifier TIA.

Thus, the output voltage VOUT1 of the operational amplifier OP is expressed by the following expression (5).

VOUT1＝VB+RTIA·(Iio+Isw) (5)

The output voltage VOUT1 is input to the analog-digital conversion circuit 12. The output voltage VOUT1 input to the analog-digital conversion circuit 12 is converted from an analog signal to a digital signal, and is output as an output signal DOUT1. The output signal DOUT1 is input to the storage circuit 32 and stored in the storage circuit 32. The output signal DOUT1 is represented by the following expression (5 a).

DOUT1＝D(VOUT1)

＝D(VB+RTIA·(Iio+Isw)) (5a)

Next, the off-state operation is performed, and the switching circuit 31 is set to the on state and performs the on-state operation. In the on state operation, the output voltage VOUT2 of the operational amplifier OP in the transimpedance amplifier TIA is shown as follows.

If the switch circuit 31 is set to the on state, a current Isen flows through the transimpedance amplifier TIA, and the reference voltage VB is supplied to the positive input terminal of the operational amplifier OP. In the on state operation, similarly to the off state operation, a leakage current Iio is generated in the input/output unit IO, and a leakage current Isw is generated in the variable resistor circuit VR in the transimpedance amplifier TIA.

Thus, the following expression (6) represents the output voltage VOUT2 of the operational amplifier OP.

VOUT2＝VB+RTIA·(Isen+Iio+Isw) (6)

The output voltage VOUT2 is input to the analog-digital conversion circuit 12. The output voltage VOUT2 input to the analog-digital conversion circuit 12 is converted from an analog signal to a digital signal, and is output as an output signal DOUT2. The output signal DOUT2 is input to the subtractor 33. The output signal DOUT2 is represented by the following expression (6 a).

DOUT2＝D(VOUT2)

＝D(VB+RTIA·(Isen+Iio+Isw))(6a)

Next, the output signal DOUT1 is subtracted from the output signal DOUT2 by the subtractor 33, and the output signal DOUT is output. The output signal DOUT is represented by the following formula (7) (= formula (6 a) -formula (5 a)).

DOUT＝DOUT2-DOUT1＝D(RTIA·Isen) (7)

Thus, an error in the effective resistance value of the variable resistance circuit VR due to the leak currents Iio and Isw can be removed, and the output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

3.3 Effect of the third embodiment

According to the third embodiment, a transimpedance amplifier that can convert an input current into a voltage with high accuracy can be provided.

The semiconductor circuit 3 according to the third embodiment includes a switch circuit 31 between the transimpedance amplifier TIA and the input/output unit IO and the input terminal WE, and includes a memory circuit 32 and a subtractor 33 at an output stage of the analog-digital conversion circuit 12. First, the switch circuit 31 is set to an off state to operate the transimpedance amplifier TIA. Thus, the output voltage VOUT1 generated by the leakage currents Iio and Isw, which are important factors of the error of the variable frequency gain of the transimpedance amplifier TIA, is output from the transimpedance amplifier TIA. The output voltage VOUT1 is converted into an output signal DOUT1 of a digital value by the analog-digital conversion circuit 12, and the output signal DOUT1 is stored in the memory circuit 32.

Next, the switch circuit 31 is set to the on state to operate the transimpedance amplifier TIA. Thus, the output voltage VOUT2 generated by the sensor current Isen, the drain currents Iio, and Isw is output from the transimpedance amplifier TIA. The output voltage VOUT2 is converted into an output signal DOUT2 of a digital value by the analog-digital conversion circuit 12, and the output signal DOUT2 is output to the subtractor 33. Then, the subtractor 33 subtracts the output signal DOUT1 from the output signal DOUT2, and removes an error component in the output signal DOUT2. Then, the output signal DOUT from which the error component is removed is output from the subtractor 33.

In the third embodiment, by subtracting the output signal DOUT1 of the transimpedance amplifier TIA when the switch circuit 31 is off from the output signal DOUT2 of the transimpedance amplifier TIA when the switch circuit 31 is on, an error in the effective resistance value of the variable resistance circuit VR caused by a leakage current when the switch circuit 31 is on can be removed, and the effective resistance value of the variable resistance circuit VR can be maintained at a predetermined value. Thus, in the semiconductor circuit 3 according to the third embodiment, the input current can be converted into a voltage with high accuracy without being affected by variations in the power supply voltage VDD and the temperature.

In addition, in the third embodiment, since it is not necessary to provide a replica circuit including the transimpedance amplifier TIAr, the circuit configuration of the semiconductor circuit 3 can be simplified as compared with the first and second embodiments.

The third embodiment described above is presented as an example, and is not intended to limit the scope of the invention. The third embodiment can be implemented in other various ways.

4. Fourth embodiment

The semiconductor circuit according to the fourth embodiment will be described below. Various circuits for testing the operation of the transimpedance amplifier TIA may be connected to the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA. Here, an example is shown in which a failure detection circuit that detects the presence or absence of a failure in the transimpedance amplifier TIA is connected to the negative input terminal of the operational amplifier OP. In the fourth embodiment, the description will be given mainly on the difference from the first embodiment. Other configurations and operations not described are the same as those of the first embodiment.

4.1 construction of semiconductor circuits

Fig. 8 is a circuit diagram showing a configuration of a semiconductor circuit according to the fourth embodiment. The semiconductor circuit 4 according to the fourth embodiment includes the failure detection circuit 41, and the switch circuits SW and SWr, in addition to the semiconductor circuit 1 described in the first embodiment. The semiconductor circuit 1 shown in fig. 8 is the same as the semiconductor circuit 1 shown in the first embodiment, and therefore, the description thereof is omitted.

As shown in fig. 8, the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA is connected to the failure detection circuit 41 via the switch circuit SW. The negative input terminal of the operational amplifier OPr in the transimpedance amplifier TIAr is connected to the failure detection circuit 41 via the switch circuit SWr.

The failure detection circuit 41 detects a voltage of the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA (hereinafter, referred to as a first detection voltage) and a voltage of the negative input terminal of the operational amplifier OPr in the transimpedance amplifier TIAr (hereinafter, referred to as a second detection voltage), and detects the presence or absence of a failure of the transimpedance amplifier TIA based on the detected first detection voltage and second detection voltage.

The failure detection circuit 41 has, for example, an analog-digital conversion circuit and a determination circuit. The analog-digital conversion circuit detects first and second detection voltages from the transimpedance amplifier TIA and the transimpedance amplifier TIAr, respectively, converts the first and second detection voltages into digital signals, respectively, and outputs first and second output signals. A decision circuit and a subsequent stage of the analog-to-digital conversion circuit. The determination circuit determines whether or not the transimpedance amplifier TIA is operating normally based on the first and second output signals output from the analog-digital conversion circuit, and outputs a determination result.

A switch circuit SW is connected between the negative input terminal of the operational amplifier OP and the failure detection circuit 41. The switch circuit SW sets the negative input terminal of the operational amplifier OP to a connection state (or a closed state, a conduction state) or an interruption state (or an open state, a disconnection state) with the failure detection circuit 41.

A switch circuit SWr is connected between the negative input terminal of the operational amplifier OPr and the failure detection circuit 41. The switch circuit SWr sets the negative input terminal of the operational amplifier OPr and the failure detection circuit 41 to a connection state or a disconnection state.

The switch circuit SWr has the same circuit configuration as the switch circuit SW. That is, the switch circuit SWr has the same circuit elements and circuit constants as the switch circuit SW. The switch circuits SW and SWr are each formed of, for example, a transistor (for example, a MOS field effect transistor).

There is a case where the switch circuits SW and SWr each generate the leakage current Iswa. As described above, the switch circuit SWr has the same circuit configuration as the switch circuit SW. Therefore, the leak currents Iswa generated in the switch circuits SW and SWr, respectively, are substantially the same, that is, have substantially the same current value.

4.2 operation of the semiconductor Circuit

The operation of the semiconductor circuit 4 according to the fourth embodiment will be described below.

When the semiconductor circuit 1 shown in fig. 8 operates and is used in a normal state, the switch circuits SW and SWr are set to an off state.

In the semiconductor circuit 4, a leakage current Iio occurs in the input/output portion IO in the measurement signal path, a leakage current Isw occurs in the variable resistance circuit VR, and a leakage current Iswa occurs in the switch circuit SW. If the leakage currents Iio, isw, and Iswa are generated, the current flowing in the variable resistance circuit VR decreases. Therefore, an error occurs in the effective resistance value of the variable resistance circuit VR due to the leakage currents Iio, isw, and Iswa.

On the other hand, in the input/output section IO, the variable resistance circuit VRr, and the switch circuit SWr in the replica circuit (or the error signal path), the leakage currents Iio, isw, and Iswa are generated in the same manner as in the input/output section IO, the variable resistance circuit VR, and the switch circuit SW in the measurement signal path.

Here, the input/output unit IOr, the variable resistance circuit VRr, and the switch circuit SWr in the replica circuit have the same circuit configuration as the input/output unit IO, the variable resistance circuit VR, and the switch circuit SW in the measurement signal path, respectively. For example, the circuit elements and circuit constants of the input/output unit IOr, the variable resistance circuit VRr, and the switch circuit SWr of the replica circuit are the same as those of the input/output unit IO, the variable resistance circuit VR, and the switch circuit SW of the measurement signal path. Therefore, the leak currents Iio, isw, and Iswa generated in the replica circuit are substantially the same as the leak currents Iio, isw, and Iswa generated in the measurement signal path, that is, substantially the same.

In this case, the output voltages VINP and VINN output from the operational amplifiers OP and OPr, respectively, are expressed by the following expressions.

VINP＝VB+RTIA·Isen-RTIA·(Iio+Isw+Iswa) (8)

VINN＝VB-RTIA·(Iio+Isw+Iswa) (9)

Thus, the output signal DOUT output from the differential input analog-digital conversion circuit 11 is represented by the following expression (10) (= expression (8) -expression (9)).

DOUT＝D(VINP-VINN)＝D(RTIA·Isen) (10)

Thus, an error in the effective resistance value of the variable resistance circuit VR due to the leakage currents Iio, isw, and Iswa can be removed, and an output signal DOUT generated based on the product of the resistance value RTIA and the sensor current Isen can be obtained.

On the other hand, when the semiconductor circuit 1 is operating and the test of the transimpedance amplifier TIA is performed, the switch circuits SW and SWr are set to the connected state. When the switch circuits SW and SWr are set to the connected state, leakage currents are generated from the switch circuits SW and SWr, respectively. Here, as described above, the switch circuit SWr has the same circuit configuration as the switch circuit SW. For example, the circuit elements of the switch circuit SWr and their circuit constants are the same as those of the switch circuit SW. Therefore, the leakage current Iswa generated in the switch circuit SWr is substantially the same as, i.e., substantially uniform to, the leakage current Iswa generated in the switch circuit SW.

The first detection voltage of the negative input terminal of the operational amplifier OP in the transimpedance amplifier TIA is input to the failure detection circuit 41 via the switch circuit SW, and the second detection voltage of the negative input terminal of the operational amplifier OPr in the transimpedance amplifier TIAr is input to the failure detection circuit 41 via the switch circuit SWr. The failure detection circuit 41 corrects the voltage value of the first detection voltage generated by the leakage current Iswa using the first detection voltage and the second detection voltage, and detects whether or not the transimpedance amplifier TIA has a failure based on the corrected first detection voltage.

4.3 Effect of the fourth embodiment

According to the semiconductor circuit 4 of the fourth embodiment, as in the first embodiment, a transimpedance amplifier capable of converting an input current into a voltage with high accuracy can be provided.

In the semiconductor circuit 4 according to the fourth embodiment, since the switch circuit SWr has the same circuit configuration as the switch circuit SW, the substantially same leakage current Iswa is generated in the switch circuit SW and the switch circuit SWr. In the fourth embodiment, the error of the first detection voltage generated by the leakage currents Iio, isw, and Iswa is corrected by the malfunction detection circuit 41 based on the first detection voltage of the input terminal of the transimpedance amplifier TIA and the second detection voltage of the input terminal of the transimpedance amplifier TIAr. Thus, in the fourth embodiment, based on the corrected first detection voltage, it is possible to accurately detect whether or not there is a failure in the transimpedance amplifier TIA.

The fourth embodiment described above is presented as an example, and is not intended to limit the scope of the invention. The fourth embodiment can be implemented in other various ways.

5. Other modifications and the like

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Claims (13)

1. A semiconductor circuit, comprising:

a first transimpedance amplifier having a first input terminal to which a reference voltage is supplied, a second input terminal to which an input current is supplied, and a first output terminal from which the first output voltage is output, the first transimpedance amplifier converting the input current into a first output voltage; and

and a second transimpedance amplifier having a third input terminal to which the reference voltage is supplied, a fourth input terminal, and a second output terminal, and having the same circuit configuration as the first transimpedance amplifier, and outputting a second output voltage from the second output terminal.

2. The semiconductor circuit according to claim 1, further comprising:

a first ESD protection circuit connected to the second input terminal of the first transimpedance amplifier; and

a second ESD protection circuit connected to the fourth input terminal of the second transimpedance amplifier and having the same circuit elements as the first ESD protection circuit,

the first transimpedance amplifier includes a first variable resistance circuit which is connected between the second input terminal and the first output terminal and which is configured to be variable in resistance value,

the second transimpedance amplifier includes a second variable resistance circuit which is connected between the fourth input terminal and the second output terminal, which is configured to have a variable resistance value, and which includes the same circuit elements as the first variable resistance circuit.

3. The semiconductor circuit of claim 2,

the first ESD protection circuit and the second ESD protection circuit both have a first circuit constant, and the first variable resistance circuit and the second variable resistance circuit both have a second circuit constant.

4. The semiconductor circuit of claim 2,

the first ESD protection circuit has a first diode and a second diode,

the first diode is connected between a ground voltage node to which a ground voltage is supplied and the second input terminal, the second diode is connected between the second input terminal and a power supply voltage node to which a power supply voltage is supplied,

the second ESD protection circuit has a third diode and a fourth diode,

the third diode is connected between the ground voltage node and the fourth input terminal, and the fourth diode is connected between the fourth input terminal and the power supply voltage node.

5. The semiconductor circuit of claim 2,

the first ESD protection circuit has a first transistor and a second transistor,

a gate and a drain of the first transistor are connected to a ground voltage node to which a ground voltage is supplied, a source of the first transistor is connected to the second input terminal,

a gate and a drain of the second transistor are connected to a power supply voltage node to which a power supply voltage is supplied, a source of the second transistor is connected to the second input terminal,

the second ESD protection circuit has a third transistor and a fourth transistor,

a gate and a drain of the third transistor are connected to the ground voltage node, a source of the third transistor is connected to the fourth input terminal,

a gate and a drain of the fourth transistor are connected to the power supply voltage node, and a source of the fourth transistor is connected to the fourth input terminal.

6. The semiconductor circuit of claim 2,

the first variable resistance circuit has a plurality of first resistors and a plurality of first transistors connected to the plurality of first resistors,

the second variable resistance circuit has a plurality of second resistors, and a plurality of second transistors connected to the plurality of second resistors.

7. The semiconductor circuit according to claim 1, further comprising:

and a differential input analog-digital conversion circuit that removes an in-phase signal component between the first output voltage and the second output voltage, and converts the voltage from which the in-phase signal component is removed into a digital value.

8. The semiconductor circuit according to claim 1, further comprising:

and a differential input amplifier circuit for removing in-phase signal components of the first output voltage and the second output voltage.

9. The semiconductor circuit according to claim 8, further comprising:

and an analog-to-digital conversion circuit for converting the voltage from which the in-phase signal component is removed into a digital value by the differential input amplification circuit.

10. The semiconductor circuit according to claim 1, further comprising:

a first circuit connected to the second input terminal of the first transimpedance amplifier; and

a second circuit connected to the fourth input terminal of the second transimpedance amplifier and having the same circuit elements as the first circuit.

11. The semiconductor circuit of claim 10,

the first circuit comprises a first switching circuit, the second circuit comprises a second switching circuit,

the first switch circuit and the second switch circuit each have a third circuit constant.

12. The semiconductor circuit according to claim 11, further comprising:

a detection circuit connected to the first switch circuit and the second switch circuit.

13. A semiconductor circuit, comprising:

a transimpedance amplifier having a first input terminal to which a reference voltage is supplied, a second input terminal to which a current is supplied, and an output terminal to which the current is converted into an output voltage and from which the output voltage is output;

a switching circuit configured to supply an input current to the second input terminal or to block the supply of the input current;

an analog-to-digital conversion circuit that converts the output voltage into a digital value and outputs a signal;

a storage circuit that stores the signal output from the analog-to-digital conversion circuit; and

a subtractor that subtracts the signal stored in the storage circuit from the signal output from the analog-to-digital conversion circuit,

the transimpedance amplifier outputs a first output voltage when the supply of the input current to the second input terminal is interrupted by the switch circuit, the analog-digital conversion circuit converts the first output voltage into a first signal, the memory circuit stores the first signal,

the transimpedance amplifier outputs a second output voltage when the input current is supplied to the second input terminal through the switching circuit, the analog-digital conversion circuit converts the second output voltage into a second signal, and the subtractor subtracts the first signal stored in the storage circuit from the second signal.

Images