CN115842011A - Package structure and method for manufacturing the same - Google Patents

Package structure and method for manufacturing the same Download PDF

Info

Publication number
CN115842011A
CN115842011A CN202211100193.9A CN202211100193A CN115842011A CN 115842011 A CN115842011 A CN 115842011A CN 202211100193 A CN202211100193 A CN 202211100193A CN 115842011 A CN115842011 A CN 115842011A
Authority
CN
China
Prior art keywords
semiconductor devices
package structure
semiconductor device
stack
common portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211100193.9A
Other languages
Chinese (zh)
Inventor
卢宗正
王彦武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202211100193.9A priority Critical patent/CN115842011A/en
Publication of CN115842011A publication Critical patent/CN115842011A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: a stack including a plurality of stacked semiconductor devices; the electrical connection parts are positioned on one side of the stacked component, each electrical connection part is electrically connected with the corresponding two semiconductor devices through a plurality of wires, and each wire is connected with one electrical connection part and at least two semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connection portion, and each of the connection portions is connected to a corresponding semiconductor device, respectively. At least the reflection problem and the problem of larger time delay caused by stub effect existing in the packaging structure can be solved.

Description

Package structure and method for manufacturing the same
Technical Field
The disclosed embodiments relate to the field of semiconductors, and in particular, to a package structure and a method for manufacturing the same.
Background
A package structure is a structure in which a semiconductor device is configured to be used as a part of an electronic product. In order to satisfy the demand for a miniaturized and highly integrated package structure, a concept of a package on package having a plurality of semiconductor devices stacked thereon is proposed, which can satisfy the demand for fast processing of large-capacity data while having a small footprint.
Generally, a package-on-package structure includes a substrate and a plurality of semiconductor devices stacked on the substrate, and the semiconductor devices are electrically connected to the substrate through a wire bonding process to electrically connect the semiconductor devices to circuits within the substrate, and then to transmit signals between the semiconductor devices and external circuits. For a package structure comprising a plurality of stacked semiconductor devices, the same electrical connection on the substrate may be connected to two semiconductor devices of different stack heights by two wires.
Disclosure of Invention
The embodiment of the disclosure provides a package structure and a manufacturing method thereof, which are at least beneficial to solving the problems of reflection and large time delay caused by stub effect in the package structure.
According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a package structure, including: a stack including a plurality of stacked semiconductor devices; a plurality of electrical connections located on one side of the stack, each electrical connection electrically connecting a respective two of the semiconductor devices; a plurality of wires, each of which connects one of the electrical connections and at least two of the semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connection portion, and each of the connection portions is connected to the corresponding semiconductor device, respectively.
According to other embodiments of the present disclosure, among at least two semiconductor devices connected to the same wire, the semiconductor device at the lowermost layer is defined as a lower layer semiconductor device; the connection point of the common portion and the connection portion is higher than the top surface of the lower semiconductor device.
According to still other embodiments of the present disclosure, a distance between a connection point of the common portion and the connection portion and a top surface of the lower semiconductor device is less than or equal to 70 μm.
According to other embodiments of the present disclosure, a line width of the common portion is the same as a line width of the connection portion for the same conductive line.
According to other embodiments of the present disclosure, the material of the common portion is the same as the material of the connection portion for the same wire.
According to other embodiments of the present disclosure, the substrate, the electrical connection portion, and the stack are located on a surface of the substrate.
According to still further embodiments of the present disclosure, the wire includes two of the connection portions; the included angle between the public portion and the surface of the substrate is a first included angle, the included angle between the two connecting portions is a second included angle, the second included angle is smaller than the first included angle, and the second included angle is smaller than 90 degrees.
According to other embodiments of the present disclosure, two of the semiconductor devices electrically connected to the same conductive line are in adjacent layers.
According to other embodiments of the present disclosure, at least one semiconductor device is further provided between two semiconductor devices electrically connected to the same wire.
According to other embodiments of the present disclosure, the stack is a vertical stack, and the side surfaces of the plurality of semiconductor devices are flush with each other.
According to other embodiments of the present disclosure, the stack is a staggered stack, and the sides of the plurality of semiconductor devices are staggered.
According to other embodiments of the present disclosure, the semiconductor device includes a chip, and the semiconductor device further includes a pad where the chip is exposed, and one end of the connection part is electrically connected to the pad.
According to some embodiments of the present disclosure, there is also provided in another aspect of the embodiments of the present disclosure a method for manufacturing a package structure, including: providing a stack including a plurality of stacked semiconductor devices; forming a plurality of electrical connection portions, wherein the electrical connection portions are positioned on one side of the stacked component, and each electrical connection portion is electrically connected with two corresponding semiconductor devices; forming a plurality of wires, each of which connects one of the electrical connections and at least two of the semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connection portion, and each of the connection portions is connected to the corresponding semiconductor device, respectively.
According to other embodiments of the present disclosure, the process of forming the conductive line includes: providing a mould, wherein the mould is provided with a hollow area corresponding to the shape of each wire; pouring a liquid conductive material into the hollow area and cooling to form the lead; and demolding the lead from the mold.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
in the technical solution of the package structure provided by the embodiment of the present disclosure, the stack includes a plurality of stacked semiconductor devices, a plurality of electrical connections are located on one side of the stack, and each electrical connection is electrically connected to two corresponding semiconductor devices (the two semiconductor devices are connected to different RANKs), and the stack has a plurality of wires, each wire connects one electrical connection and at least two semiconductor devices, wherein each wire includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connections, and each connection portion is connected to a corresponding semiconductor device. In this way, in the embodiment of the present disclosure, in two semiconductor devices to which the same electrical connection portion is connected, when one of the semiconductor devices operates, the other semiconductor device is in an empty state, and the connection portion connected to the semiconductor device in the empty state is a stub (stub). In the conventional package structure, the stub is a whole wire connecting the semiconductor device in an empty state and the electrical connection portion. The packaging structure provided by the embodiment of the disclosure shortens the length of the stub, thereby reducing the reflection of the stub to a lead connected with a semiconductor device in a working state and reducing the signal delay. In addition, two semiconductor devices in the package structure provided by the embodiment of the disclosure are connected with only one electrical connection portion, and two semiconductor devices in the common package structure are connected with two electrical connection portions or connected with one large electrical connection portion, so that the package structure provided by the embodiment of the disclosure can save the space of the substrate, and is beneficial to the miniaturization and miniaturization development of the package structure.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a cross-sectional view of a package structure;
FIG. 2 is a cross-sectional view of a stack in a package structure;
fig. 3 is a schematic cross-sectional view of a package structure according to an embodiment of the disclosure;
fig. 4 is a schematic cross-sectional view of a stack of a package structure according to an embodiment of the disclosure;
fig. 5 is another schematic cross-sectional view of a package structure provided in an embodiment of the disclosure;
fig. 6 is another schematic cross-sectional view of a package structure provided in an embodiment of the disclosure;
fig. 7 is a schematic diagram illustrating a step of forming a conductive line in a method of forming a package structure according to an embodiment of the disclosure.
Detailed Description
As can be seen from the background art, the prior art package structure has the problems of reflection caused by the stub effect existing in the package structure and large delay.
Referring to fig. 1 and 2, fig. 1 is a side view of a package structure, and fig. 2 is a side view of a stack in the package structure. The package structure includes: a stack 10, the stack 10 including a plurality of stacked semiconductor devices 11; a plurality of electrical connections 20, the electrical connections 20 being located on one side of the stack 10, and each electrical connection 20 being electrically connected to a respective two semiconductor devices 11; a plurality of wires 30, each wire 30 connecting one electrical connection 20 and one corresponding semiconductor device 11.
The package structure may further include: the substrate 40, the electrical connection portion 20 and the stack 10 are located on the surface of the substrate 40; an adhesive layer 12, the adhesive layer 12 being located between the adjacent semiconductor devices 11 for adhering the adjacent semiconductor devices 11; and a pad 50, one end of the wire 30 being electrically connected to the pad 50.
The semiconductor devices 11 arranged in the stack 10 in the direction toward the substrate 40 (i.e., arranged from top to bottom) may be referred to as rank0, rank1, respectively. Wherein, a semiconductor device 11 corresponding to rank0 and a semiconductor device 11 corresponding to rank1 are connected to the same electrical connection 20, and another semiconductor device 11 corresponding to rank0 and a semiconductor device 11 corresponding to rank1 are connected to another electrical connection 20.
During operation of the stack 10, only one of the two semiconductor devices 11 connected to the same electrical connection 20 is in operation, while the other semiconductor device 11 is in an empty state. In such a case that one semiconductor device 11 is operated and one semiconductor device 11 is vacant, the conductive line 30 connected to the vacant semiconductor device 11 becomes a stub (stub), which may generate a reflection action on the conductive line 30 connected to the semiconductor device 11 in an operating state, cause a signal delay, cause a stub effect (stub effect), and cause an error in the operating state of the corresponding semiconductor device 11, or cause a bit error in data transmitted by the semiconductor device 11 if the semiconductor device 11 is a memory, thereby causing a failure in a package structure. In addition, the strength of the stub effect is positively correlated with the length of the stub: the longer the stub length is, the stronger the reflection action of the stub on the wire 30 connected to the semiconductor device 11 in the working state is, the larger the signal delay caused by the stronger the stub effect is; the shorter the length of the stub, the weaker the reflection of the stub on the conductor 30 connected to the semiconductor device 11 in operation, the smaller the resulting signal delay and the weaker the stub effect.
Analysis shows that in the packaging structure, the stub is the whole lead connected between the electric connection part and the semiconductor device, the length of the lead is long, the produced stub effect is large, the reflection intensity is strong, and the caused signal time delay is large. If the length of the lead corresponding to the stub can be reduced, the above problem can be improved.
In the technical solution of the package structure provided by the embodiment of the present disclosure, a conductive line having a common portion and two connection portions is provided, wherein one end of the common portion is connected to the electrical connection portion, the other end of the common portion is connected to the two connection portions, and the other ends of the two connection portions are connected to different semiconductor devices. Therefore, in the packaging structure, when the stack works, the stub is a connecting part, and the length of the stub is shortened, so that the reflection generated by the stub is reduced, and the signal time delay is reduced. In addition, the number of the electric connection parts on the substrate can be reduced by providing the lead with the public part and the two connection parts, the space of the substrate is greatly saved, and the miniaturization development of a packaging structure is facilitated.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter may be practiced without these specific details or with various changes and modifications based on the following embodiments.
Fig. 3 is a schematic cross-sectional view of a package structure provided in an embodiment of the disclosure, and fig. 4 is a schematic cross-sectional view of a stack in fig. 3.
Referring to fig. 3 and 4, the package structure includes: a stack 100, the stack 100 including a plurality of stacked semiconductor devices 101; a plurality of electrical connections 102, wherein the electrical connections 102 are located on one side of the stack 100, and each electrical connection 102 is electrically connected to two corresponding semiconductor devices 101; a plurality of wires 103, each wire 103 connecting an electrical connection portion 102 and at least two semiconductor devices 101; wherein each of the wires 103 includes a common portion 113 and at least two connection portions 123 connected to one end of the common portion 113, the other end of the common portion 113 is connected to the electrical connection portion 102, and each of the connection portions 123 is connected to a corresponding one of the semiconductor devices 101, respectively.
In the above package structure, the wires 103 connecting the same electrical connection portion 102 to two different semiconductor devices 101 are provided as: including a structure of the common portion 113 having one end connected to the electrical connection portion 102 and a connection portion 123 connecting the other end of the common portion 113 and the two semiconductor devices 101. When one of the two semiconductor devices 101 connected to the same electrical connection portion 102 is in an operating state, the common portion 113 of the conductive wire 103 and the connection portion 123 connected to the semiconductor device 101 in the operating state are in the operating state, and the other connection portion 123 is in an empty state, and this connection portion 123 in the empty state serves as a stub at this time, and the stub may reflect the conductive wire 103 in the operating state, causing a signal delay. The stub in the embodiment provided by the disclosure has shorter length, weaker reflection and smaller signal time delay. Moreover, since the number of connection points of the wires on the substrate 104 is reduced, the package structure provided in the embodiment of the disclosure can also save the space of the substrate 104, which is beneficial to the miniaturization and miniaturization development of the package structure.
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.
The stack 100 may include a plurality of stacked semiconductor devices 101 therein, for example, the number of layers of the semiconductor devices 101 may be: 4, 6, 8, 10 layers, etc. The following description will be given by taking 4 layers as an example.
The semiconductor devices 101 may be wafers or chips, and the plurality of semiconductor devices 101 in the stack 100 may be the same kind of chips, for example, memory semiconductor chips. Each of the Memory semiconductor chips may be, for example, a volatile Memory semiconductor chip, which may be a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), and a Phase-Change Random Access Memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FeRAM), or a Resistive Random Access Memory (RRAM). The semiconductor device 101 may also be a flash memory, for example, a NAND (Nor AND) flash memory.
In addition, the plurality of semiconductor devices 101 in the stack 100 may also include different kinds of semiconductor chips. For example, some of the plurality of semiconductor devices 101 may be logic chips, and the other semiconductor chips may be memory chips. For example, each of the logic chips may be a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, or an Application Processor (AP) chip.
Fig. 3 is a schematic cross-sectional view of a package structure according to an embodiment of the disclosure, and referring to fig. 3, in some embodiments, the stack 100 may be a staggered stack, and the sides of the plurality of semiconductor devices 101 are staggered. This staggered stacking is advantageous in that it leaves sufficient space for the wires 103 connecting the semiconductor device 101 and the electrical connection portions 102, prevents the wires 103 from making unnecessary contact in the vicinity of the semiconductor device 101, and prevents the wires 103 from colliding with the semiconductor device 101.
In addition, in some embodiments, the semiconductor device 101 includes a chip, and the semiconductor device 101 further includes a pad 106 where the chip is exposed, and one end of the connection portion 123 of the wire 103 is connected to the pad 106. The pads 106 are used for electrical connection with circuits within the semiconductor device 101. The pad 106 may protrude from the surface of the semiconductor device 101, and the surface of the pad 106 may be flush with the surface of the semiconductor device 101. The pad 106 is generally provided on the edge surface of the semiconductor device 101.
The material of the pad 106 may include copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au), or a combination thereof. The position of the pad 106 may be located at one side edge of the semiconductor device 101 near the electrical connection portion 102.
Fig. 4 is a schematic cross-sectional structure of a stack of a package structure provided in an embodiment of the present disclosure, and referring to fig. 4, between a plurality of stacked semiconductor devices 101, an adhesive layer 105 may be further disposed, where the adhesive layer 105 is located between adjacent layers of the semiconductor devices 101 for adhering the adjacent semiconductor devices 101.
The adhesive layer 105 may be a Die Attach Film (DAF). In other embodiments, the adhesive layer 105 may not be provided, the semiconductor devices 101 of adjacent layers are in contact, and the stack 100 may be formed by electrostatic bonding or chemical bonding.
Fig. 5 is another schematic cross-sectional view of a package structure provided in an embodiment of the disclosure, and referring to fig. 5, in other embodiments, the stack 100 may be vertically stacked, and the side surfaces of the plurality of semiconductor devices 101 are flush with each other. The stacking mode can relatively reduce the size of the whole packaging structure, and is beneficial to the miniaturization and microminiaturization development of the packaging structure.
The semiconductor device 101 in the stack 100 may include two ranks 0 and two ranks 1. Among them, one semiconductor device 101 as rank0 and one semiconductor device 101 as rank1 are connected to the same electrical connection 102, and the other semiconductor device as rank0 and the other semiconductor device 101 as rank1 are connected to the other electrical connection 102.Rank refers to all memory cells connected to the same Chip Select (CS), the memory controller can perform read/write operations on all semiconductor devices 101 of the same Rank simultaneously, and the semiconductor devices 101 of the same Rank share the same control signal, the CS0 signal controls the semiconductor device 101 of Rank0 to operate, and the CS1 signal controls the semiconductor device 101 of Rank1 to operate. Therefore, only one of the two semiconductor devices 101 connected to the same electrical connection portion 102 is always in an operating state, and the other is in an idle state.
In some embodiments, the package structure may further include: the substrate 104, the electrical connections 102, and the stack 100 are located on a surface of the substrate 104. The substrate 104 may be a Printed Circuit Board (PCB), which may be a rigid PCB or a flexible PCB. In some embodiments, the electrical connections 102 may be electrically connected with circuitry within the substrate 104, such that the semiconductor device 101 is electrically connected with circuitry within the substrate 104 via the electrical connections 102. In other embodiments, the substrate 104 may also be a wafer carrier, the substrate 104 serves as a carrier for carrying the electrical connection portions 102 and the stack 100, and the substrate 104 may not be provided with a circuit.
In addition, the substrate 104 further includes: and solder balls 108. The material of the solder balls 108 may be tin.
Accordingly, the electrical connection portion 102 may be a conductive pillar or a gold finger, and the material of the electrical connection portion 102 may be at least one of copper (Cu), nickel (Ni), or gold (Au).
In addition, the package structure further includes a plurality of wires 103 having one common portion 113 and two connection portions 123.
The conducting wire 103 can convert two conducting wires connecting the same electrical connection part 102 and two semiconductor devices 101 into the same conducting wire 103, and the conducting wire 103 is connected with only one electrical connection part 102, so that the space of a packaging structure can be effectively saved. In addition, when one semiconductor device 101 is in an operating state, only the common portion 113 and one of the connection portions 123 connected to the semiconductor device 101 in the operating state are in the operating state, and the other connection portion 123 is in an empty state, and this connection portion 123 in the empty state serves as a stub which reflects the wire 103 in the operating state, causing a signal delay. Because the stub at this time is the connecting portion 123, and the length of the connecting portion 123 is much shorter than that of the stub in the conventional package structure, the reflection generated by the stub is small, the time delay of the signal caused by the reflection is also small, and the performance of the device can be effectively improved.
In some embodiments, of the at least two semiconductor devices 101 connected to the same wire 103, the semiconductor device 101 at the lowermost layer is defined as a lower layer semiconductor device, and a connection point of the common portion 113 and the connection portion 123 may be higher than a top surface of the lower layer semiconductor device 101. Such a height of the connection point enables both the connection portions 123 to be in a short state, and the other connection portion 123 as a stub does not have a large influence regardless of which connection portion 123 is in an operating state. In other embodiments, the connection point of the common portion 113 and the connection portion 123 may also be lower than the top surface of the upper semiconductor device 101, or the connection point of the common portion 113 and the connection portion 123 may also be lower than the top surface of the lower semiconductor device 101, or the connection point of the common portion 113 and the connection portion 123 may be flush with the top surface of the lower semiconductor device 101.
Specifically, in some embodiments, the connection point of the common portion 113 and the connection portion 123 may be higher than the top surface of the lower semiconductor device 101, and the distance between the connection point of the common portion 113 and the connection portion 123 and the top surface of the lower semiconductor device 101 may be less than or equal to 70 μm. Such a distance can reduce the length of the two connection portions 123 to the maximum, and reduce the influence of the stub on the performance of the semiconductor device.
It should be noted that, in fig. 3, the same wire 103 has two connection portions 123 and is electrically connected to two semiconductor devices 101, respectively, for example, in other embodiments, the same wire 103 may have three or more connection portions 123 and each connection portion 123 is electrically connected to a different semiconductor device 101.
In some embodiments, the line width of the common portion 113 and the line width of the connection portion 123 may be the same for the same conductive line 103. Because only one connecting part 123 and one common part 113 are in the working state at the same time, the common part 113 and one connecting part 123 are a complete conducting wire 103 in the working state, and the line width of the common part 113 and the line width of the connecting part 123 can be the same, so that the impedance can be reduced, and the signal reflection can be reduced. It is understood that in other embodiments, the line width of the common portion 113 may be larger than that of the connection portion 123, so as to reduce the power inductance and the power noise appropriately.
The common portion 113 and the connection portion 123 may be both circular wires, the line width of the common portion 123 refers to the diameter of the circular wire, and the line width of the connection portion 123 refers to the diameter of the circular wire. In other embodiments, the common portion 113 and the connection portion 123 may not be circular conductive lines, the line width of the common portion 113 refers to the area of the cross section of the common portion 113, and the line width of the connection portion 123 refers to the area of the cross section of the connection portion 123.
Further, in some embodiments, the material of the common portion 113 and the material of the connection portion 123 may be the same for the same wire 103, which can reduce signal attenuation caused by impedance. The common portion 113 and the connection portion 123 in the wire 103 may each be at least one of a silver alloy bonding wire, a copper wire, an aluminum wire, or a gold wire. In other embodiments, the material of the common portion 113 may also be different from the material of the connection portion 123 for the same wire 103, for example, the resistivity of the material of the common portion 113 is smaller than the resistivity of the material of the connection portion 123.
In some embodiments, the conductive line 103 includes two connection portions 123, an angle between the common portion 113 and the surface of the substrate 104 is a first angle, an angle between the two connection portions 123 is a second angle, and the second angle may be smaller than the first angle and may be smaller than 90 °. The included angle range can ensure that the length of the two connecting parts 123 is as small as possible while the electric signal can be normally and smoothly transmitted when the lead 103 works, and the influence of the stub on the performance of the device is reduced as much as possible.
Note that, the first angle here is an angle between a connection line of the electrical connection portion 102 and connection points of the common portion 113 and the connection portion 123 and the surface of the substrate 104. The second angle is an angle between a connection point of the common portion 113 and the connection portion 123 and a connection line of the pads 106 of the two semiconductor devices 101 to be connected.
Referring to fig. 5, in some embodiments, there is also at least one semiconductor device 101 between two semiconductor devices 101 electrically connected to the same wire 103. Since the same electrical signal, i.e., the same electrical connection portion 102, is connected to two semiconductor devices 101, one of the semiconductor devices 101 is rank0 and the other semiconductor device 101 is rank1. Therefore, the semiconductor device 101 may be arranged in a direction toward the electrical connection portion 102 (i.e., from top to bottom) in a manner of rank0, rank1. Or the semiconductor device 101 may be arranged in a direction toward the electrical connection portion 102 in a manner of rank1, rank0. The semiconductor devices 101 are arranged adjacently in a direction toward the electrical connection portion 102. The arrangement mode can increase the distance between the two connecting parts 123 in the wire 103, so that the wire 103 is not easy to collide with objects in the semiconductor device 101 or other packaging structures, and the product yield is increased.
Referring to fig. 6, in other embodiments, two semiconductor devices 101 electrically connected to the same conductive line 103 are in adjacent layers. Since one of the two semiconductor devices 101 connected to the same electrical connection portion 102 is rank0, the other semiconductor device 101 is rank1. Therefore, the semiconductor device 101 may be arranged in rank0, rank1, rank0, rank1 in a direction toward the electrical connection portion 102 (i.e., from top to bottom). Or the semiconductor device 101 may be arranged in a manner of rank1, rank0, rank1, rank0 in a direction toward the electrical connection portion 102. The semiconductor devices 101 are arranged in a staggered manner in a direction toward the electrical connection portions 102.
In the technical solution of the package structure provided by the embodiment of the present disclosure, a conductive line having a common portion and two connection portions is provided, wherein one end of the common portion is connected to the electrical connection portion, the other end of the common portion is connected to the two connection portions, and the other ends of the two connection portions are connected to different semiconductor devices. Therefore, in the packaging structure, when the stack works, the stub is a connecting part, and the length of the stub is shortened, so that the reflection generated by the stub is reduced, and the signal time delay is reduced. In addition, the number of the electric connection parts on the substrate can be reduced by providing the lead with the public part and the two connection parts, the space of the substrate is greatly saved, and the miniaturization development of a packaging structure is facilitated.
Another embodiment of the present disclosure further provides a manufacturing method of a package structure, which can be used to form the package structure. A semiconductor structure provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings, and the same or corresponding portions as or to the previous embodiment can be referred to the corresponding descriptions of the previous embodiment, which will not be described in detail below.
Referring to fig. 3 to 6, a stack 100 is provided, the stack 100 including a plurality of stacked semiconductor devices 101; forming a plurality of electrical connections 102, the electrical connections 102 being located on one side of the stack 100, and each electrical connection 102 being electrically connected to a respective two semiconductor devices 101; forming a plurality of wires 103, each wire 103 connecting an electrical connection portion 102 and at least two semiconductor devices 101; wherein each of the wires 103 includes a common portion 113 and at least two connection portions 123 connected to one end of the common portion 113, the other end of the common portion 113 being connected to the electrical connection portion 102, each connection portion being connected to a corresponding one of the semiconductor devices 101, respectively.
In some embodiments, a substrate 104 may also be provided in the package structure, and the electrical connection portion 102 and the stack 100 are disposed on the substrate 104.
Referring to fig. 7, in some embodiments, the process steps for forming the conductive line 103 include: providing a mold 107, wherein the mold 107 is provided with a hollow area 117 corresponding to the shape of each conducting wire 103; pouring a liquid conductive material into the hollow area 117 and performing a cooling process to form the wire 103; the wire 103 is released from the mold 107. The lead 103 has the common portion 113 and two connecting portions 123 connected to one end of the common portion 113, and the common portion 113 and the connecting portions 123 of the lead 103 have the same line width and the same material, so that the desired lead 103 is obtained by integrally molding by means of mold casting. The mode of forming the integrated wire 103 by pouring the model 107 can ensure that the wire width of each part of the wire 103 is uniform and the material is consistent, can improve the stability of the semiconductor device 101, and is beneficial to large-scale production and production efficiency.
The liquid conductive material may include at least one of silver alloy, copper, aluminum, or gold.
In addition, between the plurality of stacked semiconductor devices 101, an adhesive layer 105 may be further included, the adhesive layer 105 being positioned between the adjacent semiconductor devices 101 for adhering the adjacent semiconductor devices 101.
The adhesive layer 105 may be a Die Attach Film (DAF). In other embodiments, the adhesive layer 105 may not be provided, the semiconductor devices 101 of adjacent layers are in contact, and the stack 100 may be formed by electrostatic bonding or chemical bonding.
Tie layer 105 can include first tie layer, the second tie layer, the active surface contact of first tie layer and chip, the back contact of second tie layer and another chip, the elastic film modulus of first tie layer is greater than the elastic modulus of second tie layer, and the active surface can produce more heats, and the elastic modulus of first tie layer is great, and the deformation of first tie layer also can be less, can guarantee the bonding effect like this.
In the technical solution of the manufacturing method of the package structure provided by the embodiment of the present disclosure, a method for manufacturing a wire having a common portion and two connection portions is provided, wherein one end of the common portion is connected to the electrical connection portion, the other end of the common portion is connected to the two connection portions, and the other ends of the two connection portions are connected to different semiconductor devices. The wire is manufactured in a mode of pouring the model, so that the uniform line width and consistent materials of all the parts of the wire 103 can be ensured, the stability of the semiconductor device 101 can be improved, the large-scale production is facilitated, and the production efficiency is improved. And the reflection generated by the stub can be reduced, and the signal time delay is reduced. In addition, the space of the substrate can be greatly saved, and the miniaturization development of the packaging structure are facilitated.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the disclosure, and it is intended that the scope of the disclosure be limited only by the claims appended hereto.

Claims (14)

1. A package structure, comprising:
a stack including a plurality of stacked semiconductor devices;
a plurality of electrical connections located on one side of the stack, each electrical connection electrically connecting a respective two of the semiconductor devices;
a plurality of wires, each of which connects one of the electrical connections and at least two of the semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connection portion, and each of the connection portions is connected to the corresponding semiconductor device, respectively.
2. The package structure according to claim 1, wherein, of at least two of the semiconductor devices connected to the same wire, the semiconductor device at a lowermost layer is defined as a lower layer semiconductor device; the connection point of the common portion and the connection portion is higher than the top surface of the lower semiconductor device.
3. The package structure of claim 2, wherein a distance between a connection point of the common portion and the connection portion and a top surface of the lower semiconductor device is less than or equal to 70 μm.
4. The package structure of claim 1, wherein a line width of the common portion is the same as a line width of the connection portion for the same wire.
5. The package structure of claim 1, wherein the common portion is made of the same material as the connection portion for the same wire.
6. The package structure of claim 1, further comprising: the substrate, the electrical connection portion and the stack are located on the surface of the substrate.
7. The package structure of claim 6, wherein the wire comprises two of the connection portions; the included angle between the public portion and the surface of the substrate is a first included angle, the included angle between the two connecting portions is a second included angle, the second included angle is smaller than the first included angle, and the second included angle is smaller than 90 degrees.
8. The package structure of claim 1, wherein two of the semiconductor devices electrically connected to the same wire are in adjacent layers.
9. The package structure of claim 1, wherein there is also at least one of the semiconductor devices between two of the semiconductor devices electrically connected to the same wire.
10. The package structure of claim 1, wherein the stack is a vertical stack, and sides of the plurality of semiconductor devices are flush with each other.
11. The package structure of claim 1, wherein the stack is a staggered stack, and sides of the plurality of semiconductor devices are staggered with respect to each other.
12. The package structure according to claim 1, wherein the semiconductor device includes a chip, and the semiconductor device further includes a pad where the chip is exposed, one end of the connection portion being electrically connected to the pad.
13. A method of manufacturing a package structure, comprising:
providing a stack including a plurality of stacked semiconductor devices;
forming a plurality of electrical connections, wherein the electrical connections are positioned on one side of the stack and each electrical connection is electrically connected with two corresponding semiconductor devices;
forming a plurality of wires, each of which connects one of the electrical connections and at least two of the semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connection portion, and each of the connection portions is connected to the corresponding semiconductor device, respectively.
14. The method of manufacturing of claim 13, wherein the process step of forming the conductive line comprises: providing a mould, wherein the mould is provided with a hollow area corresponding to the shape of each wire; pouring a liquid conductive material into the hollow area and cooling to form the lead; and demolding the lead from the mold.
CN202211100193.9A 2022-09-07 2022-09-07 Package structure and method for manufacturing the same Pending CN115842011A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211100193.9A CN115842011A (en) 2022-09-07 2022-09-07 Package structure and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211100193.9A CN115842011A (en) 2022-09-07 2022-09-07 Package structure and method for manufacturing the same

Publications (1)

Publication Number Publication Date
CN115842011A true CN115842011A (en) 2023-03-24

Family

ID=85574889

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211100193.9A Pending CN115842011A (en) 2022-09-07 2022-09-07 Package structure and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN115842011A (en)

Similar Documents

Publication Publication Date Title
KR101623880B1 (en) Semiconductor package
US10211159B2 (en) Semiconductor packages having semiconductor chips disposed in opening in shielding core plate
KR100753415B1 (en) Stack package
US8338929B2 (en) Stacked-type chip package structure and fabrication method thereof
US8021928B1 (en) System and method for routing supply voltages or other signals between side-by-side die and a lead frame for system in a package (SIP) devices
US20150270242A1 (en) Semiconductor packages and methods of fabricating the same
TWI599009B (en) Semiconductor chip package, semiconductor module, method of fabricating the semiconductor chip package and method of fabricating the semiconductor module
US8933561B2 (en) Semiconductor device for semiconductor package having through silicon vias of different heights
US20190295917A1 (en) Semiconductor package
US11569145B2 (en) Semiconductor package with thermal interface material for improving package reliability
CN107293520B (en) Stacked semiconductor package
US11626380B2 (en) Semiconductor package
US11637089B2 (en) Semiconductor package including stacked semiconductor chips
US11791303B2 (en) Semiconductor package including semiconductor chips
CN115842011A (en) Package structure and method for manufacturing the same
US11217503B2 (en) Semiconductor package having logic semiconductor chip and memory packages on interposer
CN101465341B (en) Stacked chip packaging structure
TW202145495A (en) Semiconductor package including capacitor
CN105575942A (en) Interposer substrate and method of manufacturing the same
US20240047437A1 (en) Package structure and method for fabricating same
US20220059503A1 (en) Semiconductor package including vertical interconnector
CN218827104U (en) Chip packaging structure with short wiring length
KR20080029273A (en) Stack package and hi-density multi package using the same
US9966364B2 (en) Semiconductor package and method for fabricating the same
US20240178193A1 (en) Semiconductor packages with pass-through clock traces and associated systems and methods

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination