CN115840125A - System and method for testing backboard of nonvolatile memory storage device - Google Patents
System and method for testing backboard of nonvolatile memory storage device Download PDFInfo
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- CN115840125A CN115840125A CN202111097083.7A CN202111097083A CN115840125A CN 115840125 A CN115840125 A CN 115840125A CN 202111097083 A CN202111097083 A CN 202111097083A CN 115840125 A CN115840125 A CN 115840125A
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Abstract
The invention discloses a system and a method for testing a backboard of a nonvolatile memory storage device, wherein a test control device generates a first signal and transmits the first signal to an analog device through a tested circuit board (the backboard of the nonvolatile memory storage device), a signal processing element in the analog device receives the first signal and generates a second signal which is the same as the first signal, and the signal processing element transmits the second signal to the test control device through the tested circuit board, so that the test control device can judge the bit error rate of the second signal.
Description
Technical Field
The present invention relates to a test system and method thereof, and more particularly, to a system and method for testing a backplane of a nonvolatile memory storage device.
Background
Industrial 4.0 (Industry 4.0), also known as the fourth industrial revolution, is not a new industrial technology created alone, but focuses on integrating the existing industrial technology, sales process and product experience, building an intelligent factory with adaptability, resource efficiency and human factors engineering through artificial intelligence technology, and integrating customers and business partners in the business process and value process to provide perfect after-sales services, thereby constructing a new intelligent industrial world with awareness.
With the 4.0 industrial wave striking the world, manufacturers have no intelligent manufacturing optimization production transformation, and the competitiveness is improved. The intelligent manufacturing is based on sensing technology, network technology, automation technology and artificial intelligence, and realizes the intellectualization of product design and manufacturing, enterprise management and service through the processes of perception, man-machine interaction, decision, execution and feedback.
The electronic assembly industry is thin and profitable, and the price competition of products is strong, so that the manufacturers pursue more effective control and optimization on raw materials and production tools, and the production resource benefit of factories is maximized. In the production line of the electronic assembly industry, various circuit board testing links are necessarily included, and the circuit board testing for connecting a plurality of high-speed storage media is also included.
At present, there are two main ways for testing a circuit board connected with a plurality of high-speed storage media, one is to connect the circuit board with a real high-speed storage medium and perform actual testing, and the other is to perform signal loopback testing on the circuit board by using a loopback apparatus with a loopback (loopback) circuit. The first of these is the most primitive, with the disadvantage of higher costs; the second method can greatly reduce the cost under the condition of a certain test coverage, however, as the circuit board gradually needs to support the specification of PCIe Gen4/Gen5, the frequency of the signals transmitted on the circuit board is increased, but the architecture of the second method using the loopback device cannot perform high-frequency test on the circuit board at present.
More specifically, in the specification of Gen4/Gen5, because the loss requirement for signals becomes high, the signal strength is mostly adjusted by the trace length of the working circuit in the current circuit board during the circuit board design, so that the signals passing through the working circuit of the circuit board can all reach the specification of Gen4/Gen 5. Thus, when the second mode is used for testing the high-frequency signal of the circuit board, the high-frequency signal can directly pass through the loopback circuit and is sent back to the circuit board by the loopback device when entering the loopback device, so that the high-frequency signal can make a round trip in the working circuit of the circuit board to cause the circuit length passed by the high-frequency signal to be doubled, the loss of the high-frequency signal is increased, the high-frequency signal sent to the circuit board again through the loopback device cannot be correctly identified, the high-frequency signal testing on the circuit board cannot be finished, and the testing coverage rate of the circuit board is reduced.
In summary, it is known that the prior art has a problem that a high frequency signal cannot be tested on a circuit board by using a loopback apparatus for a long time, and therefore, an improved technical means is needed to solve the problem.
Disclosure of Invention
In view of the problem of the prior art that the high frequency signal cannot be tested on the circuit board by using the loopback device, the present invention discloses a system and a method for testing the backplane of the nonvolatile memory storage device, wherein:
the invention discloses a system for testing a backboard of a nonvolatile memory storage device, which at least comprises: a circuit board to be tested; the test control device is used for providing connection of a tested circuit board, generating a first signal and transmitting the first signal to the tested circuit board so that the first signal passes through the tested circuit board; the analog device is connected with the circuit board to be tested and comprises a signal processing element, wherein the signal processing element is used for receiving a first signal passing through the circuit board to be tested and generating a second signal which is the same as the first signal, and transmitting the second signal to the circuit board to be tested, so that the second signal is transmitted to the test control device through the circuit board to be tested, and the test control device is further used for receiving the second signal and judging the Bit Error Rate (BER) of the second signal so as to generate a test result of the circuit board to be tested.
The invention discloses a method for testing a backboard of a nonvolatile memory storage device, which at least comprises the following steps: connecting the test control device with the tested circuit board and connecting the tested circuit board with the simulation device, wherein the simulation device comprises a signal processing element; the test control device generates a first signal and transmits the first signal to the tested circuit board, so that the first signal is transmitted to the simulation device through the tested circuit board; the signal processing element receives the first signal and generates a second signal which is the same as the first signal; the signal processing element transmits a second signal to the circuit board to be tested, so that the second signal is transmitted to the test control device through the circuit board to be tested; the test control device receives the second signal and judges the bit error rate of the second signal to generate a test result of the tested circuit board.
The system and the method disclosed by the invention have the difference from the prior art that the test control device generates a first signal and transmits the first signal to the simulation device through the tested circuit board, the signal processing element in the simulation device receives the first signal and generates a second signal which is the same as the first signal, and the signal processing element transmits the second signal to the test control device through the tested circuit board, so that the test control device judges the bit error rate of the second signal, the problems in the prior art are solved, and the technical effect of improving the test coverage rate is achieved.
Drawings
FIG. 1 is a block diagram of a system for testing a backplane of a non-volatile memory storage device according to the present invention.
FIG. 2A is a flowchart of a method for testing a backplane of a non-volatile memory storage device according to the present invention.
Fig. 2B is a flowchart of a method for testing on/off of a pin according to the present invention.
Description of reference numerals:
110. circuit board to be tested
112. Connecting interface
113. Connecting interface
120. Simulation device
121. Signal processing element
123. Connecting interface
130. Test control device
131. Signal generating element
132. Connecting interface
Detailed Description
The features and embodiments of the present invention will be described in detail with reference to the drawings and examples, which are sufficient for those skilled in the art to easily understand the technical means applied to solve the technical problems and to implement the technical means, thereby achieving the effects achieved by the present invention.
The invention can replace the loopback device in the prior art with an analog device, and use the analog device to complete the test of the circuit board to be tested, wherein the circuit board to be tested is usually a nonvolatile Memory storage device (NVMe), and besides, the test of the circuit board to be tested can also comprise the test of high frequency signals besides all tests which can be carried out by the loopback device.
The operation of the system of the present invention will be described with reference to FIG. 1, which is a block diagram of a system for testing a backplane of a non-volatile memory storage device. As shown in FIG. 1, the system of the present invention comprises a circuit board 110 under test, an analog device 120, and a test control device 130.
The circuit board under test 110 may be connected to the test control device 130, and may also be connected to the simulation device 120. In more detail, the circuit board 110 under test may be connected to the test control device 130 through the connection interface 112, and the circuit board 110 under test may also be connected to the simulation device 120 through the connection interface 113.
The circuit board under test 110 contains the working circuit to be tested (not shown). Through the operating circuit, electrical signals may be passed between the test control device 130 and the simulation device 120. It is noted that the electrical signal may generate noise and/or reduce the signal strength during the transmission on the working circuit, therefore, the working circuit needs to be designed to take into account the loss of the electrical signal, so that the electrical signal is still maintained at a strength that can be correctly recognized when the electrical signal is transmitted from the test control device 130 to the simulation device 120 or from the simulation device 120 to the test control device 130, and in most embodiments, the electrical signal is usually just in line with or slightly above the minimum strength of the specification when the electrical signal is transmitted from the test control device 130 to the simulation device 120 or from the simulation device 120 to the test control device 130, considering the cost.
The analog device 120 may be connected to the circuit board under test 110, and the analog device 120 includes a signal processing element 121. In more detail, the simulation apparatus 120 includes a connection circuit (not shown) that can connect the signal processing element 121 and the connection interface 123, so that the electrical signal passing through the circuit board under test 110 can reach the signal processing element 121 from the connection interface 113 through the connection circuit.
The signal processing element 121 is responsible for receiving a first signal passing through the circuit board under test 110 and for generating a second signal identical to the received first signal. The signal processing element 121 may increase the intensity of the first signal to generate the second signal or regenerate the second signal having the same waveform according to the waveform of the first signal, but the manner of generating the second signal by the signal processing element 121 is not limited thereto.
The signal processing component 121 is also responsible for transmitting the generated second signal to the circuit board under test 130, so that the second signal is transmitted to the test control device 130 through the circuit board under test 110. In more detail, the second signal may be transmitted to the connection interface 113 of the circuit board under test 110 through the connection circuit and connection interface 123, and may reach the test control apparatus 130 through the working circuit and connection interface 112 of the circuit board under test 110.
The signal processing element 121 may also send back the received first signal or the generated second signal to itself in a loopback circuit, i.e. send back the first signal or the second signal to the signal processing element 121. Generally, the length of the loopback circuit is similar to that of the loopback circuit in the prior art, but the invention is not limited thereto.
The simulation apparatus 120 may also be connected to the test control apparatus 130, and the simulation apparatus 120 may also receive a control signal generated by the test control apparatus 130. For example, the analog device 120 may be connected to the test control device 130 through a JTAG interface (not shown in the figure), and the JTAG interface is connected to the signal processing element 121 through a connection circuit, so that the signal processing element 121 can obtain the control signal generated by the test control device 130, wherein the control signal includes a reception control signal and a transmission control signal.
In more detail, the signal processing element 121 may also receive a reception control signal generated by the test control apparatus 130 through the JTAG interface, and may receive a third signal passing through the circuit board 110 under test according to the received reception control signal; the signal processing unit 121 may also receive a transmission control signal generated by the test control apparatus 130 through the JTAG interface, and may transmit a generated fourth signal to the circuit board under test 130, so that the fourth signal is transmitted to the test control apparatus 130 through the circuit board under test 110.
The test control device 130 provides the circuit board under test 110 with a connection, and is responsible for generating and transmitting a first signal to the circuit board under test 110, so that the first signal passes through the circuit board under test 110. In more detail, the test control apparatus 130 may be connected to the circuit board 110 under test through the connection interface 132, and may transmit the generated first signal to the circuit board 110 under test through the connection interface 132.
The test control device 130 may include a signal generating element 131, and the signal generating element 131 may generate a first signal, generally, the first signal generated by the signal generating element 131 is a differential signal. For example, the signal generating element 131 may be a SAS controller or a PCIe controller, but the invention is not limited thereto. In some embodiments, the signal generating element 131 may also include a clock detection logic circuit.
The test control device 130 is also responsible for receiving the second signal generated by the analog device 120 and determining a Bit Error Rate (BER) of the second signal at the corresponding characteristic frequency to generate a test result of the circuit board under test 110.
In some embodiments, the test control device 130 is not limited to determine only the bit error rate, and the test control device 130 may select a corresponding test mode according to the executed test program, and may generate a corresponding test result according to the test signal transmitted to the simulation device 120 and the response signal returned by the simulation device 120, and generate a test result including various test results. For example, the test control device 130 may also determine the on-off status of each pin connected between the circuit board under test 110 and the test control device 130, and generate a corresponding detection result according to the determined on-off status of each pin, that is, the test result generated by the test control device 130 may include a bit error rate, and a detection result indicating whether each pin connected between the circuit board under test 110 and the test control device 130 is actually connected.
More specifically, the test control device 130 may be connected to the analog device 120 through a JTAG interface, and may transmit the generated control signal to the analog device 120 through the JTAG interface, meanwhile, the test control device 130 may also generate a third signal, and may transmit the generated third signal to the circuit board under test 110, so that the third signal reaches the analog device 120 through the circuit board under test 110, and the test control device 130 may also receive the generated fourth signal, and may determine, according to the received fourth signal, the on-off status of each pin connecting the circuit board under test 110 and the test control device 130 to generate a corresponding detection result.
Next, an embodiment of a system and a method for testing a backplane of a non-volatile memory storage device is described with reference to fig. 2A.
First, the tester can connect the test control apparatus 130 with the circuit board 110 under test and connect the circuit board 110 under test with the simulation apparatus 120 (step 211). In the embodiment, it is assumed that the test control device 130 and the circuit board 110 under test can be connected to the connection interface 112 of the circuit board 110 under test through the connection interface 132 of the test control device 130, and the circuit board 110 under test and the simulation device 120 can be plugged into the connection interface 113 of the circuit board 110 under test through the simulation device 120.
After connecting the test control device 130 with the circuit board 110 under test and connecting the circuit board 110 under test with the simulation device 120 (step 211), the test control device 130 may generate a first signal and may transmit the first signal to the simulation device 120 through the circuit board 110 under test, that is, transmit the generated first signal to the circuit board 110 under test, so that the first signal is transmitted to the simulation device 120 through the circuit board 110 under test (step 230). In this embodiment, it is assumed that the test control apparatus 130 includes a signal generating element 131, the signal generating element 131 can generate a PRBS test sequence (a first signal) with a high-frequency differential signal after the tester starts the test control apparatus 130, and can transmit the first signal through the connection interface 132 of the test control apparatus 130, so that the first signal sequentially reaches the simulation apparatus 120 through the connection interface 132, the connection interface 112 of the circuit board under test 110, the working circuit and the connection interface 113.
After the first signal generated by the test control device 130 reaches the simulation device 120, the signal processing component 121 of the simulation device 120 may receive the first signal and may generate a second signal identical to the received first signal (step 250). In the present embodiment, it is assumed that the signal processing element 121 may receive a first signal arriving at the analog device 120 through a connection circuit of the analog device 120, and may enhance the signal strength of the received first signal to generate a second signal, regenerate (driver) the same second signal as the first signal, or reconstruct (timer) the first signal through a clock check (clock checker) signal to generate the second signal.
In practice, the signal processing component 121 of the analog device 120 may transmit the first signal to a loopback circuit connected to the signal processing component 121 on the analog device 120 after receiving the first signal and before generating the second signal, so that the first signal is looped back to itself (the signal processing component 121), or transmit the second signal to the loopback circuit after generating the second signal, so that the second signal is looped back to itself.
After the signal processing element 121 of the simulation apparatus 120 generates the second signal, the signal processing element 121 may transmit the generated second signal to the test control apparatus 130 through the circuit board under test 110, that is, transmit the generated second signal to the circuit board under test 110, so that the second signal is transmitted to the test control apparatus 130 through the circuit board under test 110 (step 260). In this embodiment, it is assumed that the signal processing component 121 can transmit the second signal to the connection interface 123 through the connection circuit of the simulation apparatus 120, so that the second signal sequentially passes through the connection interface 123, the connection interface 113 of the circuit board under test 110, and the working circuit and the connection interface 112 to reach the test control apparatus 130.
After the second signal generated by the signal processing component 121 of the simulation apparatus 120 reaches the test control apparatus 130, the test control apparatus 130 may receive the second signal and determine the bit error rate of the received second signal, thereby generating a test result corresponding to the circuit board under test 110 (step 270). In this embodiment, it is assumed that the test control device 130 can compare the data represented by the received second signal with the data corresponding to the transmitted first signal, determine the bit error rate of the second signal according to the comparison result, and generate the test result including the determined bit error rate.
Thus, the analog device 130 of the present invention can test the high-frequency differential signal on the circuit board 120 under test, which cannot be performed by the prior art using the loopback device.
In the above embodiment, after the test control apparatus 130 and the circuit board 110 under test are connected and the circuit board 110 under test and the simulation apparatus 120 are connected (step 211), before the signal processing component 121 of the simulation apparatus 120 receives the first signal and generates the second signal (step 250) identical to the received first signal, as shown in the flow chart of fig. 2B, the test control apparatus 130 and the simulation apparatus 120 may be connected (step 215), for example, the JTAG connection interface of the test control apparatus 130 and the simulation apparatus 120 is connected through a flat cable.
After connecting the test control device 130 and the simulation device 120 (step 215), the test control device 130 may execute a corresponding test program according to the current test stage, and select a corresponding test type according to the executed test program (step 221), when the test type is represented by high frequency transmission detection (PRBS mode), the test control device 130 may determine a bit error rate of the PRBS test sequence generated according to the above process (steps 211 to 270), and when the test mode is represented by pin on-off detection (1149.6 mode), the test control device 130 may generate a reception control signal first, and may transmit the generated reception control signal to the simulation device 120 through the JTAG connection interface, and may transmit a third signal for testing a specific pin to the circuit board under test 110 through the connection interface 132, so that the third signal reaches the simulation device 120 through the circuit board under test 110, and the signal processing element 121 of the simulation device 120 may receive the third signal passing through the circuit board under test 110 according to the received reception control signal (step 223).
After the signal processing element 121 of the analog device 120 receives the third signal, a corresponding fourth signal may be generated according to the received third signal (step 225), and then the test control device 130 may continue to generate the transmission control signal and may transmit the generated transmission control signal to the analog device 120 through the JTAG connection interface, and after receiving the transmission control signal generated by the test control device 130 through the JTAG connection interface, the signal processing element 121 of the analog device 120 may generate a fourth signal associated with the third signal according to the received transmission control signal and may transmit the generated fourth signal to the circuit board 110 through the connection interface 123, so that the fourth signal reaches the test control device 130 through the circuit board 110, or may transmit the fourth signal to the test control device 130 through the JTAG connection interface (step 227).
The test control device 130 may generate a test result corresponding to the tested pin according to the received fourth signal after receiving the fourth signal. The test control device 130 may repeat the above process until all the pins are sent out corresponding third signals and the on/off detection results corresponding to the pins are generated (step 229), so that when the test control device 130 generates the test results corresponding to the circuit board under test 110 (step 270), the test control device 130 may generate the test results including the on/off detection results and the bit error rate.
In summary, it can be seen that the difference between the present invention and the prior art is that the test control device generates a first signal and transmits the first signal to the analog device through the tested circuit board, the signal processing device in the analog device receives the first signal and generates a second signal identical to the first signal, and the signal processing device transmits the second signal to the test control device through the tested circuit board, so that the test control device determines the bit error rate of the second signal.
In addition, the method of the present invention for generating the same signal to test the circuit board using the analog device can be realized in hardware, software, or a combination of hardware and software, and can also be realized in a centralized manner in a computer system or in a distributed manner in which different elements are distributed among several interconnected computer systems.
Although the embodiments of the present invention have been disclosed, the disclosure is not intended to limit the scope of the invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is defined by the appended claims.
Claims (10)
1. A method for testing a backplane of a non-volatile memory storage device, the method comprising:
connecting a test control device with a tested circuit board and connecting the tested circuit board with an analog device, wherein the analog device comprises a signal processing element, and the tested circuit board is a back plate of a nonvolatile memory storage device;
the test control device generates a first signal and transmits the first signal to the circuit board to be tested, so that the first signal is transmitted to the simulation device through the circuit board to be tested;
the signal processing element receives the first signal and generates a second signal which is the same as the first signal;
the signal processing element transmits the second signal to the circuit board to be tested, so that the second signal is transmitted to the test control device through the circuit board to be tested; and
the test control device receives the second signal and judges the bit error rate of the second signal to generate a test result of the tested circuit board.
2. The method of claim 1, wherein the step of the signal processing component generating the second signal identical to the first signal further comprises the step of the signal processing component sending the first signal or the second signal back to the signal processing component.
3. The method as claimed in claim 1, further comprising the steps of connecting the test control device and the simulation device, the test control device transmitting a reception control signal to the signal processing element and transmitting a third signal to the signal processing element through the circuit board under test, so that the signal processing element receives the third signal according to the reception control signal, and the test control device transmitting a transmission control signal to the signal processing element, so that the signal processing element transmits a fourth signal to the test control device through the circuit board under test according to the transmission control signal, and the test control device generating the on/off detection results of all the pins connected to the test control device through the circuit board under test according to the fourth signal.
4. The method of claim 1, wherein the step of the test control device generating the first signal generates the first signal of a differential signal for a signal generating element included in the test control device.
5. The method as claimed in claim 1, wherein the step of the test control device generating the test result of the circuit board under test further comprises the steps of the test control device selecting a test mode, generating a corresponding test signal according to the test mode and transmitting the test signal to the analog device, and generating the test result according to a response signal generated by the analog device.
6. A system for testing a backplane of a non-volatile memory storage device, the system comprising:
the circuit board to be tested is a nonvolatile memory storage device backboard;
the test control device is used for providing the connection of the circuit board to be tested, generating a first signal and transmitting the first signal to the circuit board to be tested so that the first signal passes through the circuit board to be tested; and
the analog device is connected with the circuit board to be tested and comprises a signal processing element, wherein the signal processing element is used for receiving the first signal passing through the circuit board to be tested and generating a second signal which is the same as the first signal, and transmitting the second signal to the circuit board to be tested, so that the second signal is transmitted to the test control device through the circuit board to be tested, and the test control device is also used for receiving the second signal and judging the bit error rate of the second signal to generate a test result of the circuit board to be tested.
7. The system of claim 6, wherein the signal processing component is further configured to send the first signal or the second signal back to the signal processing component.
8. The system of claim 6, wherein the simulation device is further configured to connect to the test control device, the test control device is further configured to transmit a receiving control signal to the signal processing device and transmit a third signal to the signal processing device through the circuit board under test, the signal processing device is further configured to receive the receiving control signal transmitted by the test control device, receive the third signal according to the receiving control signal, receive the sending control signal transmitted by the test control device, and transmit a fourth signal to the test control device through the circuit board under test according to the sending control signal, so that the test control device generates the on/off detection results of all the pins connecting the circuit board under test and the test control device according to the fourth signal.
9. The system of claim 6, wherein the test control device further comprises a signal generating element configured to generate the first signal of the differential signal.
10. The system of claim 6, wherein the test control device is further configured to select a test mode, generate a corresponding test signal according to the test mode, transmit the test signal to the simulation device, and generate the test result according to a response signal generated by the simulation device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111097083.7A CN115840125A (en) | 2021-09-18 | 2021-09-18 | System and method for testing backboard of nonvolatile memory storage device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111097083.7A CN115840125A (en) | 2021-09-18 | 2021-09-18 | System and method for testing backboard of nonvolatile memory storage device |
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| CN115840125A true CN115840125A (en) | 2023-03-24 |
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| CN202111097083.7A Pending CN115840125A (en) | 2021-09-18 | 2021-09-18 | System and method for testing backboard of nonvolatile memory storage device |
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