CN115840062A - Atom probe tomography sample, preparation method thereof and chip - Google Patents

Abstract

The embodiment of the disclosure provides an atom probe tomography sample, a preparation method thereof and a chip. The preparation method comprises the following steps: providing a substrate, wherein the substrate is provided with an array area and a peripheral area; performing a first semiconductor process on the array region to form a first semiconductor structure, simultaneously performing a process of forming a material of the first semiconductor structure in the first semiconductor process on the peripheral region, and forming stacked material layers on the peripheral region; and extracting and processing the material layer, and reserving the material layer to be detected to form a sample. The sample prepared by the embodiment of the disclosure has the advantages of uniform material distribution, reduced preparation difficulty, simplified process, improved sample integrity and surface smoothness, and improved accuracy of test results.

Description

Atom probe tomography sample, preparation method thereof and chip

Technical Field

The disclosure relates to the technical field of semiconductor detection, in particular to a sample for atomic probe tomography analysis, a preparation method thereof and a chip.

Background

APT (Atom Probe Tomography) is a technique that provides three-dimensional tomographic images and chemical identification on an atomic scale, and is a common test means for analyzing element distributions or doping concentrations in different semiconductor regions of a semiconductor device at present.

In the related art, in performing the APT test, an APT sample is prepared by using a portion to be tested in a semiconductor device. However, the structure of the part to be tested is complex, for example, a capacitor may have a hollow structure, and the material layers are not uniformly distributed, which greatly increases the difficulty of preparing the APT sample, and the prepared APT sample is incomplete and has a rough surface, thereby reducing the accuracy of the test result.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure, and thus it may include information that does not constitute related art known to those of ordinary skill in the art.

Disclosure of Invention

The embodiment of the disclosure provides an atom probe tomography sample, a preparation method thereof and a chip, which can reduce the difficulty of APT sample preparation, improve the integrity of the sample and the surface smoothness, and thus improve the accuracy of a test result.

The embodiment of the disclosure provides a preparation method of a sample for atom probe tomography analysis, which comprises the following steps: providing a substrate, wherein the substrate is provided with an array area and a peripheral area; performing a first semiconductor process in the array region to form a first semiconductor structure, simultaneously performing a process of forming a material of the first semiconductor structure in the first semiconductor process in the peripheral region, forming stacked material layers in the peripheral region; and extracting and processing the material layer, and reserving the material layer to be detected to form a sample.

According to some exemplary embodiments of the disclosure, the base is a semiconductor substrate, and before the first semiconductor process is performed in the array region, the method further includes: and forming a conical carrying column on the semiconductor substrate in the peripheral region.

According to some exemplary embodiments of the disclosure, the material of the carrier pillar is at least one of a semiconductor material and a conductor material.

According to some exemplary embodiments of the disclosure, a stacked material layer is formed at the peripheral region, including: and forming the material layer to be tested on the surface of the carrying column in a conformal mode.

According to some exemplary embodiments of the disclosure, the method further comprises: forming a protective layer in the peripheral area, wherein the protective layer completely covers the material layer to be tested on the carrying column; forming a stack of material layers in the peripheral region, further comprising: and continuing to synchronously execute the process of forming the material of the first semiconductor structure in the first semiconductor process on the protective layer, and forming a non-test material layer on the protective layer.

According to some exemplary embodiments of the disclosure, the method further comprises: removing the non-test material layer to expose the protective layer; extracting the material layer and processing, and reserving the material layer to be detected to form a sample, wherein the method comprises the following steps: cutting a target area in the peripheral area to obtain the semiconductor substrate of the target area, and the carrier posts, the material layer to be tested and the protective layer which are positioned on the semiconductor substrate; and removing the protective layer to expose the conical material layer to be detected, and forming the sample.

According to some disclosed exemplary embodiments, the material of the protective layer is at least one of photoresist, silicon oxide, silicon nitride, and silicon oxynitride.

According to some exemplary embodiments of the disclosure, extracting the material layer and processing, retaining the material layer to be tested, forming a sample, comprises: cutting the material layer in a target area by using a focused ion beam to form a sample strip containing the material layer to be detected; cutting off and fixing the part of the sample strip on a base of an atom probe to form a sample to be subjected to ring cutting; and circularly cutting the sample to be circularly cut to form the conical sample.

According to some exemplary embodiments of the disclosure, the bottom of the sample strip has a first metal layer.

According to some exemplary embodiments of the disclosure, before extracting and processing the material layer, further comprising: and forming a second metal layer on the surface of the material layer.

According to some exemplary embodiments of the disclosure, the second metal layer is made of at least one of tungsten, platinum and nickel.

According to some exemplary embodiments of the disclosure, after forming the first semiconductor structure in the array region and forming the stacked material layers in the peripheral region, further comprising: and synchronously performing a second semiconductor process in the array region and the peripheral region to respectively form second semiconductor structures on the first semiconductor structures in the array region and the material layer in the peripheral region.

According to some exemplary embodiments of the disclosure, the substrate comprises: a semiconductor substrate having the array region and the peripheral region; a third semiconductor structure located in the array region and the peripheral region of the semiconductor substrate.

Embodiments of the present disclosure also provide a sample for atom probe tomography, where the sample is prepared by the method of any of the above embodiments, and the sample includes: and sequentially stacking the material layers to be tested.

According to some exemplary embodiments of the disclosure, the sample further comprises: a semiconductor substrate and a conical carrier pillar. The carrier pillar is located on the semiconductor substrate, and the material layer to be tested is conformally located on the surface of the carrier pillar.

The embodiment of the present disclosure further provides a chip, which has a working area and a reserved sample area, wherein the working area has a first semiconductor structure formed by a first semiconductor process; the reserved sample area has a stack of material layers formed by a process of forming a material of the first semiconductor structure in the first semiconductor process; wherein the stacked material layers comprise a material layer to be tested.

According to some exemplary embodiments of the disclosure, the reserved sample area further has a cone-shaped carrier pillar therein, and at least the material layer to be tested is conformally located on the surface of the carrier pillar.

According to the technical scheme, the preparation method of the sample for the atom probe tomography analysis in the embodiment of the disclosure has at least one of the following advantages and positive effects:

in the embodiment of the disclosure, the substrate is divided into the array area and the peripheral area, the first semiconductor process is performed in the array area to form the first semiconductor structure, the process of forming the material of the first semiconductor structure in the first semiconductor process is performed in the peripheral area synchronously to form the stacked material layers, so that the material layer of the peripheral area and the corresponding material of the first semiconductor structure in the array area are formed synchronously, and the material layer have the same thickness and element distribution.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a flow diagram of a method of preparing a sample for atom probe tomography shown in some embodiments of the present disclosure;

FIG. 2 is a top view of a substrate shown in some embodiments of the present disclosure;

FIG. 3 isbase:Sub>A cross-sectional view taken along line A-A of FIG. 2;

FIG. 4 is a schematic diagram illustrating the formation of carrier pillars in the periphery region according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram illustrating the formation of a first semiconductor structure in the array region and the formation of a layer of material to be tested on the pillars in the peripheral region according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram illustrating the formation of a protection layer on a material layer to be tested in a peripheral region according to some embodiments of the disclosure;

FIG. 7 is a schematic diagram illustrating the formation of a non-test material layer in the array region and the peripheral region according to some embodiments of the present disclosure;

FIG. 8 is a schematic view of a target area with a non-test material layer removed in accordance with certain embodiments of the present disclosure;

FIG. 9 is a schematic illustration of a sample formed after removal of a protective layer according to some embodiments of the present disclosure;

fig. 10 is a top view of a first semiconductor structure formed in an array region and a material layer formed in a peripheral region according to some embodiments of the present disclosure;

FIG. 11 is a cross-sectional view taken along line B-B of FIG. 10;

FIG. 12 is a schematic illustration of a sample strip taken in a target area shown in some embodiments of the present disclosure;

FIG. 13 is a schematic view of the sample strip secured to a base of an atom probe according to some embodiments of the present disclosure;

FIG. 14 is a schematic illustration of a sample to be ring cut prepared according to some embodiments of the present disclosure;

fig. 15 is a schematic illustration of a sample formed into a cone shape, shown in some embodiments of the present disclosure.

Description of reference numerals:

1. a substrate; 101. an array region; 102. a peripheral region; 2. a first semiconductor structure; 20. a capacitor; 201. a lower electrode layer; 202. a dielectric layer; 203. an upper electrode layer; 3. a material layer to be tested; 4. carrying a column; 5. a protective layer; 6. a layer of non-test material; 7. a sample strip; 8. a sample is to be cut circularly; 9. a sample; 10. a base; 11. a first metal layer; 12. a tungsten needle; p, target area.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not numerical limitations of their objects.

The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

In addition, in the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Atom Probe Tomography (APT) is a nanoscale material analysis technique that can confirm atomic species and visually reconstruct the spatial positions thereof, relatively truly display the three-dimensional spatial distribution of atoms of different elements in a material, and is an analysis test means for analyzing the element distribution of different semiconductor regions of a semiconductor device.

The APT test relies on the electrical and subsequent field evaporation of individual atoms/clusters on the sample surface, which is made in the form of a conical tip with a vertex radius of less than 100nm. When a 3D (3-Dimensional) APT (atomic emission tomography) test is carried out, a sample is used as an anode and is connected with a positive high voltage, atoms at the tip end of the sample are in a state to be ionized, pulse voltage or pulse laser is superposed at the tip end of the sample, surface atoms of the sample are ionized and evaporated, a time-of-flight mass spectrometer is used for measuring the ratio of the mass-to-charge ratio (the ratio of the mass to the charge of the evaporated ions) of the evaporated ions, so that the mass spectrum peak of the ions is obtained to determine the element types of the ions, a position sensitive probe is used for recording the two-Dimensional coordinates of the flying ions on the surface of the tip end of the sample, and the longitudinal coordinates of the ions are determined through the layer-by-layer accumulation of the ions in the longitudinal direction, so that three-Dimensional space distribution images of different element atoms are obtained.

When preparing an APT sample, a part to be detected is directly taken out from a semiconductor device, and the part to be detected is processed to form a sample. For example, the portion to be measured is a capacitor in a Memory cell of a DRAM (Dynamic Random Access Memory). The structure of the capacitor is complicated, for example, in a cup-shaped capacitor, a hollow structure may exist in the center of a cup, if a sample is directly sampled in the cup-shaped capacitor, the sample taken out may also have a hollow structure, when the sample is subjected to circular cutting, due to the existence of the hollow structure, the circular cutting is not uniform, the surface of the finally formed conical sample is not uniform, and in severe cases, the sample is even broken, so that the difficulty in preparing an APT sample is increased, and a hollow structure may also exist in the final sample, so that the APT sample material is not uniformly distributed, and the accuracy of the test is reduced. In addition, there may be multiple material layers in the lateral direction at the same thickness of the sample, and still in the case of the cup-shaped capacitor described above, there may be an upper electrode, a dielectric, and a lower electrode at the same thickness at the same time. The evaporation fields of different materials have difference, and the metal and the semiconductor have different field evaporation voltages, which can seriously affect the accuracy of the atom probe during testing and even break the needle, cause distortion or failure during signal collection, and cause extremely low success rate of sample analysis.

Based on this, the embodiment of the present disclosure provides a method for preparing a sample for atom probe tomography. As shown in fig. 1 to 15, in which fig. 1 shows a flow chart of the preparation method, fig. 2 and 3 show a top view and a cross-sectional view of the substrate 1, respectively, fig. 4 to 9 show schematic diagrams of a sample preparation process in some embodiments, and fig. 10 to 15 show schematic diagrams of a sample preparation process in other embodiments.

As shown in fig. 1, a method for preparing a sample for atom probe tomography according to an embodiment of the present disclosure includes: steps S110 to S130.

S110: a substrate 1 is provided, the substrate 1 having an array region 101 and a peripheral region 102.

In some embodiments, as shown in fig. 2 and 3, the base 1 may be a semiconductor substrate, and the material of the semiconductor substrate may be silicon, silicon carbide, silicon-on-insulator, silicon germanium-on-insulator, or the like. The semiconductor substrate can also be implanted with certain doping particles according to design requirements to change electrical parameters.

The substrate 1 is divided into an array region 101 and a peripheral region 102, and a semiconductor process is performed on the semiconductor substrate 1 to form a semiconductor structure. After the semiconductor process is completed, the semiconductor structure formed in the array region 101 can be used as a semiconductor device by performing dicing. The peripheral region 102 of the embodiment of the present disclosure refers to a region around the array region 101, a semiconductor process may be performed in the peripheral region 102 simultaneously with the array region 101, a semiconductor structure formed in the peripheral region 102 is used for preparing a sample 9 (hereinafter referred to as a sample or an APT sample) for atomic probe tomography, and the peripheral region 102 may also be referred to as a sample preparation region.

Step S120: a first semiconductor process is performed in the array region 101 to form the first semiconductor structure 2, a process of forming the material of the first semiconductor structure 2 in the first semiconductor process is simultaneously performed in the peripheral region 102, and stacked material layers are formed in the peripheral region 102.

In an embodiment of the present disclosure, the first semiconductor process refers to a semiconductor manufacturing process, and the first semiconductor process may include: deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer vapor deposition, and the like; etching processes such as wet etching processes, dry etching processes, and the like; polishing processes, such as chemical mechanical polishing; cleaning process; an oxidation process; doping; spin coating process; a planarization process; photolithography, etc., i.e., processes used in fabricating semiconductor structures, will not be described herein.

The first semiconductor structure 2 in the embodiment of the present disclosure refers to a semiconductor structure including a portion to be tested, which may be a complete semiconductor device, for example, the first semiconductor structure 2 includes a capacitor 20 and a transistor (not shown in the figure), or the first semiconductor structure 2 may also be an incomplete semiconductor device, for example, the first semiconductor structure 2 includes only a part of the capacitor 20 or a part of the transistor (not shown in the figure), as long as the first semiconductor structure 2 includes a portion capable of preparing an APT sample, which is not limited herein.

In some embodiments, as shown in fig. 4, before the first semiconductor process is performed in the array region 101, the method may further include: a conical shaped charge pin 4 is formed on the semiconductor substrate in the peripheral region 102.

In some embodiments, the material of conical carrier post 4 may be at least one of a semiconductor and a conductor material. Carrier posts 4 may be metal-doped semiconductor to improve conductivity. The carrier pillar 4 may also be a conductive material, for example, the material of the carrier pillar 4 may be metal, which can improve the conductivity and strength to prevent fracture.

In the embodiment of the present disclosure, the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is performed simultaneously in the peripheral region 102.

Taking a semiconductor process for forming the cup-shaped capacitor 20 as an example, a sacrificial layer is deposited and formed on the array region 101 of the substrate 1, a mask layer with a capacitor hole pattern is deposited and formed on the sacrificial layer, the sacrificial layer is etched by using the mask layer, the pattern is transferred to the sacrificial layer to form a capacitor hole, a lower electrode layer 201 with a certain thickness is deposited on the inner wall and the bottom wall of the capacitor hole, a dielectric layer 202 is deposited and formed on the lower electrode layer 201, and an upper electrode layer 203 is deposited and formed on the dielectric layer 202, as shown in fig. 5, the lower electrode layer 201, the dielectric layer 202 and the upper electrode layer 203 form the cup-shaped capacitor 20.

It should be noted that, since the semiconductor process for forming the capacitor 20 is well known in the art, the above description only briefly describes the main process steps, and the detailed process for forming the capacitor 20 is not described in detail.

If the portion to be measured is the capacitor 20, when the semiconductor process is performed in the array region 101, the deposition process may be performed only in the peripheral region 102, such that the sacrificial layer and the mask layer are formed by performing the deposition process, and when the etching process is performed in the array region 101, the execution of the peripheral region 102 is stopped, or the shielding layer is disposed in the peripheral region 102, so that the material layer formed in the peripheral region 102 is not affected. While the array region 101 continues to perform a deposition process to form the lower electrode layer 201, the dielectric layer 202, and the upper electrode layer 203, the deposition process is simultaneously performed in the peripheral region 102 to form material layers of the lower electrode layer 201, the dielectric layer 202, and the upper electrode layer 203 stacked in a direction perpendicular to the substrate 1. Alternatively, the deposition process is performed simultaneously only in the peripheral region 102 to form the material layers of the stacked lower electrode layer 201, dielectric layer 202, and upper electrode layer 203, without performing the deposition process to form the sacrificial layer, the mask layer, simultaneously.

Based on this, the material layer formed in the peripheral region 102 is a stacked planar layer, and no hollow or other complex structure occurs, such as: with a plurality of different material layers at the same thickness in the direction perpendicular to the substrate 1. And the material layer of the peripheral region 102 is formed simultaneously with the material of the array region 101, and is completely the same as the material of the array region 101, so that the accuracy of the test result is ensured.

In an embodiment of the present disclosure, forming the stacked material layers in the peripheral region 102 includes: the material layer 3 to be tested is conformally formed on the surface of the loading column 4.

The material layer 3 to be tested is conformally formed on the surface of the carrier pillar 4, and can directly form a conical sample 9. If the semiconductor process is terminated, that is, the semiconductor process device is completed, the target area in the peripheral region 102 may be directly cut to form the APT sample 9. It should be noted that, since the tip of the APT sample 9 is smaller than 100nm, before the pillar 4 is formed, the size of the pillar 4 can be set according to the thickness of the material layer 3 to be measured, so as to ensure that the total size of the pillar 4 and the material layer 3 to be measured meets the size requirement of the APT sample 9. Compared with the method for directly sampling and processing the APT sample 9 in the semiconductor device to form the APT sample 9, the circular cutting is not needed to prepare the conical shape, the process is simpler, the material layer is uniform, and the test result is more accurate.

In the embodiment of the present disclosure, if the semiconductor process cannot be stopped at forming the material layer to be tested 3, that is, the semiconductor device is not prepared yet or the first semiconductor process is stopped at this time to sample the peripheral region 101, which is not favorable for forming the semiconductor device, after forming the material layer to be tested 3, as shown in fig. 6, the preparation method further includes: a protection layer 5 is formed in the peripheral region 102, and the protection layer 5 completely covers the material layer 3 to be tested on the carrier pillar 4.

In the embodiment of the present disclosure, the material of the protection layer 5 may be at least one of a photoresist, a silicon oxide, a silicon nitride, and a silicon oxynitride layer. As shown in fig. 6, the protective layer 5 fills the space between each adjacent conical material layer 3 to be tested, and completely covers the conical top of the material layer, so as to completely encapsulate the conical pillars 4 and the material layer 3 to be tested in the protective layer 5. Therefore, the material layer 3 to be tested can be isolated from the outside, and when the semiconductor process is continuously executed, other materials and processes cannot contact the material layer 3 to be tested, and the material layer 3 to be tested cannot be influenced. In other embodiments, the protection layer 5 may also be conformally formed on the surface of the material layer 3 to be tested, so as to completely cover the material layer 3 to be tested. In the embodiment of the present disclosure, the protection layer 5 is not particularly limited as long as it can completely cover the material layer 3 to be tested.

After forming the protection layer 5, the first semiconductor process is performed continuously, so that forming the stacked material layers in the peripheral region 102 further includes: the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is continued on the protective layer 5, and the non-test material layer 6 is formed on the protective layer 5.

In the embodiment of the present disclosure, as shown in fig. 7, the first semiconductor process may be continuously performed in the array region 101 and the peripheral region 102, and a material layer may be continuously deposited on the protection layer 5 in the peripheral region 102. The material layer formed at this time is referred to as a non-test material layer 6 because it is not required to be subjected to an APT test. The process of forming the material of the first semiconductor structure 2 in the first semiconductor process in the array region 101 is continuously performed in the peripheral region 102 in order to ensure the continuity of the first semiconductor process in the array region 101 to form a complete semiconductor structure/device.

Step S130: the material layer was extracted and processed, leaving the material layer 3 to be measured, forming sample 9.

As shown in fig. 8, after the first semiconductor process is completed, the method further includes: the non-test material layer is removed, exposing the protective layer 5.

Since the first semiconductor process is completed, for example, the entire capacitor 20 structure is formed in the array region, and the desired semiconductor structure is formed in the array region 101, the subsequent cutting process can be performed. For the peripheral region 102 where the sample 9 needs to be extracted, the non-test material layer 6 can be removed by a chemical mechanical polishing process or an etching process to expose the protection layer 5.

In the embodiment of the present disclosure, S130 further includes: and cutting a target area in the peripheral area 102 to obtain a semiconductor substrate of the target area, and a carrying column 4, a material layer to be tested 3 and a protective layer 5 which are positioned on the semiconductor substrate. The target area is understood to be the sampling area, and the material layer 3 to be tested of the target area obtained by cutting is used for preparing the APT sample 9.

In the embodiment of the present disclosure, as shown in fig. 9, S130 further includes: and removing the protective layer 5 to expose the conical material layer 3 to be detected to form a sample 9.

The protective layer 5 may be removed by an etching process or other chemical methods to expose the material layer 3 to be tested. The etching process may be a wet etching process or a dry etching process, and other chemical methods may be to dissolve the protective layer 5 by using a specific solvent without damaging the material layer 3 to be detected, and no matter which process or method is adopted, as long as the protective layer 5 can be removed and the material layer 3 to be detected is not damaged, a person skilled in the art may determine how to remove the protective layer 5 according to the material of the material layer 3 to be detected and the material of the protective layer 5, and the method is not particularly limited herein. In addition, after the protective layer 5 is removed, the material layer 3 to be tested on the semiconductor substrate may also be removed, that is, the material layer 3 to be tested on the semiconductor substrate between the cones is removed, so as to ensure that the material layer 3 to be tested is formed into a strict cone shape, and the test is more accurate.

In sample 9 formed in the above embodiment, since sample 9 is formed directly on a semiconductor substrate, sample 9 can be directly placed on a test stage, and sample 9 can be analyzed by performing positioning assistance with a laser. Therefore, in the above embodiment of the present disclosure, the cone shape can be formed during the semiconductor process, and the focused ion beam is not required to be used for sampling and performing the circular cutting, thereby avoiding by-products generated during the sampling of the focused ion beam, avoiding damages to the sample 9 during the circular cutting, and avoiding the need of welding the sample 9 on the silicon base 10 before the test, so that the preparation process is simpler, and the sample preparation efficiency is greatly improved. Meanwhile, the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is synchronously performed in the peripheral region 102, so that the material layer 3 to be tested of the sample 9 is completely the same as the material corresponding to the first semiconductor structure in the array region 101, and the authenticity of the analysis test data is ensured. And only the process of forming the material in the first semiconductor structure 2 is performed in the peripheral region 102, so that the formed material layers 3 to be tested are stacked on the carrier posts 4 layer by layer, the distribution is more uniform, and the test result is more accurate.

In other embodiments of the present disclosure, the method of making includes S110-S130 in the above embodiments. As shown in fig. 10 and 11, unlike the above-described embodiment, before the first semiconductor process is performed on the array region 101, the conical carrier pillars 4 are not formed on the semiconductor substrate in the peripheral region 102, but when the first semiconductor process is performed on the array region 101, the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is performed simultaneously in the peripheral region 102, and the stacked material layers are formed in the peripheral region 102.

As shown in fig. 12 to 15, the other differences from the above embodiment are that S130 includes: cutting the material layer in the target area P by using a focused ion beam to form a sample strip 7 containing the material layer 3 to be detected; portions of the sample strip 7 are cut and secured to the base 10 of the atom probe to form a sample 8 to be ring-cut. The sample 8 to be ring-cut is ring-cut to form a conical sample 9.

The Focused Ion Beam (FIB) is an Ion Beam generated by an Ion source and accelerated by an Ion gun, and the Focused Ion Beam acts on the surface of the sample 9 to cut or strip the sample 9. The target area P is understood to be the sampling area from which the material layer obtained by cutting is used for preparing the sample strip 7.

In some embodiments, as shown in fig. 13, the bottom of the sample strip 7 has a first metal layer 11. The first metal layer 11 may be a metal layer formed at the bottom of the material layer 3 to be tested when the first semiconductor process is performed, and the metal layer 11 is cut when FIB cutting is performed, so that the bottom of the formed sample 9 is a metal layer. Alternatively, if the bottom of the material layer 3 to be measured is not a metal layer, the first metal layer 11 may be formed on the bottom of the sample bar 7 by a sputtering process after the sample bar 7 is formed by FIB cutting. One end of the sample strip 7 is fixed on the base 10 of the atom probe, and the first metal layer 11 is arranged at the bottom of the sample strip 7, so that the first metal layer 11 can be directly utilized for welding, and the welding adhesion degree can be improved. In addition, because the metal has better electrical conductivity and thermal conductivity, the electric field heat conduction to the tip of the conical sample 9 is more facilitated in the analysis and test process, the phenomenon that the heat is enriched at the tip is improved, the success rate of the test is improved, and the signal-to-noise ratio of the analysis result is improved.

In some embodiments, the material of the first metal layer 11 may be at least one of tungsten (W), platinum (Pt) and nickel (Ni).

In some embodiments, as shown in fig. 12 and 13, a tungsten needle 12 may be used to extract the sample strip 7. Specifically, after the FIB is used to cut the sample strip 7, one end of the sample strip 7 is still connected to the material layer 3 to be measured in the peripheral region 102, and the other end is a free end. Moving the tungsten needle 12 to the surface of the free end, depositing platinum or tungsten between the tungsten needle 12 and the free end, and welding the tungsten needle 12 and the surface of the free end to connect the tungsten needle 12 and the free end of the sample strip 7. One end of the sample bar 7 is cut by FIB, and the tungsten needle 12 is moved to take out the sample bar 7.

As shown in fig. 13, one end of the sample strip 7 is fixed to the base 10, the sample strip 7 is partially cut, the tungsten needle 12 is moved, the cut portion is removed, and as shown in fig. 14, the portion to be circular-cut is retained on the base 10 to form the sample 8 to be circular-cut. As shown in fig. 15, the sample to be ring-cut 8 is then ring-cut to form a sample 9 in a conical shape, and the silicon base 10 and the sample 9 are placed in a test apparatus for testing.

In some embodiments, before the extracting the material layer and the processing in S130, the preparation method further includes: a second metal layer (not shown) is formed on the surface of the material layer.

After the stacked material layers are formed, the target region P needs to be determined for sampling. The determination of the target area P and the cutting by the FIB require SEM (Scanning Electron Microscope) imaging positioning, and the formation of the second metal layer on the surface of the material layer can improve the surface conductivity of the material layer, which is beneficial for the SEM imaging to be clearer and the positioning of the target area P to be more accurate. In addition, before SEM imaging, the substrate 1 of the peripheral region 102 to be observed is fixed to the carrier by using a carbon adhesive tape, so as to improve the conductivity of the sample on the peripheral region 102 and improve the imaging quality of SEM.

Specifically, a second metal layer may be deposited on the surface of the material layer by using a deposition process, and the material of the second metal layer may be at least one of tungsten (W), platinum (Pt) and nickel (Ni).

During testing, since the second metal layer is not an object to be analyzed, in order to avoid the influence of the second metal layer on the APT test result, after the sample strip 7 is obtained, the second metal layer on the surface of the sample strip 7 may be removed to expose the surface of the material layer 3 to be tested.

In some embodiments, after forming the first semiconductor structure 2 in the array region 101 and the stacked material layers in the peripheral region 102 in S130, and before extracting the sample strip 7, further comprising: a second semiconductor process is performed simultaneously in the array region 101 and the peripheral region 102 to form a second semiconductor structure (not shown) on the first semiconductor structure 2 of the array region 101 and on the material layer of the peripheral region 102, respectively.

Since the material layer to be tested is already formed in the peripheral region 102 and the preparation of the semiconductor device in the array region 101 is not yet completed, the semiconductor process needs to be continuously performed to complete the preparation of the semiconductor device, a second semiconductor process may be simultaneously performed on the array region 101 and the peripheral region 102, and a second semiconductor structure may be formed on the first semiconductor structure 2 of the array region 101 and on the material layer of the peripheral region 102, for example, the second semiconductor structure may be a conductor portion formed on the capacitor 20. The second semiconductor process is performed simultaneously in the array region 101 and the peripheral region 102, and a process of forming the second semiconductor material is not required to be selectively performed simultaneously in the peripheral region 102, which can simplify the operation process.

It should be noted that the second semiconductor structure may be a semiconductor structure located on the first semiconductor structure 2 in the semiconductor device, and the second semiconductor process may include the same process as that in the first semiconductor process, which is not limited herein.

After the second semiconductor structure is formed, before the sample strip 7 is extracted from the peripheral region 102, the second semiconductor structure in the peripheral region 102 may be removed, for example, the second semiconductor structure is removed by using a chemical mechanical polishing process to expose the material layer 3 to be tested, and the subsequent sampling process is the same as that in the above embodiment, which is not described herein again.

In some embodiments, the base 1 may include a semiconductor substrate and a third semiconductor structure (not shown in the figures). The semiconductor substrate has an array region 101 and a peripheral region 102, and the third semiconductor structure is located in the array region 101 and the peripheral region 102 of the semiconductor substrate. For example, the third semiconductor structure may be a structure of a transistor located below the capacitor 20. That is, before the first semiconductor process is performed, a third semiconductor structure is already formed on the semiconductor substrate, and since the material layer in the first semiconductor structure 2 needs to be tested, the third semiconductor structure and the semiconductor substrate are taken together as the base 1, the first semiconductor process is continuously performed on the third semiconductor structure located in the array region 101, and the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is performed on the third semiconductor structure located in the peripheral region 102, so that a complete semiconductor device can be formed in the array region 101.

In summary, in the method for preparing the sample 9 for atomic probe tomography according to the embodiment of the disclosure, the substrate 1 is divided into the array region 101 and the peripheral region 102, the first semiconductor process is performed in the array region 101 to form the first semiconductor structure 2, and the process of forming the material of the first semiconductor structure 2 in the first semiconductor process is performed in the peripheral region 102 to form the stacked material layers, so that the material layer of the peripheral region 102 and the corresponding material of the first semiconductor structure 2 in the array region 101 are formed simultaneously, and therefore, the two material layers have the same thickness and element distribution, and each layer in the peripheral region 102 is a flat layer, and the multiple layers are stacked.

The embodiment of the present disclosure further provides a sample 9 for atom probe tomography, where the sample 9 is prepared by the method in any of the embodiments, and details regarding the preparation method are not repeated here. The sample 9 includes material layers 3 to be tested sequentially stacked in a direction perpendicular to the substrate 1.

In some embodiments, the sample 9 further comprises a semiconductor substrate and a conical carrier pillar 4. The carrier pillar 4 is located on the semiconductor substrate, and the material layer 3 to be tested is conformally located on the surface of the carrier pillar 4.

According to the sample 9 disclosed by the embodiment of the disclosure, the distribution of the material layer 3 to be tested is more uniform, no hollow or other complex structures exist, the integrity and the surface smoothness of the sample 9 are improved, the accuracy of a test result can be improved, the preparation process is simple, the sample preparation efficiency is improved, and the cost is reduced.

The embodiment of the disclosure also provides a chip, which is provided with a working area and a reserved sample area. As in fig. 7 and 11, schematic diagrams of chips having different structures are shown. The working area of the chip has a first semiconductor structure 2 therein, and the first semiconductor structure 2 is formed by a first semiconductor process. The reserved sample area has stacked material layers formed by a process of forming the material of the first semiconductor structure 2 in a first semiconductor process; wherein, the stacked material layers include a material layer 3 to be tested.

In some embodiments, the working region of the chip corresponds to the array region 101 of the substrate 1 in any of the above embodiments, and the reserved sample region corresponds to the peripheral region 102 of the substrate 1 in any of the above embodiments. The first semiconductor process may be the first semiconductor process in any of the above embodiments, and is not described herein again.

In some embodiments, the stacked material layers of the reserved sample area are formed by a process of simultaneously performing the material forming the first semiconductor structure 2 in the first semiconductor process.

In some embodiments, the reserved sample area further has a cone-shaped carrier pillar 4, and at least the material layer 3 to be tested is conformally located on the surface of the carrier pillar 4.

In some embodiments, the sample reservation region may further have a protective layer 5 therein, and the protective layer 5 completely covers the material layer 3 to be tested on the carrier pillar 4.

According to the chip disclosed by the embodiment, the stacked material layers of the reserved sample area are completely the same as the corresponding materials of the first semiconductor structure 2 of the working area, each material layer in the reserved sample area is a flat layer, the multiple layers are stacked, the structure is simple, and hollow and other complex structures cannot exist, so that the APT sample 9 is prepared by utilizing the material layers in the reserved sample area, the preparation process can be simplified, the difficulty is greatly reduced, the material layers are uniformly distributed, the integrity and the surface smoothness of the prepared sample 9 can be improved, and the accuracy of a test result can be improved.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (17)

1. A method for preparing a sample for atom probe tomography, which is characterized by comprising the following steps:

providing a substrate, wherein the substrate is provided with an array area and a peripheral area;

performing a first semiconductor process in the array region to form a first semiconductor structure, simultaneously performing a process of forming a material of the first semiconductor process in the peripheral region, and forming stacked material layers in the peripheral region;

and extracting and processing the material layer, and reserving the material layer to be detected to form a sample.

2. The method of claim 1, wherein the base is a semiconductor substrate, and before the first semiconductor process is performed in the array region, the method further comprises: and forming a conical carrying column on the semiconductor substrate in the peripheral region.

3. The method of claim 2, wherein the material of the carrier pillar is at least one of a semiconductor material and a conductor material.

4. The method of claim 2, wherein forming a stack of material layers in the peripheral region comprises: and forming the material layer to be tested on the surface of the carrying column in a conformal mode.

5. The method of claim 4, further comprising:

forming a protective layer in the peripheral area, wherein the protective layer completely covers the material layer to be tested on the carrying column;

forming a stack of material layers in the peripheral region, further comprising:

and continuing to synchronously execute the process of forming the material of the first semiconductor structure in the first semiconductor process on the protective layer, and forming a non-test material layer on the protective layer.

6. The method of claim 5, further comprising:

removing the non-test material layer to expose the protective layer;

extracting the material layer and processing, and reserving the material layer to be detected to form a sample, comprising:

cutting a target area in the peripheral area to obtain the semiconductor substrate of the target area, and the carrier posts, the material layer to be tested and the protective layer which are positioned on the semiconductor substrate;

and removing the protective layer to expose the conical material layer to be detected, and forming the sample.

7. The method of claim 5, wherein the material of the protective layer is at least one of photoresist, silicon oxide, silicon nitride, and silicon oxynitride.

8. The method of claim 1, wherein extracting the material layer and processing the material layer to retain the material layer to be tested to form a sample comprises:

cutting the material layer in a target area by using a focused ion beam to form a sample strip containing the material layer to be detected;

cutting off and fixing the part of the sample strip on a base of an atom probe to form a sample to be subjected to ring cutting;

and circularly cutting the sample to be circularly cut to form the conical sample.

9. The method of claim 8, wherein the bottom of the sample strip has a first metal layer.

10. The method of claim 1, further comprising, prior to extracting and processing the material layer: and forming a second metal layer on the surface of the material layer.

11. The method of claim 10, wherein the second metal layer is made of at least one of tungsten, platinum and nickel.

12. The method of claim 1, further comprising, after forming the first semiconductor structure in the array region and the stacked material layers in the peripheral region:

and synchronously performing a second semiconductor process in the array region and the peripheral region to respectively form second semiconductor structures on the first semiconductor structures in the array region and the material layer in the peripheral region.

13. The method of claim 1, wherein the substrate comprises:

a semiconductor substrate having the array region and the peripheral region;

a third semiconductor structure located in the array region and the peripheral region of the semiconductor substrate.

14. A sample for atom probe tomography, the sample prepared by the method of any one of claims 1 to 13, the sample comprising: and sequentially stacking the material layers to be tested.

15. The sample according to claim 14, further comprising:

a semiconductor substrate;

the conical carrier pillar is positioned on the semiconductor substrate, and the material layer to be tested is conformally positioned on the surface of the carrier pillar.

16. A chip, characterized in that the chip has a working area and a reserved sample area, wherein,

the working area is provided with a first semiconductor structure, and the first semiconductor structure is formed by a first semiconductor process;

the reserved sample area has a stack of material layers formed by a process of forming a material of the first semiconductor structure in the first semiconductor process; and the stacked material layers comprise the material layer to be tested.

17. The chip of claim 16, wherein the reserved sample area further has a cone-shaped carrier pillar, and at least the material layer to be tested is conformally located on the surface of the carrier pillar.

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