CN115834003B - Definable Ethernet link layer redundancy method and definable Ethernet link layer redundancy device based on compatible real-time synchronization - Google Patents
Definable Ethernet link layer redundancy method and definable Ethernet link layer redundancy device based on compatible real-time synchronization Download PDFInfo
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Abstract
The invention discloses a link layer redundancy method of definable Ethernet based on compatible real-time synchronization, and the system is composed of a plurality of main control devices, switching devices and terminal devices which are linked and networked. A centralized and distributed control architecture is adopted, a network transmission controller is formed by a plurality of main control devices, and the real-time message forwarding paths of all the switching devices are controlled. The main controller collects real-time topology information of the whole network, and finds a plurality of optimal forwarding paths by comparing time delays, bandwidths and bit error rates of different channels and using Dijkstra algorithm. And constructing a plurality of redundant messages at the real-time sending terminal, forwarding the redundant messages according to a flow table issued by the network transmission controller by a switch of a plurality of channels, and synthesizing the redundant messages arriving at different paths and at different times at the real-time receiving terminal, so that high-reliability communication is realized, the information transmission redundancy is improved, and the reliability of an industrial control system is fundamentally improved.
Description
Technical Field
The invention belongs to the technical field of Internet, relates to a redundancy protocol of an Internet data link layer, and particularly relates to a definable Ethernet link layer redundancy method and device based on compatible real-time synchronization.
Background
High availability is critical for industrial ethernet and ethernet-based control systems, such as high-speed rail automation and substation automation systems. Since standard ethernet does not support fault tolerance, the high availability of ethernet can be improved by using redundancy protocols. Various redundancy protocols for ethernet have been developed and standardized, such as Rapid Spanning Tree Protocol (RSTP), media Redundancy Protocol (MRP), parallel Redundancy Protocol (PRP), high availability seamless redundancy (HSR), and the like. Wherein RSTP and MRP provide redundancy in the network, the disadvantage is the handover delay. While PRP and HSR provide seamless redundancy in end nodes, zero recovery time can be provided, but PRP requires repeated network infrastructure, while HSR is primarily used for ring-based topologies. Therefore, the existing redundancy protocol has the problems of low efficiency and complex protocol, and can not provide flexible definition functions for network users.
The traditional data exchange device generally comprises a control plane, a data plane and a management plane, wherein the management plane and the control plane always have higher coupling, and a definable Ethernet compatible with real-time synchronous communication separates the control plane from the original architecture to form an application layer, a control layer and a forwarding layer three-layer architecture, so that the exchange device can be simplified to be a forwarding device controlled by remote software, and network configuration and fault response are easier. The communication between network devices is realized by using definable Ethernet compatible with real-time synchronous communication, and a controller, a switching device and a terminal device are needed, wherein the controller is used for controlling the dispatch of a schedule, a high-priority static flow table and a low-priority dynamic flow table, the switching device and the terminal device perform global/regional time synchronization based on a clock calibration module, the terminal device is used as a transmitting end for transmitting a network message to the switching device, and the switching device transmits the network message to a corresponding receiving end according to the schedule and the flow table type issued by the controller after receiving the network message. In definable ethernet compatible with Real-time synchronous communication, network messages are divided into Real-time Message (RM) and regular Message (NM). For the transmission of RM-type messages, the sending end periodically triggers according to the global synchronous time, and the switch forwards the RM-type messages through a high-priority static flow table triggered at fixed time and finally receives the RM-type messages by the receiving end in an expected time window; and the NM message is randomly triggered by each node according to the event, and when the sender sends the NM message, the sender waits until the sending time window of the periodically triggered RM message of the sender is ended and then sends the NM message.
Based on the definable Ethernet compatible with real-time synchronous communication, the corresponding redundancy protocol is designed, so that the high safety and high redundancy of the real-time control message can be realized from the link, and the high availability of the Ethernet is improved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a definable Ethernet link layer redundancy method and a definable Ethernet link layer redundancy device based on compatible real-time synchronization, which adopt a centralized and distributed control architecture, and a network transmission controller is formed by a plurality of main control devices to control the real-time message forwarding paths of all switching devices so as to realize redundancy on the main controller, a communication link and device ports.
The link layer redundancy method based on the definable Ethernet compatible with real-time synchronization specifically comprises the following steps:
And 2, performing time synchronization of the whole network based on a synchronization protocol, and acquiring line delay between terminal devices by the main control device. The switching equipment collects the data quantity transmitted per unit time of each port, the data quantity received and the error rate, transmits the data quantity and the error rate to the main control equipment, and the data quantity, the data quantity received and the error rate are stored in the database by the main control equipment. The switching device manages data associated with itself via a slave controller.
And 3, the main control equipment selects the optimal n paths between any two source terminal equipment and the receiving terminal equipment according to the data and the line delay acquired in the step 2 as redundant paths between the two terminal equipment, completes optimization of the flow table, and distributes the flow table to the switching equipment in sequence. The contents of the flow table include a source mac, a destination mac, a redundant packet sequence number, and a forwarding port of the corresponding switching device. Wherein the redundant packet sequence number indicates the path to which the switching device belongs.
Preferably, in the optimization process of the flow table, the judgment standard of the optimal path between the two terminal devices is one or more of line delay, line bandwidth occupancy rate and line error rate.
Preferably, the optimal path is selected by using Dijkstra algorithm, and the optimization of the flow table is completed.
And 4, after n paths are selected, the source terminal equipment copies the real-time control message to be sent, and the number of copied message packets is not more than n. Then before calculating the CRC check value of each message packet, an id is inserted in the Ethernet type field, and a redundant packet sequence number corresponding to the message packet is inserted in the last byte before CRC.
And 5, the switching equipment receives the flow table issued by the main control equipment, and forwards the real-time control message processed by the source terminal equipment to the receiving terminal equipment through the corresponding port according to the forwarding port specified in the flow table.
And 6, after majority voting is carried out on all redundant message packets received from the switching equipment by the receiving terminal equipment, synthesizing the redundant message packets into a correct message for subsequent protocol analysis.
The invention has the following beneficial effects:
the invention adopts a centralized and distributed control architecture by a technique similar to a software defined Ethernet, and a network transmission controller is formed by a plurality of main control devices to control the real-time message forwarding paths of all switching devices. The method realizes redundancy on the main controller, the switch, the communication link and the terminal interface in the physical layer and the data link layer. Unlike conventional RSTP and other link redundancy techniques, the present invention selects network transmission paths that rely on real-time path information rather than inherent bandwidth. The main controller collects real-time topology information of the whole network, and finds out a plurality of optimal forwarding paths by comparing time delays, bandwidths and bit error rates of different channels and using Dijkstra algorithm. The method comprises the steps that a plurality of redundant messages are built at a real-time sending terminal, a switch of a plurality of channels forwards according to a flow table issued by a network transmission controller, redundant messages arriving at different paths and at different times are synthesized at a real-time receiving terminal, real-time control information in all channels in the whole network is planned and controlled, high safety and high redundancy of the real-time control messages can be fundamentally realized from a communication link, and when a certain device in the network fails or is attacked by the network, the stability of the system and the certainty and the accuracy of real-time information transmission can be ensured, so that the reliability of an industrial control system is fundamentally improved.
Drawings
FIG. 1 is a schematic diagram of a definable Ethernet device based on compatible real-time synchronization in an embodiment;
FIG. 2 is a diagram of a definable Ethernet hardware architecture based on compatible real-time synchronization in an embodiment;
FIG. 3 is a functional flow diagram of a switch slave controller in an embodiment;
FIG. 4 is a flow chart of flow table creation and optimization in an embodiment;
FIG. 5 is a schematic diagram of a message structure of a redundancy protocol in an embodiment;
fig. 6 is a flow chart of a receiving terminal device receiving a redundant message in an embodiment.
Detailed Description
The invention is further explained below with reference to the drawings;
the link layer redundancy method based on the definable Ethernet compatible with real-time synchronization specifically comprises the following steps:
As shown in fig. 2, the switching device includes an FPGA switching chip and an embedded CPU. The FPGA exchange chip is used for flow table management, data acquisition, protocol encapsulation and analysis of real-time control information and forwarding of the real-time control information according to the flow table. The embedded CPU is used as a slave controller for data statistics, flow table inquiry and control instruction issuing. Two communication modes are used for communication between the embedded CPU and the FPGA exchange chip, namely SPI and mac layer networks. The two communication modes represent two roles of the embedded CPU, namely a controller of the FPGA exchange chip and a common terminal in the Ethernet.
In SPI communication, a communication mode is set as duplex, an embedded CPU is used as a host, read/write register operation is initiated to an FPGA exchange chip, and an SPI message custom format is as follows: preamble, register address, register value. The step of writing the register is as follows: the embedded CPU inserts the register address to be written into the register address field of the message, and inserts the value to be written into the register value field of the message. The step of reading the register is: the embedded CPU sends a message to the FPGA exchange chip to inform the register address to be read; the FPGA exchange chip immediately takes out the content of the appointed register and packages the content into an SPI message; the embedded CPU sends a message to the FPGA exchange chip, the register address to be read is cleared to prevent repeated reading, and meanwhile, the FPGA exchange chip sends the packed message to the embedded CPU. In Ethernet communication, the embedded CPU is used as a terminal to be accessed into the FPGA switching chip, so that the CPUs of different switching devices and the control devices can be connected through a network, and the deployment of a distributed algorithm and the remote management of the control devices are realized.
The terminal device can support real-time control information and can be a device accessed to a plurality of real-time network cards or an embedded device. Each terminal equipment at least comprises two network ports, and can perform redundant transmission and redundant reception.
The main control equipment is a PC or an industrial personal computer, and is connected with the embedded CPU in the switching equipment through a plurality of networks and is integrated in the original Ethernet to form a centralized-distributed control structure. In order to prevent the system from being paralyzed caused by the failure of the master controller, the master controller and the standby master controllers can be adopted or a plurality of master controllers are commonly connected into the network system. The plurality of master controllers communicate with each other, monitor each other, actively shut off the error controllers, and issue the correct commands. Unlike the terminal device, the master device only needs to support general messaging. The main control equipment is used for managing the sampling information and the flow table state transmitted by each switching equipment in the database, optimizing the flow table according to the information in the database and issuing an optimal flow table scheduling strategy to each switching equipment. In addition, the main controller is also provided with a main database which stores id, mac, ip, working states, port ids and corresponding port states of all the switching devices, real-time transmission bandwidths, real-time receiving bandwidths and real-time transmission error rates of all the ports), and id, mac, ip and working states of all the device ids at both ends of the link, the link bandwidths and all the terminal devices. The main database has an aging function, and after a certain time, the expired item is deleted.
The multi-master controller redundancy method comprises the following steps: multiple master controllers ensure that only one is active and can send instructions to the switch. Meanwhile, the activated master controller sends self state messages to other master controllers at regular time. After other unactivated main controllers find out that the activated main controller fails, a new main controller is decided to activate by using an election method of STP, and all switches are notified to not trust the instruction of the failed main controller, so that the redundant replacement of the main controller is completed.
And 2, carrying out time synchronization of the whole network based on a synchronization protocol, and acquiring the line topology and the line time delay between the terminal devices by the main control device in the synchronization process.
The method for obtaining the line topology comprises the following steps: the embedded CPU of the switching device is used as a slave controller to collect relevant topology information around the slave controller, and the relevant topology information is uploaded to the master control device for integration. As shown in fig. 3, the embedded CPU of the switching device is provided with a topology management database for storing the status and information of each port, and the port opposite devices id, mac and ip in real time. When the port opposite terminal equipment is switching equipment, storing the related information of the opposite terminal switching equipment and a link; when the port opposite terminal equipment is terminal equipment, the relative information of the opposite terminal equipment and the port is stored. The topology discovery process is divided into the following four parts:
the first part is that the master device manages all switching devices: and after the embedded CPUs of all the switching devices are powered on, the UDP report message is sent immediately, and the UDP report message is sent once every 500 ms. And after receiving the report message of the switching equipment, the main control equipment returns to the corresponding switching equipment to confirm the message. Inquiring whether corresponding switching equipment exists in the database, if not, generating a new switching equipment id by a hash code of the mac, and storing related data; if so, updating the related data.
The second part is that the switching device acquires the adjacent switching device link: after receiving the acknowledgement message from the master device, the embedded CPU of all the switching devices starts Hong Fa a topology discovery message (LLDP message) including its own ip and mac. Before the FPGA exchange chip outputs the message, the output port id is stamped in the message. In order to limit the topology discovery message not to be forwarded and only to be received once, the following operations need to be performed: after receiving the topology discovery message, the FPGA exchange chip of each exchange device marks a receiving port id stamp and a local port bandwidth stamp in the message, and changes the destination mac (mass-sending mac) of the topology discovery message into mac corresponding to the embedded CPU of the exchange device. After the embedded CPU of the switching equipment receives the topology discovery message, all information of the link is obtained according to the source port id, the receiving port id and the ip and mac of the source port and is stored in a database of the embedded CPU. The key of the topology discovery message is that the ethernet type is different from the conventional ethernet type and has the following format: the local mac+the local ip+the egress port id+the egress port bandwidth+the ingress port id+the ingress port bandwidth.
The third part is that the switching device obtains the information of the adjacent terminal device: all terminal devices send topology statement messages at intervals, the messages are directly transferred into an embedded CPU of the direct-connected switching device, and the embedded CPU obtains the ip, mac and port numbers of the terminal devices. Also stored in the database of the switching device.
And the fourth part is that the embedded CPU uploads the local link database package message to the main control equipment at intervals. And continuously collecting the transmitted data quantity, the received data quantity and the error rate of each port by an FPGA (field programmable gate array) exchange chip in the exchange equipment, and storing corresponding data in a register at a specific position. The embedded CPU is used as a host for SPI communication, requests are sent to an FPGA exchange chip used as an SPI slave every one second, data of a corresponding register are read, after the data are integrated in the embedded CPU, the data are sealed in a communication message, the communication message is sent to the main control equipment through a common Ethernet message channel, and the communication message is stored in a database by the main control equipment.
The method for obtaining the line delay comprises the following steps: assume that each switching device S x At least one terminal is marked as E x . In the process of clock synchronization, assuming that the terminal equipment a is in master role, the master role initiates clock synchronization to all other slave terminals, and the line delay between all terminal equipment and the switching equipment is approximately t d . Terminal equipment a vs E 1 Clock synchronization to obtain time delay T a1 ＝t s1 +2t d . Then, terminal equipment a pair E 3 Clock synchronization to obtain time delay T a3 ＝t s1 +t s3 +2t d +t l,13 . By calculating T a3 -T a1 Then t can be obtained s3 +t l,13 The time delay of the corresponding communication segment is obtained. Similarly, the line delay of other communication sections is obtained through the process. And then the line delay is sent to the master control equipment by the terminal equipment.
Step 3, the main control equipment sends the bandwidth occupancy B in real time according to the line delay t acquired in the step 2 t Real-time received bandwidth occupancy B r And a real-time reception error rate B e And selecting the optimal n paths between the source terminal equipment a and the receiving terminal equipment b as redundant paths between the two terminal equipment, and completing the optimization of the flow table. The specific process is that firstly, the whole ethernet structure is represented by a weighted undirected graph g= (V, R), wherein V is a vertex, and represents all switching devices and terminal devices of the whole network, R is a weighted undirected edge, then the terminal devices a and b are two elements in the set V, the path T from the vertex a to the b is a vertex sequence, no vertex with the type of terminal device exists in the sequence, and according to the network structure shown in fig. 1, the paths between the terminal devices a and b are as follows:
①a→S1→S3→b
②a→S1→S4→S2→S5→b
③a→S2→S4→S1→S3→b
④a→S2→S5→b
defining the length D of the path to be the sum of the weights of all the edges on the path, d= Σw, the weights of the edges being determined from the data collected in step 2:
w＝t·(ω 1 B t +ω 2 B r +ω 3 B e )
wherein omega 1 ,ω 2 ,ω 3 As a design parameter for constructing the weights of the corresponding edges. As can be seen from the above equation, the paths with smaller delay, lower bandwidth occupancy and lower bit error rate have smaller weights, and the paths with shorter lengths should be preferentially selected by the master control device.
Dijkstra's algorithm is a breadth-first search method that uses a greedy strategy by declaring an array D ia To save the shortest distance from the source point to each vertex and a set T to save the vertices for which the shortest path has been found. Initially, set T has only vertex a, and the path weight for vertex a is assigned 0, D ia [s]=0. If there is a directly reachable edge (a, b) for vertex a, D is then ia [m]Let w be the weight on the edge, and let the path length of vertices that all a cannot reach directly be infinity. Then, from D ia And selecting a minimum value in the array, wherein the minimum value is the shortest path from the vertex a to the vertex corresponding to the minimum value, and adding the point into the set T. At this time, one vertex is completed, then, it is determined whether the vertex newly added to the set T can reach other vertices, and whether the path length through the vertex to reach other vertices is shorter than the path length from the vertex a directly to the vertex, if so, the vertices are replaced in the array D ia Is a value of (b). The above process is then repeated until all vertices are included in the set T.
In the present embodiment, the number of redundant channels between the terminal devices a, b is set
And (3) finding 2 shortest paths between a and b by using Dijkstra algorithm to obtain (3) and (4) and constructing a flow table. The content of the flow table comprises a source mac, a destination mac and a redundant packet sequence number n ab And a forwarding port corresponding to the switching device. In the present embodiment, the redundant packet sequence number n ab =0, 1, and corresponds to the (3) th and (4) th paths, respectively. The flow table represents the forwarding port required by the redundant message appointed by the main control equipment to the exchange equipment for implementing message forwarding, and the content of the flow table represents that when the source mac accords with the destination mac, the source mac accords with the redundancyNumber n of remaining packet ab And according to the coincidence, forwarding to the corresponding port.
And 4, after 2 redundant paths are selected in the step 3, the source terminal equipment copies the real-time control message to be sent, and the number of copied message packets is not more than 2. Then, a link layer message is established according to the illustration of fig. 5, and first, two bytes of ethernet type in the original message are converted into one byte of "redundant packet sequence number" and one byte of "real-time ethernet type". After receiving the message, the switching device directly reads the real-time ethernet type in the message, determines whether the message is a real-time message, and then stores the redundant packet sequence number for comparison with the redundant packet sequence number in the flow table. And then adding an id which is not repeated in a period of time after the message data is finished, and using the id for receiving judgment of a subsequent redundant receiving module. Unlike the redundant packet sequence number and the real-time ethernet type, the id does not need to be identified by the switching device, and can be regarded as normal data direct transmission.
And 5, the main control equipment distributes the optimized flow table to an embedded CPU of the switching equipment, and then the embedded CPU distributes the optimized flow table to the FPGA switching chip. The FPGA exchange chip uses a ram to manage all the flow tables, and uploads the flow tables for the inquiry of the main controller after the request of the embedded CPU. Aiming at the real-time control information stored in the combining queue of the switching equipment sent by the source terminal equipment, the reader redundancy packet sequence number is used for sequentially inquiring the flow table to obtain the forwarded port, and then the real-time control information is sent to the PHY chip of the corresponding port.
After the flow table is issued to the FPGA switch chip, each switch device already has the capability to forward the relevant redundant messages. When any switching device or line in the system shown in fig. 1 fails, it will be reflected in the port statistics that exceed the limit. When the main control equipment collects all port statistic data in real time, the main control equipment can confirm the fault node or the line and re-plan the flow table according to the fault node or the line.
Thus, the link layer redundancy method of the definable Ethernet based on compatible real-time synchronization is completed. It should be noted that the foregoing embodiments merely illustrate the technical solution and design principles of the present invention in detail by using an optimized technical solution, and should not be construed as limiting the scope of the present invention.
Claims (9)
1. The link layer redundancy method based on the definable Ethernet compatible with real-time synchronization is characterized in that: the method specifically comprises the following steps:
step 1, constructing a definable Ethernet compatible with real-time synchronous communication, which comprises a plurality of switching devices, a main control device and terminal devices; in the Ethernet, a plurality of usable information paths are arranged between each pair of terminal equipment which needs to carry out real-time control information communication; the main control equipment and the plurality of switching equipment are respectively used as management equipment of a centralized-distributed topology and form a network topology real-time management framework together;
step 2, synchronizing the time of the whole network based on a synchronization protocol, and acquiring the line time delay between terminal devices by a main control device; the switching equipment collects the real-time transmission bandwidth occupancy B of each port t Real-time received bandwidth occupancy B r And a real-time reception error rate B e Transmitting to the main control equipment;
step 3, the main control equipment selects the optimal n paths between any two source terminal equipment and receiving terminal equipment as redundant paths according to the data acquired in the step 2, completes the optimization of the flow table, and distributes the flow table to the switching equipment; the content of the flow table comprises a source mac, a destination mac, a redundant packet sequence number and a forwarding port of the corresponding switching equipment; wherein the redundant packet sequence number represents the path to which the switching device belongs;
step 4, after n paths are selected, the source terminal equipment copies the real-time control message to be sent, and the number of copied message packets is not more than n; before calculating the CRC value of each message packet, inserting a redundant packet id in the Ethernet type field, and inserting a redundant packet sequence number corresponding to the message packet in the last byte before CRC;
step 5, the switching equipment receives the flow table issued by the main control equipment, compares redundant packet sequence numbers in the real-time control message processed by the source terminal equipment, and forwards the real-time control message to the receiving terminal equipment through the corresponding port according to the specified forwarding port in the flow table after confirming that the redundant packet sequence numbers are error-free;
and 6, after majority voting is carried out on all redundant message packets received from the switching equipment by the receiving terminal equipment, synthesizing the redundant message packets into a correct message for subsequent protocol analysis.
2. The link layer redundancy method of a definable ethernet based on compatible real-time synchronization according to claim 1, wherein: the whole Ethernet structure is represented by a weighted undirected graph G= (V, R), wherein V is a vertex set, all switching equipment and terminal equipment of the whole Ethernet are included, and R is a weighted undirected edge; defining a path T between two vertexes as a vertex sequence not including terminal equipment, wherein the path length D is the sum of weights of all sides on the path, and the main control equipment sends the bandwidth occupancy B in real time according to the line delay T acquired in the step 2 t Real-time received bandwidth occupancy B r And a real-time reception error rate B e The weight of the edge is determined.
3. The link layer redundancy method of a definable ethernet based on compatible real-time synchronization according to claim 1, wherein: the main control equipment adopts Dijkstra algorithm to select n optimal paths.
4. The link layer redundancy method of a definable ethernet based on compatible real-time synchronization according to claim 1, wherein: the redundancy message generated by the source terminal device includes a 6-byte destination mac address, a 6-byte source mac address, a 1-byte redundancy packet sequence number, a 1-byte ethernet type, data, a 1-byte redundancy packet id, and a 4-byte frame check sequence FCS.
5. The link layer redundancy method of a definable ethernet based on compatible real-time synchronization according to claim 1, wherein: the process of receiving the redundant message by the receiving terminal equipment is as follows: after CRC check, starting an independent thread; when each thread is started, starting a time window with a time length capable of receiving all redundant messages, and performing majority voting on all messages received in the thread after the time window is finished to obtain a comprehensive message; each thread only receives redundant messages with homologous mac and same id, and for different messages, the receiving terminal equipment starts a new thread to receive.
6. The link layer redundancy device based on the definable Ethernet compatible with real-time synchronization is characterized in that: a link layer redundancy method for implementing a definable ethernet based compatible real-time synchronization according to any one of claims 1 to 5; the device comprises a switching device, a main control device and a terminal device;
the switching equipment comprises an FPGA switching chip and an embedded CPU; the FPGA exchange chip is used for flow table management, data acquisition, protocol encapsulation and analysis of real-time control information and forwarding of the real-time control information according to the flow table; the embedded CPU is used for data statistics, flow table inquiry and control instruction issuing; the FPGA exchange chip is communicated with the embedded CPU through the serial peripheral interface SPI, and the embedded CPU is directly connected with the FPGA exchange chip at the mac layer as a terminal;
the terminal equipment can support real-time control information, and each terminal equipment at least comprises two network ports for redundant transmission and reception;
the main control equipment is a PC or an industrial personal computer and is connected with the embedded CPU in the exchange equipment by a plurality of networks; the main control equipment is used for managing the sampling information and the flow table state transmitted by each switching equipment in the database, optimizing the flow table according to the information in the database and issuing an optimal flow table scheduling strategy to each switching equipment.
7. The real-time synchronization based definable ethernet link layer redundancy apparatus of claim 6, wherein: in the switching device, the step of writing the register is: the embedded CPU inserts the register address to be written into the register address field of the message, and inserts the value to be written into the register value field of the message; the step of reading the register is: the embedded CPU sends a message to the FPGA exchange chip to inform the register address to be read; the FPGA exchange chip immediately takes out the content of the appointed register and packages the content into an SPI message; the embedded CPU sends a message to the FPGA exchange chip, the register address to be read is cleared to prevent repeated reading, and meanwhile, the FPGA exchange chip sends the packed message to the embedded CPU.
8. A definable ethernet based link layer redundancy apparatus for compatible real time synchronization according to claim 6 or 7, wherein: the FPGA exchange chip in the exchange equipment continuously collects the transmitted data quantity, the received data quantity and the error rate of each port, and stores corresponding data in a register at a specific position; the embedded CPU is used as a host for SPI communication, requests are sent to the FPGA exchange chip serving as a slave at intervals of one second, data of a corresponding register are read, after the data are integrated in the embedded CPU, the data are sealed in a communication message, the communication message is sent to the main control equipment through a common Ethernet message channel, and the communication message is stored in a database by the main control equipment.
9. The real-time synchronization based definable ethernet link layer redundancy apparatus of claim 6, wherein: the main control equipment distributes the optimized flow table to an embedded CPU of the switching equipment, and then the embedded CPU distributes the optimized flow table to the FPGA switching chip; the FPGA exchange chip uses a ram to manage all the flow tables, and uploads the flow tables for the inquiry of the main controller after the request of the embedded CPU.
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