CN115832661A - Manufacturing method of temperature compensation attenuator based on NTC (negative temperature coefficient) heat-sensitive ceramic substrate chip - Google Patents
Manufacturing method of temperature compensation attenuator based on NTC (negative temperature coefficient) heat-sensitive ceramic substrate chip Download PDFInfo
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Abstract
A manufacturing method of a temperature compensation attenuator based on an NTC heat-sensitive ceramic substrate chip belongs to the technical field of electronic components. The temperature-sensitive ceramic substrate comprises an NTC temperature-sensitive ceramic substrate, a thin film resistance layer, a thin film electrode layer and a back insulation protective layer. The NTC thermistor consists of an NTC thermal sensitive ceramic substrate and an electrode thereof, and is not only a bearing body of the chip temperature compensation attenuator, but also a functional body of a negative temperature coefficient resistor of the attenuation network of the chip temperature compensation attenuator; preparing a thin film resistor on the upper surface of the NTC thermosensitive ceramic substrate, and preparing a thin film electrode layer on the thin film resistor layer; preparing a back insulation protective layer on the bottom surface of the NTC thermosensitive ceramic substrate; the resistance film is not only a positive temperature coefficient resistance functional body of the attenuation network of the chip temperature compensation attenuator, but also an adhesion resistance layer of the electrode layer. The problems of large size, low N value and low application frequency of the conventional temperature compensation attenuator are solved. The chip temperature compensation attenuator is widely applied to the fields of 5G communication, electronic radars, man-machine delivery and the like.
Description
Technical Field
The invention belongs to the technical field of electronic components, and further relates to the field of attenuators, in particular to a manufacturing method of a temperature compensation attenuator based on an NTC heat-sensitive ceramic substrate chip.
Background
The passive chip type film temperature compensation attenuator (hereinafter referred to as temperature compensation attenuator) has the characteristics of high application frequency, good compensation characteristic, no system distortion, phase shift, time delay and the like, is widely applied to the fields of industrial internet, electronic radar, man-machine interaction, 5G communication and the like, and plays the roles of temperature compensation and isolation protection in an electronic system.
At present, the temperature compensation attenuator is mainly formed by organically integrating NTC resistance paste and PTC resistance paste on a ceramic substrate in a thick film printing mode to form a pi-type attenuation network, and then the product preparation is completed through processes such as encapsulation protection, electrode preparation and the like. However, this preparation method has the following limitations:
firstly, the minimum operation size of the thick film process platform is about 60 μm in general, and the NTC resistor and the PTC resistor are integrated on a limited area to form the attenuator core resistor network, so the operation precision of the thick film platform greatly limits the reduction of the product size, and therefore the minimum size of the temperature compensation attenuator in the current market is 1.91mm × 1.52mm × 0.30mm, which is equivalent to the size of the resistor 2012.
Secondly, for the high temperature coefficient (N value) temperature compensation attenuator, the beta value of the used NTC slurry is very high, and for the attenuator of 1 dB-10 dB, the resistance value is 100 omega level, so that the design of reducing the square on a limited area becomes the key for preparing the high N value temperature compensation attenuator, and the design of reducing the square is limited due to the limited size, so that the temperature compensation attenuator can be basically only used for improving N1 (-0.001 dB/dB/DEG C) to N9 (-0.009 dB/dB/DEG C) at present and cannot provide the temperature compensation attenuator with a higher N value.
Finally, the application frequency of the temperature-compensated attenuator prepared by thick film printing is greatly limited, and the temperature compensation characteristic of the temperature-compensated attenuator is reduced along with the increase of the application frequency. The application frequency of the temperature-compensated attenuator commonly used in the market is only 18GHz.
The thin film technology is an effective method for solving the problem of size miniaturization of the temperature compensation attenuator, but the research on the NTC heat-sensitive material target and the PTC heat-sensitive material target is not mature at present, and the thin film temperature compensation attenuator does not exist in the market.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the problems that the minimum operation size of a thick film process platform of the temperature compensation attenuator prepared by the conventional thick film printing process is limited, the high N value is limited by the size, and the application frequency is limited are solved.
The invention has the following inventive concept: the film resistor attenuation network, the film electrode and the insulating protective layer are manufactured by adopting the film sputtering and photoetching forming process and interact with the resistor of the NTC thermosensitive ceramic substrate, so that the aims of micro size, high N value and high frequency are fulfilled.
Therefore, the invention provides a temperature compensation attenuator based on an NTC heat-sensitive ceramic substrate chip, and the schematic structure is shown in figures 1-2.
The NTC thermal sensitive ceramic substrate comprises an NTC thermal sensitive ceramic substrate 1, a thin film resistance layer 2, a thin film electrode layer 3 and a back surface insulating protection layer 4.
The resistance attenuation network of the chip temperature compensation attenuator is composed of an NTC thermistor, a film resistor and a film electrode.
The NTC thermistor consists of an NTC thermosensitive ceramic substrate and an electrode thereof, wherein the NTC thermosensitive ceramic substrate is not only a supporting body of the chip temperature compensation attenuator, but also a functional body of a negative temperature coefficient resistor of the attenuation network of the chip temperature compensation attenuator.
The NTC thermal sensitive ceramic substrate is a double-sided polished substrate, a thin film resistor is prepared on the upper surface of the NTC thermal sensitive ceramic substrate, and a thin film electrode layer is prepared on the thin film resistor layer; and preparing a back insulating protective layer on the bottom surface of the NTC thermosensitive ceramic substrate.
The thin film resistor consists of an electrode on the NTC thermal sensitive ceramic substrate and a sputtering resistor thin film, wherein the resistor thin film is not only a positive temperature coefficient resistor functional body of the attenuation network of the chip temperature compensation attenuator, but also an adhesion blocking layer of an electrode layer.
The thin film electrode and the thin film resistor are completed by a thin film process.
The surface pattern structure of the chip temperature compensation attenuator is determined by the specific shapes and specific combinations of the thin film resistor layer and the thin film electrode layer, and comprises but is not limited to pi-type network straight resistor double-straight-line parallel electrodes, pi-type network S-shaped resistor UT-shaped nested parallel electrodes, pi-type network U-resistor double-straight-line broken strip-shaped parallel electrodes, T-type network straight resistor three-straight-line parallel electrodes, T-type network straight resistor cross-shaped nested three-parallel electrodes or T-type network S-shaped resistor three-straight-line parallel electrodes and the like. In general, the shape of the electrodes includes, but is not limited to, S-shaped electrodes, nested electrodes, rigid parallel-type electrodes, and the like; the shape of the thin film resistor includes, but is not limited to, an S-type resistor, a Z-type resistor, and a rigid resistor.
The NTC thermistor consists of an NTC thermosensitive substrate and an electrode. Under the condition that the sheet resistance of the NTC thermosensitive substrate is constant, the resistance value of the NTC thermosensitive resistor is determined by the shape of the electrodes and the distance between the electrodes.
The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator comprises the following steps:
(1) Cleaning: selecting an NTC thermal sensitive ceramic substrate with a double-sided polished specific B value, sequentially carrying out ultrasonic cleaning on the substrate by using a ceramic cleaning agent, acetone, alcohol and deionized water, and then drying in an oven;
(2) Sputtering of the resistance film layer: preparing a resistance film layer on a polished surface on one side of the NTC thermosensitive ceramic substrate by adopting a magnetron sputtering method;
(3) Electrode layer sputtering: adopting a magnetron sputtering method to form an electrode film layer on the thermosensitive ceramic substrate with the prepared resistance film layer;
(4) Primary photoetching: gluing, exposing and developing; etching the electrode film layer, and removing the photoresist after etching;
(5) Secondary photoetching: after the electrode is etched, coating glue, baking, exposing and developing again, etching the thin film resistance layer, and removing the glue after etching;
(6) Preparing a back insulating layer: preparing a polyimide film protective layer on the back surface of the NTC thermosensitive ceramic substrate by adopting a rotary coating mode, and carrying out pre-baking, exposure and post-baking; then curing in an oven;
(7) Scribing and cutting: and scribing and cutting the NTC thermal sensitive ceramic substrate by adopting a mechanical cutting method to obtain the chip temperature compensation attenuator with the set size.
The resistance film layer is prepared by adopting a film process, including but not limited to vacuum evaporation, chemical deposition, sputtering and the like;
the resistance film layer material includes but is not limited to TaN, niCr, crSi, tiAlN and other Ni-Co series films, ta series resistance films, si series resistance films, au-Cr series resistance films, ni-P series resistance films.
The electrode film layer is of a metal film structure, and the electrode layer is made of materials including but not limited to a TiW-Au structure metal film, a TiW-Ni-Au structure metal film, a TiW-Cu structure metal film, tiN-AL and the like.
The material of the back insulating protective layer includes but is not limited to polyimide film, thick film printed resin film, silicon nitride film, silicon oxide film and the like; the preparation process includes but is not limited to thick film printing, CVD deposition, dispensing coating, magnetron sputtering and the like.
Has the advantages that:
compared with the existing temperature compensation attenuator preparation technology, the preparation method fully utilizes the advantages of the NTC thermal sensitive ceramic substrate such as linear temperature compensation characteristic and miniaturization of a thin film process, so that the prepared chip temperature compensation attenuator has the characteristics of small volume, high application frequency (up to 36 GHz), good compensation characteristic, large temperature compensation coefficient, good compensation linearity and the like; meanwhile, the chip temperature attenuator is prepared by using the process method, and the process is simple, high in repeatability and low in cost.
The chip temperature compensation attenuator prepared by the invention can be widely applied to the fields of 5G communication, electronic radar, man-machine delivery and the like.
Drawings
FIG. 1 is a schematic view of a pi-type chip temperature-compensation attenuator.
FIG. 2 is a schematic structural diagram of a T-type chip temperature-compensated attenuator.
In the figure: the material comprises an NTC thermal sensitive ceramic substrate 1, a resistance functional layer 2, an electrode layer 3 and a back surface insulation protective layer 4.
Detailed Description
As shown in fig. 1-2, in the manufacturing method of the NTC-based thermal ceramic substrate chip temperature compensation attenuator, the resistive film layer is a TaN resistive film, and the thickness of the film layer is 0.05 μm to 1 μm; the electrode film layer adopts a metal electrode film with a TiW-Au composite structure, and the thickness of the electrode film layer is 2-4 mu m; the NTC thermal sensitive ceramic substrate is double-sided polished, the roughness is 0.005-0.025 μm, the thickness of the substrate is 150-550 μm, and the beta value range is 150-4500K; the back insulating protective layer is a polyimide film.
The specific manufacturing process comprises the following steps:
(1) Cleaning: selecting an NTC thermal sensitive ceramic substrate with a specific B value and polished on both sides, sequentially carrying out ultrasonic cleaning on the substrate by using a ceramic cleaning agent, acetone, alcohol and deionized water for 10min +/-2 min respectively, and then drying in an oven at 150 +/-10 ℃ for 120-180 min;
(2) Sputtering of the resistance film layer: preparing a resistance film layer on a polished surface on one side of the NTC thermal sensitive ceramic substrate by adopting a magnetron sputtering method, wherein the sputtering time is 20-60 min, and the thickness of the film layer is 0.05-1 mu m;
(3) Electrode layer sputtering: sputtering a TiW adhesion layer and an Au layer on a thermal sensitive ceramic substrate with a prepared resistance film layer in sequence by adopting a magnetron sputtering method, wherein the sputtering time of the Au layer is 40-60 min, and the thickness is about 2-4 mu m; the thickness of the titanium tungsten is about 150nm to 200nm;
(4) Primary photoetching: gluing; baking the mixture on a hot plate at the temperature of 95-110 ℃ for 90s +/-10 s; exposing for 10s +/-3 s and developing; and etching the top gold layer and the titanium-tungsten layer. Removing the photoresist after etching, and brushing the product with acetone;
(5) Secondary photoetching: after the electrode is etched, coating glue again, baking (the temperature is 95-110 ℃, the time is 90s +/-10 s), exposing (the time is 10s +/-3 s) and developing (the time is 45s +/-10 s), then etching the thin film resistor body, and finally removing the glue;
(6) Preparing a back insulating layer: preparing a polyimide film protective layer on the other polished surface of the NTC thermosensitive ceramic substrate by adopting a rotary coating mode, wherein the pre-drying temperature is 95-110 ℃, and the pre-drying time is 90s +/-10 s; exposing (time 35s +/-15 s) and post-baking; then curing in an oven at 250 +/-5 ℃ for 240-300 min;
(7) Scribing and cutting: and scribing and cutting the NTC thermal sensitive ceramic substrate by adopting a mechanical cutting method to obtain the chip temperature compensation attenuator with the size meeting the requirement.
Finally, it should be noted that: the above examples are given for clarity of illustration only, and the present invention includes but is not limited to the above examples, which are neither exhaustive nor exhaustive of all embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. Embodiments that meet the requirements of the present invention are within the scope of the present invention.
Claims (10)
1. A manufacturing method of a temperature compensation attenuator based on an NTC heat-sensitive ceramic substrate chip is characterized by comprising the following steps:
the chip temperature compensation attenuator structurally comprises an NTC thermal sensitive ceramic substrate, a thin film resistance layer, a thin film electrode layer and a back insulation protective layer;
the resistance attenuation network of the chip temperature compensation attenuator consists of an NTC thermistor, a film resistor and a film electrode;
the NTC thermistor consists of an NTC thermosensitive ceramic substrate and an electrode thereof, wherein the NTC thermosensitive ceramic substrate is not only a bearing body of the chip temperature compensation attenuator, but also a functional body of a negative temperature coefficient resistor of the attenuation network of the chip temperature compensation attenuator;
the NTC thermal sensitive ceramic substrate is a double-sided polished substrate, a thin film resistor is prepared on the upper surface of the NTC thermal sensitive ceramic substrate, and a thin film electrode layer is prepared on the thin film resistor layer; preparing a back insulation protective layer on the bottom surface of the NTC thermosensitive ceramic substrate;
the thin film resistor consists of an electrode and a sputtering resistor thin film on the NTC thermal sensitive ceramic substrate, wherein the resistor thin film is not only a positive temperature coefficient resistor functional body of the attenuation network of the chip temperature compensation attenuator, but also an adhesion blocking layer of an electrode layer;
the manufacturing method of the chip temperature compensation attenuator comprises the following steps:
(1) Cleaning: selecting an NTC thermal sensitive ceramic substrate with a double-sided polished specific B value, sequentially carrying out ultrasonic cleaning on the substrate by using a ceramic cleaning agent, acetone, alcohol and deionized water, and then drying in an oven;
(2) Sputtering of the resistance film layer: preparing a resistance film layer on a polished surface on one side of the NTC thermosensitive ceramic substrate by adopting a magnetron sputtering method;
(3) Electrode layer sputtering: adopting a magnetron sputtering method to form an electrode film layer on the thermosensitive ceramic substrate with the prepared resistance film layer;
(4) Primary photoetching: gluing, exposing and developing; etching the electrode film layer, and removing the photoresist after etching;
(5) Secondary photoetching: after the electrode is etched, coating glue, baking, exposing and developing again, etching the thin film resistance layer, and removing the glue after etching;
(6) Preparing a back insulating layer: preparing a polyimide film protective layer on the back surface of the NTC thermosensitive ceramic substrate by adopting a rotary coating mode, and carrying out pre-baking, exposure and post-baking; then curing in an oven;
(7) Scribing and cutting: and scribing and cutting the NTC thermal sensitive ceramic substrate by adopting a mechanical cutting method to obtain the chip temperature compensation attenuator with the set size.
2. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the resistance attenuation network is a pi-type resistance attenuation network or a T-type resistance attenuation network.
3. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the resistance film layer is prepared by adopting a film process, and the film process is vacuum evaporation, chemical deposition or sputtering.
4. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the resistance film layer is a Ni-Co series film, a Ta series resistance film, a Si series resistance film, an Au-Cr series resistance film or a Ni-P series resistance film, and the thickness of the film layer is 0.05-1 mu m.
5. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature compensation attenuator according to claim 4, wherein: the resistance film is made of TaN, niCr, crSi or TiAlN.
6. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the electrode film layer is of a metal film structure, and the thickness of the electrode layer is 2-4 mu m.
7. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the metal film structure is a TiW-Au structure metal film, a TiW-Ni-Au structure metal film, a TiW-Cu structure metal film or a TiN-AL structure metal film.
8. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the NTC thermal sensitive ceramic substrate is double-sided polished, the roughness is 0.005-0.025 μm, the thickness of the substrate is 150-550 μm, and the beta value range is 150-4500K.
9. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the back insulation protective layer is an insulation film, the preparation process of the insulation film is thick film printing, CVD deposition, dispensing coating or magnetron sputtering, and the insulation film is made of polyimide film, thick film printed resin film, silicon nitride film or silicon oxide film.
10. The manufacturing method of the NTC-based temperature-sensitive ceramic substrate chip temperature-compensated attenuator according to claim 1, wherein: the detailed manufacturing process of the chip temperature compensation attenuator comprises the following steps:
(1) Cleaning: selecting an NTC thermal sensitive ceramic substrate with a specific B value and polished on both sides, sequentially carrying out ultrasonic cleaning on the substrate by using a ceramic cleaning agent, acetone, alcohol and deionized water for 10min +/-2 min respectively, and then drying in an oven at 150 +/-10 ℃ for 120-180 min;
(2) Sputtering of the resistance film layer: preparing a resistance film layer on a polished surface on one side of the NTC thermal sensitive ceramic substrate by adopting a magnetron sputtering method, wherein the sputtering time is 20-60 min, and the thickness of the film layer is 0.05-1 mu m;
(3) Electrode layer sputtering: sputtering a TiW adhesion layer and an Au layer on a thermal sensitive ceramic substrate with a prepared resistance film layer in sequence by adopting a magnetron sputtering method, wherein the sputtering time of the Au layer is 40-60 min, and the thickness is about 2-4 mu m; the thickness of the titanium tungsten is about 150nm to 200nm;
(4) Primary photoetching: gluing; baking the mixture on a hot plate at the temperature of between 95 and 110 ℃ for 90s +/-10 s; exposing for 10s +/-3 s and developing; and etching the top gold layer and the titanium-tungsten layer. Removing the photoresist after the etching is finished, and scrubbing the product by using acetone;
(5) Secondary photoetching: after the electrode is etched, coating glue again, baking for 90s +/-10 s at the temperature of 95-110 ℃, exposing for 10s +/-3 s, developing for 45s +/-10 s, then etching the thin film resistor body, and finally removing the glue;
(6) Preparing a back insulating layer: preparing a polyimide film protective layer on the other polished surface of the NTC thermosensitive ceramic substrate by adopting a rotary coating mode, and baking for 90s +/-10 s at the temperature of 95-110 ℃; exposing for 35s +/-15 s, and post-baking; then curing in an oven at 250 +/-5 ℃ for 240-300 min;
(7) Scribing and cutting: and scribing and cutting the NTC thermal sensitive ceramic substrate by adopting a mechanical cutting method to obtain the chip temperature compensation attenuator with the size meeting the requirement.
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| CN116709638A (en) * | 2023-08-03 | 2023-09-05 | 合肥国家实验室 | Bus for superconducting quantum computer system |
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