CN115832065A - Back contact battery, manufacturing method thereof and photovoltaic module - Google Patents
Back contact battery, manufacturing method thereof and photovoltaic module Download PDFInfo
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L31/0216—Coatings
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a back contact cell, a manufacturing method thereof and a photovoltaic module, relates to the technical field of solar cells, and is used for simultaneously preventing electric leakage at a transverse interface and a longitudinal interface of a first doped semiconductor layer and a second doped semiconductor layer. The back contact battery includes: the semiconductor device comprises a silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer. The first passivation layer and the first doped semiconductor layer are sequentially stacked on a backlight surface of the silicon substrate. The second passivation layer and the second doped semiconductor layer are sequentially stacked on the backlight surface. The second passivation layer and the second doped semiconductor layer which are arranged in a stacked mode cover partial regions of the first passivation layer and the first doped semiconductor layer which are arranged in a stacked mode, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite. An insulating layer is located at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a back contact cell, a manufacturing method of the back contact cell and a photovoltaic module.
Background
The passivated back contact type solar cell refers to a solar cell which has a passivated contact structure, wherein a positive electrode and a negative electrode are positioned on the back surface of the cell, and the front surface is not shielded by a metal electrode. Because the passivated back contact solar cell has the advantages of large light absorption area, low carrier back recombination rate and the like, the passivated back contact solar cell is widely concerned by the photovoltaic academic and industrial fields and becomes the hot development direction of the high-efficiency solar cell technology.
However, in the conventional passivated back contact solar cell, when one of two types of passivated contact structures with opposite carrier collection types covers a partial region of the other type, the two types of passivated contact structures are difficult to be separated by a thinner passivation layer, the risk of leakage current is large, and the performance of the passivated back contact solar cell is further improved.
Disclosure of Invention
The invention aims to provide a back contact cell, a manufacturing method thereof and a photovoltaic module, which are used for simultaneously preventing electric leakage at a transverse interface and a longitudinal interface of a first doped semiconductor layer and a second doped semiconductor layer and are beneficial to improving the photoelectric conversion efficiency of the back contact cell.
In a first aspect, the present invention provides a back contact battery comprising: the silicon substrate is sequentially stacked on a first passivation layer and a first doped semiconductor layer on a backlight surface along the thickness direction of the silicon substrate. And a second passivation layer and a second doped semiconductor layer which are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate. The second passivation layer and the second doped semiconductor layer which are arranged in a stacked mode cover partial regions of the first passivation layer and the first doped semiconductor layer which are arranged in a stacked mode, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite. An insulating layer disposed on the backlight surface. An insulating layer is located at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer.
Under the condition of adopting the technical scheme, the first passivation layer and the first doped semiconductor layer are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate. The passivation contact structure formed by the first passivation layer and the first doped semiconductor layer can realize excellent interface passivation and carrier selective collection, and is beneficial to improving the photoelectric conversion efficiency of the back contact cell. Similarly, the passivation contact structure formed by the second passivation layer and the second doped semiconductor layer also has the beneficial effects of the first passivation layer and the first doped semiconductor layer, and the description thereof is omitted.
In addition, the second passivation layer and the second doped semiconductor layer which are stacked cover partial regions of the first passivation layer and the first doped semiconductor layer which are stacked. In addition, the back contact battery provided by the invention also comprises an insulating layer arranged on the backlight surface. The insulating layer is at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer. It is to be understood that the insulating layer may not only space the second passivation layer and the first doped semiconductor layer along the thickness direction of the silicon substrate, but also space the second passivation layer and the first doped semiconductor layer along a direction parallel to the backlight surface. In this case, the insulating layer can prevent carriers in the second doped semiconductor layer from entering the first doped semiconductor layer through the second passivation layer by a tunneling effect, and can also prevent carriers in the first doped semiconductor layer from entering the second doped semiconductor layer through the second passivation layer by a tunneling effect, that is, the insulating layer can prevent the carriers collected by the second doped semiconductor layer from being combined with the carriers collected by the first doped semiconductor layer with the opposite conductivity type, so that the leakage at the transverse interface and the longitudinal interface of the first doped semiconductor layer and the second doped semiconductor layer can be prevented at the same time, and the photoelectric conversion efficiency of the back contact cell can be improved.
As a possible implementation manner, the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.
With the above technical solution, in an actual manufacturing process, in order to form the first passivation layer and the first doped semiconductor layer only on a specific region of the backlight surface, patterning processing needs to be performed on the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer. Compared with the mode of realizing the patterning treatment by combining photoetching with wet etching and printing ink printing with wet etching, the method for realizing the patterning treatment by adopting the laser etching process has lower cost and is more suitable for mass production. Moreover, since the second passivation layer and the second doped semiconductor layer which are stacked cover partial regions of the first passivation layer and the first doped semiconductor layer which are stacked, the forming step of the first passivation layer and the first doped semiconductor layer which are stacked is earlier than the forming step of the second passivation layer and the second doped semiconductor layer which are stacked in the actual manufacturing process. Under the above conditions, because the amorphous silicon material is easy to form polycrystalline silicon or monocrystalline silicon at high temperature, and the tunneling passivation material and the polycrystalline silicon have relatively stable chemical properties at high temperature, compared with the stacked intrinsic amorphous silicon layer and the stacked doped amorphous silicon layer, the stacked tunneling passivation layer and the stacked doped polycrystalline silicon layer have smaller sensitivity to high-temperature laser thermal damage, and the influence on the passivation effect can be reduced during the laser film opening process, so that the process window is further increased, and the process difficulty is reduced.
In addition, the tunneling passivation layer and the doped polysilicon layer can be formed by deposition with a low-pressure chemical vapor deposition device. And the intrinsic amorphous silicon layer and the doped amorphous silicon layer are formed by deposition by using a chemical vapor deposition device. Therefore, because the cost of the low-pressure chemical vapor deposition equipment is lower than that of the chemical vapor deposition equipment, when the first passivation layer can also be a tunneling passivation layer and the first doped semiconductor layer can also be a doped polycrystalline silicon layer, a passivation material layer for manufacturing the first passivation layer and a doped semiconductor material layer for manufacturing the first doped semiconductor layer can be deposited through the low-pressure chemical vapor deposition equipment, so that the manufacturing cost of the back contact battery can be reduced.
As a possible implementation manner, the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer.
Under the condition of adopting the technical scheme, the intrinsic amorphous silicon layer has better passivation effect than a tunneling passivation layer. Based on this, compared with the case that the second passivation layer is a tunneling passivation layer and the second doped semiconductor layer is a doped polysilicon layer, when the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer is an intrinsic amorphous silicon layer, the recombination rate of carriers with opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell can be further improved.
As a possible implementation manner, the back contact battery further includes: and an aluminum oxide layer and a silicon nitride layer which are arranged on the light facing surface of the silicon substrate are sequentially stacked along the direction departing from the silicon substrate. Or, the back contact cell further comprises: and sequentially laminating a silicon oxide layer and a silicon nitride layer on a light facing surface of the silicon substrate along a direction departing from the silicon substrate.
By adopting the technical scheme, the aluminum oxide layer and the silicon nitride layer which are stacked can passivate the light facing surface, the recombination rate of carriers at the light facing surface is reduced, and the photoelectric conversion efficiency of the back contact cell is further improved. And the silicon nitride can play a role in antireflection, so that more light rays are favorably refracted into the silicon substrate from the light facing surface, and the utilization rate of the back contact battery to the light rays is further improved. On the basis, when a passivation layer of an amorphous silicon material is formed on the light facing surface with the small textured structure by adopting a deposition process, epitaxial growth is easy to occur on the top of the textured structure, so that the thickness of the part, positioned at the top of the textured structure, of the amorphous silicon material is larger than that of the part, positioned at the base of the textured structure, of the amorphous silicon material, the thicknesses of all areas of the passivation layer of the formed amorphous silicon material are inconsistent, the passivation effect of the passivation layer on the light facing surface is reduced, and the formation of other film layers on the light facing surface can be influenced. Compared with the passivation layer made of amorphous silicon materials, the passivation layer made of aluminum oxide materials cannot grow epitaxially when being deposited on the light facing surface of the small textured structure, so that the passivation effect of the passivation layer made of aluminum oxide materials is good, the textured surface of the light facing surface of the silicon substrate can be a textured surface with a small pyramid size, the textured surface with a small size has a better light trapping effect, and the light absorption of the silicon substrate is further improved. In addition, the beneficial effects of the silicon oxide layer and the silicon nitride layer stacked in the above-mentioned manner can be analyzed with reference to the beneficial effects of the aluminum oxide layer and the silicon nitride layer stacked in the above-mentioned manner, and details are not described herein again.
Furthermore, the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer can be deposited by using an atomic layer deposition device. And the intrinsic amorphous silicon layer is formed by deposition by using a chemical vapor deposition device. Based on this, since the cost of the atomic layer deposition apparatus is lower than that of the chemical vapor deposition apparatus, when an aluminum oxide layer (or a silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as the passivation antireflection layer, the aluminum oxide layer (or the silicon oxide layer) and the silicon nitride layer can be formed on the light-facing surface by deposition with the atomic layer deposition apparatus, so that the manufacturing cost of the back contact battery can be reduced.
As a possible implementation, the insulating layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence in a direction away from the silicon substrate. Or the insulating layer comprises a silicon oxide layer and a silicon nitride layer which are sequentially stacked along the direction deviating from the silicon substrate.
By adopting the technical scheme, the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer have good dielectric properties, the second passivation layer and the first doped semiconductor layer are separated by the insulating layer, the parallel resistance of the back contact battery can be further improved, and the electric leakage risk of the back contact battery is reduced. Furthermore, aluminum oxide, silicon nitride and silicon oxide can also be used to produce a film layer on the light-facing surface that has a passivating effect and/or an antireflection effect. Based on the above, when the insulating layer comprises the aluminum oxide layer and the silicon nitride layer which are arranged in a stacked mode, or the silicon oxide layer and the silicon nitride layer which are arranged in a stacked mode, the material of the insulating layer is the same as that of the passivation antireflection layer, so that the passivation antireflection layer can be formed on the light facing surface while the insulating layer is formed, the manufacturing process of the back contact battery is simplified, and the manufacturing efficiency of the back contact battery is improved.
As a possible implementation, the thickness of the insulating layer is 75nm to 125nm. The thickness of the insulating layer is within the range, so that partial carriers which are possibly collected by the second doped semiconductor layer and sequentially pass through the second passivation layer and the insulating layer through the tunneling effect to be combined with the carriers collected by the first doped semiconductor layer with the opposite conductivity type can be prevented, and the insulating layer is ensured to have good insulating performance. Meanwhile, the insulating layer not only separates the second passivation layer from the first doped semiconductor layer along the direction of the silicon substrate, but also separates the second passivation layer from the first doped semiconductor layer along the direction parallel to the backlight surface of the silicon substrate, so that the part of the insulating layer at the longitudinal junction of the second passivation layer and the first doped semiconductor layer, and the first doped semiconductor layer and the second doped semiconductor layer are distributed above the backlight surface along the direction parallel to the backlight surface. In this case, it can be understood that, when the thickness of the insulating layer is larger, the cross-sectional area of the portion of the insulating layer located at the longitudinal boundary between the second passivation layer and the first doped semiconductor layer is larger, and the surface area of the backlight surface is a fixed value, so when the thickness of the insulating layer is 75nm to 125nm, it is also possible to prevent the cross-sectional area of at least one of the first doped semiconductor layer and the second doped semiconductor layer from being reduced due to the larger thickness of the insulating layer, thereby affecting the carrier collection capability thereof, ensuring that carriers generated after the silicon substrate absorbs photons are timely led out by the first doped semiconductor layer and the second doped semiconductor layer, and further improving the photoelectric conversion efficiency of the back contact cell.
As a possible implementation manner, the light-facing surface of the silicon substrate is a textured surface. The width of the tower base of the suede is 1-3 μm.
Under the condition of adopting the technical scheme, in a certain range, the smaller the width of the tower base of the suede is, the better the light trapping effect of the suede is. Based on this, when the light facing surface of the silicon substrate is a textured surface, and the width of the tower base of the textured surface is 1 μm to 3 μm, the width of the tower base of the light facing surface is relatively small, and the light facing surface has a high light trapping effect. In this case, in an actual application process, an amorphous silicon material such as aluminum oxide and silicon oxide and a passivation reflection layer matched with the suede with a small tower footing width are formed on the light-facing surface, so that more light can be transmitted into the silicon substrate through the light-facing surface, and the photoelectric conversion efficiency of the back contact cell is further improved.
In a second aspect, the present invention also provides a photovoltaic module, which includes the back contact cell provided in the first aspect and its various implementations.
The beneficial effects of the second aspect and various implementation manners of the second aspect of the present invention can refer to the beneficial effect analysis of the first aspect and various implementation manners of the first aspect, and are not described herein again.
In a third aspect, the present invention also provides a method of manufacturing a back contact battery, the method comprising: first, a silicon substrate is provided. And then, forming a first passivation layer and a first doped semiconductor layer which are sequentially stacked on a backlight surface of the silicon substrate along the thickness direction of the silicon substrate. Next, an insulating layer is formed on the backlight surface. And forming a second passivation layer and a second doped semiconductor layer which are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate. The second passivation layer and the second doped semiconductor layer which are arranged in a stacked mode cover partial regions of the first passivation layer and the first doped semiconductor layer which are arranged in a stacked mode, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite. An insulating layer is located at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer.
For the beneficial effects of the third aspect of the present invention, reference may be made to the beneficial effect analysis of the first aspect, which is not described herein again.
As a possible implementation, forming a first passivation layer and a first doped semiconductor layer in a stacked arrangement includes: firstly, a passivation material layer covering the backlight surface and an intrinsic semiconductor material layer positioned on the passivation material layer are sequentially formed. Next, the intrinsic semiconductor material layer is subjected to a diffusion process so that the intrinsic semiconductor material layer forms a doped semiconductor material layer and a doped glass layer is formed on the doped semiconductor material layer. And then, removing part of the doped glass layer on the doped semiconductor material layer by adopting a laser etching process. Wherein the remaining portion of the doped glass layer forms a mask layer. And sequentially removing the part of the doped semiconductor material layer exposed outside the mask layer and the part of the passivation material layer exposed outside the mask layer under the mask action of the mask layer to form a first passivation layer and a first doped semiconductor layer which are stacked.
Under the condition of adopting the above technical solution, in an actual application process, when the intrinsic semiconductor material layer located on the passivation material layer is subjected to diffusion treatment, the intrinsic semiconductor material layer is converted into a doped semiconductor material layer, and a doped Glass layer is formed on a surface of the doped semiconductor material layer, where the doped Glass layer may be, for example, a Phosphorus Silicate Glass (PSG), a Boron Silicate Glass (BSG), or the like. In this case, after the laser etching process is used to remove part of the doped glass layer on the doped semiconductor material layer, the mask layer can be formed on the remaining part of the doped glass layer, so that patterning processing on the doped semiconductor material layer and the passivation material layer can be realized without additionally forming other mask layers such as silicon nitride and the like, the manufacturing process of the back contact battery is simplified, and meanwhile, the manufacturing cost of the back contact battery can be reduced.
As a possible implementation manner, after forming the first passivation layer and the first doped semiconductor layer which are stacked, before forming the insulating layer on the backlight surface, the method for manufacturing the back contact cell further includes: and removing the winding-plating doped glass layer, the winding-plating doped semiconductor material layer and the winding-plating passivation material layer which are positioned on the light-facing surface and the side surface of the silicon substrate. And then, under the action of the mask layer, texturing processing is carried out on the light facing surface of the silicon substrate, so that the light facing surface is textured. And removing the mask layer.
In the case of adopting the above technical scheme, as described above, in the texturing process, the mask layer used is obtained by patterning the doped glass layer formed on the doped semiconductor material layer in the diffusion process by using a laser etching process, and the mask layer such as silicon nitride and the like is not additionally formed by deposition and other processes after the first passivation layer and the first doped semiconductor layer which are stacked are obtained, so that the manufacturing process of the back contact cell can be further simplified, and the manufacturing cost of the back contact cell can be reduced.
As a possible realization, the thickness of the doped glass layer is 40nm to 60nm. In this case, the thickness of the doped glass layer is within the range, so that the problem that the protective effect of the mask layer formed by the remaining part of the doped glass layer is poor due to the small thickness of the doped glass layer, and the first doped semiconductor layer and the first passivation layer which are positioned below the doped glass layer are difficult to protect in corresponding operation can be prevented, the first doped semiconductor layer and the first passivation layer are ensured to have good film forming quality, and the yield of the back contact battery is improved. Meanwhile, the problems of reduction of manufacturing efficiency, increase of manufacturing cost and the like caused by the large thickness of the doped glass layer can be prevented, and the mass production of the back contact cell is favorably improved.
As a possible implementation manner, the diffusion time of the diffusion treatment is 60min to 120min, and the diffusion temperature is 800 ℃ to 900 ℃. The beneficial effect of the doped glass layer in this case is similar to that when the doped glass layer has a thickness of 40nm to 60nm, which can be referred to above and will not be described herein again.
As a possible implementation, forming a first passivation layer and a first doped semiconductor layer in a stacked arrangement includes: firstly, a passivation material layer covering the backlight surface and a doped semiconductor material layer positioned on the passivation material layer are sequentially formed. And then, patterning the doped semiconductor material layer and the passivation material layer by adopting a laser etching process to form a first passivation layer and a first doped semiconductor layer which are arranged in a stacked mode. The first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer. In this case, the beneficial effects of the first passivation layer being a tunneling passivation layer and the first doped semiconductor layer being a doped polysilicon layer can be analyzed as described above, and details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic longitudinal cross-sectional view of a structure of a passivated back contact solar cell of the related art;
FIG. 2 is a schematic longitudinal cross-sectional view of another structure of a passivated back contact solar cell of the related art;
fig. 3 is a first schematic structural diagram illustrating a manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 4 is a second schematic structural diagram illustrating a manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram three illustrating a manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a fourth process of manufacturing a back contact battery according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram five illustrating a manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 8 is a sixth schematic structural diagram in the manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram seven in the manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram eight illustrating a process of manufacturing a back contact battery according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram nine in the manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram ten illustrating a process of manufacturing a back contact battery according to an embodiment of the present invention;
fig. 13 is an eleventh schematic structural diagram in the manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 14 is a twelve schematic structural diagram in the manufacturing process of a back contact battery according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram thirteen in the manufacturing process of a back contact battery according to the embodiment of the present invention;
fig. 16 is a schematic structural diagram fourteen in the manufacturing process of the back contact battery according to the embodiment of the present invention.
Reference numerals: 11 is a silicon substrate, 12 is a passivation material layer, 121 is a first passivation layer, 13 is an intrinsic semiconductor material layer, 14 is a doped semiconductor material layer, 141 is a first doped semiconductor layer, 15 is a doped glass layer, 151 is a mask layer, 16 is an insulating material layer, 161 is an insulating layer, 17 is a second passivation layer, 18 is a second doped semiconductor layer, 19 is an aluminum oxide layer, 20 is a silicon nitride layer, 21 is a transparent conductive material layer, 211 is a first transparent conductive layer, 212 is a second transparent conductive layer, 22 is a first electrode, and 23 is a second electrode.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
The passivated back contact type solar cell refers to a solar cell which has a passivated contact structure, wherein the positive electrode and the negative electrode are positioned on the back surface of the cell, and the front surface is not shielded by a metal electrode. Because the passivated back contact solar cell has the advantages of larger light absorption area, lower carrier back recombination rate and the like, the passivated back contact solar cell is widely concerned by the photovoltaic academia and the industry and becomes the hot development direction of the high-efficiency solar cell technology.
Specifically, as shown in fig. 1 and 2, a passivated back contact solar cell in the related art generally includes a silicon substrate 11, a first passivated contact structure, and a second passivated contact structure. Wherein, along the direction parallel to the backlight surface of the silicon substrate 11, the first passivation contact structures and the second passivation contact structures are alternately distributed on the backlight surface. And the second passivation contact structure covers a partial region of the first passivation contact structure. Specifically, the first passivation contact structure and the second passivation contact structure each include a passivation layer and a doped semiconductor layer stacked in sequence along a direction away from the silicon substrate 11. Based on this, during the operation of the passivated back contact solar cell, the corresponding type of carriers may respectively pass through the passivation layers included in the first and second passivated contact structures by a tunneling effect and be conducted to the corresponding electrodes through the corresponding doped semiconductor layers included in the first and second passivated contact structures, thereby forming a photocurrent.
However, as shown in fig. 1 and 2, in order to reduce the tunneling resistance of carriers, the passivated back contact solar cell in the related art is generally designed such that the first passivated contact structure and the second passivated contact structure include a smaller thickness of the passivation layer. And the first and second passivation contact structures comprise doped semiconductor layers of opposite conductivity types. In this case, when the second passivation contact structure covers a partial region of the first passivation contact structure, even if the insulating layer is disposed at a longitudinal boundary of the first passivation contact structure and the second passivation contact structure along a thickness direction of the silicon substrate, the insulating layer can only separate the first passivation contact structure and the second passivation contact structure in the longitudinal direction, and at a lateral boundary of the first passivation contact structure and the second passivation contact structure, the first passivation contact structure and the second passivation contact structure are separated only by the passivation layer (for example, separated by the intrinsic semiconductor layer), however, it is difficult for the thinner passivation layer to achieve separation of carriers in the doped semiconductor layer of the first passivation contact structure and carriers in the doped semiconductor layer of the second passivation contact structure, resulting in a higher recombination rate of carriers of opposite conductivity types at the lateral interface of the first passivation contact structure and the second passivation contact structure, and there is a risk of electric leakage, which further affects performance of the passivated back contact solar cell to be further improved.
In order to solve the above technical problems, in a first aspect, an embodiment of the present invention provides a back contact battery. As shown in fig. 13, the back contact battery includes: a silicon substrate 11, a first passivation layer 121, a first doped semiconductor layer 141, a second passivation layer 17, a second doped semiconductor layer 18, and an insulating layer 161.
As shown in fig. 13, a first passivation layer 121 and a first doped semiconductor layer 141 are sequentially stacked on the back light surface of the silicon substrate 11 along the thickness direction of the silicon substrate 11. Along the thickness direction of the silicon substrate 11, a second passivation layer 17 and a second doped semiconductor layer 18 are sequentially stacked on the backlight surface. Wherein the stacked second passivation layer 17 and the stacked second doped semiconductor layer 18 cover a partial region of the stacked first passivation layer 121 and the stacked first doped semiconductor layer 141, and the conductivity types of the second doped semiconductor layer 18 and the first doped semiconductor layer 141 are opposite. The insulating layer 161 is disposed on the backlight surface. The insulating layer 161 is at least between the second passivation layer 17 and the first doped semiconductor layer 141 for spacing the second passivation layer 17 and the first doped semiconductor layer 141.
Specifically, the silicon substrate may be an N-type silicon substrate or a P-type silicon substrate in terms of conductivity type. In terms of structure, the specific structure of the silicon substrate can be set according to practical application scenarios. For example: as shown in fig. 3, the silicon substrate 11 may be a silicon substrate on which no film layer is formed and the backlight surface and the light-facing surface are both polished surfaces. Alternatively, as shown in fig. 13, the silicon substrate 11 may also be a silicon substrate without any film layer formed thereon and with a textured light-facing surface. Compared with a polishing surface, the textured structure has a good light trapping effect, so that more light rays can be refracted into the silicon substrate 11 from the textured surface under the condition that the light facing surface of the silicon substrate 11 is textured, and the photoelectric conversion efficiency of the back contact cell is improved. Specifically, under the condition that the light facing surface of the silicon substrate 11 is a textured surface, the width of the tower footing of the textured surface may be set according to actual requirements, and is not specifically limited herein.
For the first passivation layer and the first doped semiconductor layer, the material and the thickness of the first passivation layer and the first doped semiconductor layer, and the doping type and the doping concentration of the doping element in the first doped semiconductor layer may be set according to actual requirements, as long as the application can be applied to the back contact cell provided by the embodiment of the invention.
For example: the first passivation layer may be an intrinsic amorphous silicon layer, and the first doped semiconductor layer may be a doped amorphous silicon layer. At this time, the first passivation layer and the first doped semiconductor layer may constitute a hetero contact structure. Based on this, because the heterogeneous contact structure has a passivation effect superior to that of a tunneling passivation contact structure, under the condition that the first passivation layer and the first doped semiconductor layer which are arranged in a stacked mode form the heterogeneous contact structure, the carrier recombination rate at the interface of the silicon substrate and the first passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell is favorably improved.
Another example is: the first passivation layer may also be a tunneling passivation layer, and the first doped semiconductor layer may also be a doped polysilicon layer. In this case, in an actual manufacturing process, as shown in fig. 5 to 7, in order to form the first passivation layer 121 and the first doped semiconductor layer 141 only on a specific region of the backlight surface, it is necessary to perform a patterning process on the passivation material layer 12 that manufactures the first passivation layer 121 and the doped semiconductor material layer 14 that manufactures the first doped semiconductor layer 141. Compared with the mode of realizing the patterning treatment by combining photoetching with wet etching and printing ink printing with wet etching, the method for realizing the patterning treatment by adopting the laser etching process has lower cost and is more suitable for mass production. Further, as shown in fig. 13, since the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked, a forming step of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked is earlier than a forming step of the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked in an actual manufacturing process. Under the above conditions, because the amorphous silicon material is easy to form polycrystalline silicon or monocrystalline silicon at high temperature, and the tunneling passivation material and the polycrystalline silicon have relatively stable chemical properties at high temperature, compared with the stacked intrinsic amorphous silicon layer and the stacked doped amorphous silicon layer, the stacked tunneling passivation layer and the stacked doped polycrystalline silicon layer have smaller sensitivity to high-temperature laser thermal damage, and the influence on the passivation effect can be reduced during the laser film opening process, so that the process window is further increased, and the process difficulty is reduced.
In addition, the tunneling passivation layer and the doped polysilicon layer can be formed by deposition with a low-pressure chemical vapor deposition device. And the intrinsic amorphous silicon layer and the doped amorphous silicon layer need to be deposited by adopting a chemical vapor deposition device. Therefore, because the cost of the low-pressure chemical vapor deposition equipment is lower than that of the chemical vapor deposition equipment, when the first passivation layer can also be a tunneling passivation layer and the first doped semiconductor layer can also be a doped polycrystalline silicon layer, a passivation material layer for manufacturing the first passivation layer and a doped semiconductor material layer for manufacturing the first doped semiconductor layer can be deposited through the low-pressure chemical vapor deposition equipment, so that the manufacturing cost of the back contact battery can be reduced.
Specifically, the material of the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride. The specific material of the tunneling passivation layer can be set according to actual requirements.
For the second passivation layer and the second doped semiconductor layer, the material and the thickness of the second passivation layer and the second doped semiconductor layer, and the doping type and the doping concentration of the doping element in the second doped semiconductor layer may be set according to actual requirements. Wherein the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. Based on this, in practical application, the second doped semiconductor layer may be a P-type doped semiconductor layer doped with boron or other elements, and the first doped semiconductor layer may be an N-type doped semiconductor layer doped with phosphorus or other elements. Alternatively, the second doped semiconductor layer may be an N-type doped semiconductor layer, and the first doped semiconductor layer may be a P-type doped semiconductor layer.
In addition, the second passivation layer may be a tunneling passivation layer, and the second doped semiconductor layer may be a doped polysilicon layer. Alternatively, the second passivation layer may be an intrinsic amorphous silicon layer, and the second doped semiconductor layer may be a doped amorphous silicon layer.
It should be noted that, under the condition that the first passivation layer is a tunneling passivation layer, the second doped semiconductor layer is a doped polysilicon layer, the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer, patterning processing can be performed on the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer by using a laser etching process, so that the first passivation layer and the first doped semiconductor layer are ensured to have good film forming quality, a process window is increased, and meanwhile, the intrinsic amorphous silicon layer has a better passivation effect than the tunneling passivation layer. Based on this, compared with the case that the second passivation layer is a tunneling passivation layer and the second doped semiconductor layer is a doped polycrystalline silicon layer, when the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer is provided, the recombination rate of carriers with opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell can be further improved.
Furthermore, the area of the stacked second passivation layer and the stacked second doped semiconductor layer covering the stacked first passivation layer and the stacked first doped semiconductor layer may be set according to an actual application scenario, and is not specifically limited herein.
For the above insulating layer, the insulating layer may be a single-layer structure made of one or more insulating materials, or the insulating layer may be a multi-layer composite structure made of a plurality of insulating materials. Specifically, the specific structure of the insulating layer can be set according to actual requirements. The insulating material may be any material having insulating properties. In addition, the thickness of the insulating layer and the forming range of the insulating layer on the backlight surface can be set according to actual requirements, as long as the insulating layer can be at least positioned between the second passivation layer and the first doped semiconductor layer, and the second passivation layer and the first doped semiconductor layer can be spaced apart by the insulating layer.
As can be seen from the above, as shown in fig. 13, the insulating layer 161 may not only space the second passivation layer 17 and the first doped semiconductor layer 141 along the thickness direction of the silicon substrate 11, but also space the second passivation layer 17 and the first doped semiconductor layer 141 along the direction parallel to the backlight surface. In this case, the insulating layer 161 can prevent the carriers in the second doped semiconductor layer 18 from entering the first doped semiconductor layer 141 through the second passivation layer 17 by a tunneling effect, and can also prevent the carriers in the first doped semiconductor layer 141 from entering the second doped semiconductor layer 18 through the second passivation layer 17 by a tunneling effect, that is, the insulating layer 161 can prevent the carriers collected by the second doped semiconductor layer 18 from being combined with the carriers collected by the first doped semiconductor layer 141 with the opposite conductivity type, so as to prevent the leakage from occurring at the lateral interface and the longitudinal interface of the first doped semiconductor layer 141 and the second doped semiconductor layer 18, thereby being beneficial to improving the photoelectric conversion efficiency of the back contact cell.
As a possible implementation, the thickness of the insulating layer is 75nm to 125nm. In this case, the thickness of the insulating layer is within this range, so that it is possible to prevent a portion of carriers that may be collected by the second doped semiconductor layer from being recombined with carriers collected by the first doped semiconductor layer of the opposite conductivity type through the second passivation layer and the insulating layer in sequence by a tunneling effect due to the small thickness of the insulating layer, thereby ensuring that the insulating layer has good insulating properties. Meanwhile, as shown in fig. 13, the insulating layer 161 not only separates the second passivation layer 17 from the first doped semiconductor layer 141 along the thickness direction of the silicon substrate 11, but also separates the second passivation layer 17 from the first doped semiconductor layer 141 along the direction parallel to the backlight surface of the silicon substrate 11, so that the portion of the insulating layer 161 located at the longitudinal boundary between the second passivation layer 17 and the first doped semiconductor layer 141, and the second doped semiconductor layer 18 are distributed above the backlight surface along the direction parallel to the backlight surface. In this case, it can be understood that, when the thickness of the insulating layer 161 is larger, the cross-sectional area of the portion of the insulating layer 161 located at the longitudinal boundary between the second passivation layer 17 and the first doped semiconductor layer 141 is larger, and the surface area of the backlight surface is a fixed value, so when the thickness of the insulating layer 161 is 75nm to 125nm, it is also possible to prevent the cross-sectional area of one of the first doped semiconductor layer 141 and the second doped semiconductor layer 18 from being reduced due to the larger thickness of the insulating layer 161, and further affect the carrier collection capability thereof, and ensure that carriers generated after the silicon substrate 11 absorbs photons are guided out by the first doped semiconductor layer 141 and the second doped semiconductor layer 18 in time, thereby further improving the photoelectric conversion efficiency of the back contact cell.
Of course, the thickness of the insulating layer can be set to other suitable values according to different application requirements.
As a possible implementation manner, as shown in fig. 13, the back contact battery further includes: an alumina layer 19 and a silicon nitride layer 20 provided on a light-facing surface of the silicon substrate 11 are stacked in this order in a direction away from the silicon substrate 11. Or, the back contact cell further comprises: and sequentially laminating a silicon oxide layer and a silicon nitride layer on a light facing surface of the silicon substrate along a direction departing from the silicon substrate.
Specifically, the thicknesses of the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer may be set according to actual requirements, and are not specifically limited herein.
By adopting the technical scheme, the aluminum oxide layer and the silicon nitride layer which are stacked can passivate the light facing surface, the recombination rate of carriers at the light facing surface is reduced, and the photoelectric conversion efficiency of the back contact cell is further improved. And the silicon nitride layer can play a role in antireflection, so that more light rays can be favorably refracted into the silicon substrate from the light facing surface, and the utilization rate of the back contact battery to the light rays is further improved. On the basis, when a passivation layer of amorphous silicon material is formed on the light facing surface with the suede structure with smaller size by adopting a deposition process, epitaxial growth is easy to occur on the top of the suede structure, so that the thickness of the part of the amorphous silicon material positioned on the top of the suede structure is larger than that of the part of the amorphous silicon material positioned on the base of the suede structure, the thickness of each area of the passivation layer of the formed amorphous silicon material is inconsistent, the passivation effect of the passivation layer on the light facing surface is reduced, and the formation of other film layers on the light facing surface is influenced. Compared with the passivation layer made of amorphous silicon materials, the passivation layer made of aluminum oxide materials cannot grow epitaxially when the passivation layer made of aluminum oxide materials is deposited on the light facing surface of the small textured structure, so that the passivation effect of the passivation layer made of aluminum oxide materials is good, the textured surface of the light facing surface of the silicon substrate can be a textured surface with a pyramid size being small, the textured surface with the small size has a better light trapping effect, and the light absorption of the silicon substrate is further improved. In addition, the beneficial effects of the silicon oxide layer and the silicon nitride layer stacked in the above-mentioned manner can be analyzed with reference to the beneficial effects of the aluminum oxide layer and the silicon nitride layer stacked in the above-mentioned manner, and details are not described herein again. In addition, the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer can be deposited by using an atomic layer deposition device. And the intrinsic amorphous silicon layer is formed by deposition by using a chemical vapor deposition device. Based on this, since the cost of the atomic layer deposition apparatus is lower than that of the chemical vapor deposition apparatus, when an aluminum oxide layer (or a silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as the passivation antireflection layer, the aluminum oxide layer (or the silicon oxide layer) and the silicon nitride layer can be formed on the light-facing surface by deposition with the atomic layer deposition apparatus, so that the manufacturing cost of the back contact battery can be reduced.
It is noted that, in addition to the silicon oxide layer, the silicon nitride layer, and the aluminum oxide layer, the material forming the film layer having the passivation and antireflection functions on the light-facing surface may be provided as other suitable materials. For example: the film layer having the passivation and anti-reflection functions formed on the light-facing surface may further include at least one of a silicon oxynitride layer, a titanium oxide layer, and a silicon oxycarbide layer.
As a possible implementation, as shown in fig. 13, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer which are sequentially stacked in a direction away from the silicon substrate 11. Alternatively, the insulating layer 161 includes a silicon oxide layer and a silicon nitride layer which are stacked in this order in a direction away from the silicon substrate 11.
By adopting the technical scheme, the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer have good dielectric properties, the second passivation layer and the first doped semiconductor layer are separated by the insulating layer, the parallel resistance of the back contact battery can be further improved, and the electric leakage risk of the back contact battery is reduced. Furthermore, aluminum oxide, silicon nitride and silicon oxide can also be used to produce a film layer on the light-facing surface that has a passivating effect and/or an antireflection effect. Based on the above, when the insulating layer comprises the aluminum oxide layer and the silicon nitride layer which are arranged in a stacked mode, or the silicon oxide layer and the silicon nitride layer which are arranged in a stacked mode, the material of the insulating layer is the same as that of the passivation antireflection layer, so that the passivation antireflection layer can be formed on the light facing surface while the insulating layer is formed, the manufacturing process of the back contact battery is simplified, and the manufacturing efficiency of the back contact battery is improved.
It will be appreciated that in addition to the silicon oxide layer, the silicon nitride layer and the aluminum oxide layer, the insulating layer may be provided with other materials as described above for the film layer having the passivation and anti-reflection functions, in order to make the material of the insulating layer the same as that of the passivation anti-reflection layer.
As a possible implementation manner, as shown in fig. 13, the light-facing surface of the silicon substrate 11 is a textured surface. And the width of the tower base of the suede is 1-3 μm.
Under the condition of adopting the technical scheme, in a certain range, the smaller the width of the tower base of the suede is, the better the light trapping effect of the suede is. Based on this, when the light facing surface of the silicon substrate is a textured surface, and the width of the tower base of the textured surface is 1 to 3 μm, the width of the tower base of the light facing surface is relatively small, and the light facing surface has a high light trapping effect, so that the photoelectric conversion efficiency of the back contact cell can be further improved.
In the conventional heterojunction back contact cell, the passivation layer formed on the light-facing surface is usually an amorphous silicon layer. Moreover, as mentioned above, in order to ensure the passivation effect of the amorphous silicon layer on the light-facing surface to the light-facing surface, it is usually necessary to form the amorphous silicon layer on the textured structure with a relatively large width of the tower footing. In a certain range, the larger the width of the tower base of the suede is, the poorer the light trapping effect of the suede is. Accordingly, the higher the reflectivity of the light-facing surface. Therefore, in the existing heterojunction back contact battery, the compatibility between the amorphous silicon passivation layer positioned on the light facing surface and the suede with small tower footing width is poor, and the reflectivity of the light facing surface to light rays is difficult to reduce while the passivation effect of the light facing surface is improved. In this case, in an actual application process, when the intrinsic amorphous silicon layer and the doped amorphous silicon layer which are stacked are formed on the backlight surface of the back contact cell provided in the embodiment of the present invention, the passivation reflection layer which is formed on the backlight surface and is made of amorphous silicon materials such as aluminum oxide and silicon oxide and is matched with the textured surface with a small tower footing width may be formed, so that not only the passivation effect of the backlight surface may be improved, but also more light may be transmitted into the silicon substrate through the backlight surface, and the photoelectric conversion efficiency of the back contact cell provided in the embodiment of the present invention may be further improved.
In some cases, as shown in fig. 16, the back contact cell provided by the embodiment of the present invention may further include a first transparent conductive layer 211, a second transparent conductive layer 212, a first electrode 22, and a second electrode 23. The first transparent conductive layer 211 is at least formed on the first doped semiconductor layer 141, and the first electrode 22 is located on a portion of the first transparent conductive layer 211 corresponding to the first doped semiconductor layer 141, so as to guide out carriers collected by the first doped semiconductor layer 141. The second transparent conductive layer 212 is formed on the second doped semiconductor layer 18, and the second transparent conductive layer 212 and the first transparent conductive layer 211 are insulated from each other. The second electrode 23 is located on the second transparent conductive layer 212 to facilitate the conduction of carriers collected by the second doped semiconductor layer 18.
The first transparent conductive layer or the second transparent conductive layer can be made of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, indium hydroxide and the like. The thicknesses of the first transparent conductive layer and the second transparent conductive layer may be set according to actual requirements, and are not specifically limited herein. The first electrode and the second electrode may be made of conductive materials such as silver, aluminum, copper, nickel, and the like.
In a second aspect, embodiments of the present invention further provide a photovoltaic module, where the photovoltaic module includes the back contact cell provided in the first aspect and its various implementation manners.
The beneficial effects of the second aspect and various implementation manners of the second aspect of the present invention can refer to the beneficial effect analysis of the first aspect and various implementation manners of the first aspect, and are not described herein again.
In a third aspect, the embodiment of the invention also provides a manufacturing method of the back contact battery. The manufacturing process will be described below with reference to cross-sectional views in the manufacturing process of the back contact battery shown in fig. 3 to 16. Specifically, the manufacturing method of the back contact battery comprises the following steps:
first, as shown in fig. 1, a silicon substrate 11 is provided. The detailed structure of the silicon substrate 11 can be referred to the above, and is not described herein again.
In the practical application process, the doped silicon substrate can be polished in a tank-type cleaning device by using an alkaline cleaning solution such as KOH and the like to obtain the silicon substrate. In this case, compared with an untreated bare silicon substrate, the back light surface and the light facing surface of the polished silicon substrate are both flat polished surfaces, so that a structure meeting the process requirements can be conveniently formed on the basis of the flat polished surfaces, and the yield of back contact batteries is improved.
As shown in fig. 7, a first passivation layer 121 and a first doped semiconductor layer 141 sequentially stacked on a back surface of the silicon substrate 11 are formed along a thickness direction of the silicon substrate 11. Specifically, reference may be made to the foregoing for information such as the material and thickness of the first passivation layer 121 and the first doped semiconductor layer 141, which is not described herein again.
Illustratively, the forming of the first passivation layer and the first doped semiconductor layer in a stacked arrangement as described above may comprise the steps of: as shown in fig. 4, a passivation material layer 12 covering the backlight surface and an intrinsic semiconductor material layer 13 on the passivation material layer 12 are sequentially formed. As shown in fig. 5, the intrinsic semiconductor material layer is subjected to a diffusion process such that the intrinsic semiconductor material layer forms a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the doped semiconductor material layer 14. And then, removing part of the doped glass layer on the doped semiconductor material layer by adopting a laser etching process. Wherein the remaining portion of the doped glass layer forms a mask layer. Finally, as shown in fig. 6 and 7, under the mask action of the mask layer 151, the portion of the doped semiconductor material layer exposed outside the mask layer and the portion of the passivation material layer exposed outside the mask layer are sequentially removed, and the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked are formed.
In practical applications, the formation processes of the first passivation layer and the first doped semiconductor layer may be determined according to the materials of the two layers. For example: in the case that the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is doped polysilicon, as shown in fig. 4, a passivation material layer 12 covering the back surface and an intrinsic semiconductor material layer 13 on the passivation material layer 12 may be sequentially formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. Wherein, in the process of forming the passivation material layer 12 and the intrinsic semiconductor material layer 13, a wraparound passivation material layer and a wraparound intrinsic semiconductor material layer are also formed on the side surface and the light facing surface of the silicon substrate 11. Next, the intrinsic semiconductor material layer 13 is subjected to diffusion treatment by a diffusion apparatus. Specifically, as shown in fig. 5, when the intrinsic semiconductor material layer on the passivation material layer 12 is subjected to a diffusion process, the intrinsic semiconductor material layer is converted into a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the surface of the doped semiconductor material layer 14. The processing conditions of the diffusion process may be determined according to the doping concentration of the doping element in the first doped semiconductor layer 141, the thickness and the degree of densification of the doped glass layer 15 to be formed, and the actual application scenario, and are not specifically limited herein. Of course, after the diffusion treatment, the spin-on intrinsic semiconductor material layer is also formed into a spin-on doped semiconductor material layer, and a spin-on doped glass layer is formed on the spin-on doped semiconductor material layer. Then, after patterning the doped glass layer 15 by using a laser etching process, a mask layer may be formed on the remaining portion of the doped glass layer. The mask layer covers the part of the doped semiconductor material layer corresponding to the first doped semiconductor layer. As shown in fig. 6, under the mask action of the mask layer 151, the doped semiconductor material layer and the passivation material layer may be patterned by using a laser etching process, a wet etching process, a dry etching process, or the like, so as to form the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked.
It is noted that the mask layer used in the patterning of the doped semiconductor material layer and the passivation material layer is obtained by patterning the doped glass layer. In other words, the patterning treatment of the doped semiconductor material layer and the passivation material layer can be realized without additionally forming other mask layers such as silicon nitride and the like, so that the manufacturing process of the back contact cell is simplified, and the manufacturing cost of the back contact cell can be reduced.
Specifically, the specific material of the doped glass layer may be determined according to the material and doping type of the first doped semiconductor layer. For example: when the first doped semiconductor layer is an N-type doped polycrystalline silicon layer doped with phosphorus, the doped glass layer is a phosphorosilicate glass layer. Another example is: when the first doped semiconductor layer is a P-type doped polysilicon layer doped with boron, the doped glass layer is a borosilicate glass layer.
In addition, the thickness of the doped glass layer can be set according to actual requirements, as long as the mask layer formed by the doped glass layer has a corresponding mask effect.
Illustratively, the doped glass layer may have a thickness of 40nm to 60nm. For example: the thickness of the doped glass layer may be 40nm, 45nm, 50nm, 55nm or 60nm. In this case, the thickness of the doped glass layer is moderate, so that the difficulty in protecting the first doped semiconductor layer and the first passivation layer positioned below the doped glass layer in corresponding operation due to poor protection effect of the mask layer formed by the residual part of the doped glass layer due to the small thickness of the doped glass layer can be prevented, the first doped semiconductor layer and the first passivation layer are ensured to have good film forming quality, and the yield of the back contact battery is improved. Meanwhile, the problems of reduction of manufacturing efficiency, increase of manufacturing cost and the like caused by the large thickness of the doped glass layer can be prevented, and the mass production of the back contact cell is favorably improved.
In addition, the diffusion time of the diffusion treatment can be 60min to 120min, and the diffusion temperature can be 800 ℃ to 900 ℃. For example: the diffusion time may be 60min, 70min, 80min, 90min, 100min, 110min or 120min. The diffusion temperature may be 810 ℃, 820 ℃, 830 ℃, 840 ℃, 850 ℃, 860 ℃, 870 ℃, 880 ℃, 890 ℃ or 900 ℃.
It is understood that the diffusion temperature and the diffusion time affect the thickness of the doped glass layer formed during the diffusion process and the compactness of the doped glass layer. Specifically, in a certain range, the longer the diffusion time and the higher the diffusion temperature, the greater the thickness and the higher the density of the formed doped glass layer, and accordingly, the stronger the masking effect of the mask layer formed through the doped glass layer. Conversely, within a certain range, the shorter the diffusion time and the lower the diffusion temperature, the smaller the thickness and the lower the density of the doped glass layer formed, and accordingly the weaker the masking effect of the mask layer formed by the doped glass layer. In this case, when the diffusion time is 60min to 120min and the diffusion temperature is 800 ℃ to 900 ℃, it is possible to prevent the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect in the corresponding operation due to the short diffusion time and the low diffusion temperature, ensure the first doped semiconductor layer and the first passivation layer have good film formation quality, and improve the yield of the back contact cell. Meanwhile, the problems of reduction of manufacturing efficiency, increase of manufacturing cost and the like caused by long diffusion time and high diffusion temperature can be prevented, and the mass production of the back contact battery is favorably improved.
Besides the intrinsic semiconductor material layer is subjected to diffusion treatment to form the doped semiconductor material layer, the doped semiconductor material layer can be formed by ion implantation, doping source coating advancement and other processes. The forming process of the doped semiconductor material layer can be selected according to the requirements of practical application scenes.
In addition, as described above, in the case that the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is a doped polysilicon layer, the doped polysilicon layer may be formed by a plasma enhanced chemical vapor deposition process in addition to the low pressure chemical vapor deposition process and the diffusion process. In addition, the doped polysilicon layer can be crystallized by in-situ annealing to reduce the stress in the doped polysilicon layer and improve the film forming quality of the doped polysilicon layer.
Further, as described above, the first passivation layer may be a tunneling passivation layer, and the first doped semiconductor layer may be a doped polysilicon layer. Based on this, as shown in fig. 5, after the passivation material layer 12 covering the backlight surface and the doped semiconductor material layer 14 on the passivation material layer 12 are sequentially formed, as shown in fig. 6, the doped semiconductor material layer and the passivation material layer may be patterned by using a laser etching process to form the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked. In this case, the beneficial effects of the first passivation layer 121 being a tunneling passivation layer and the first doped semiconductor layer 141 being a doped polysilicon layer can be referred to for analysis, and are not described herein again.
For example, as mentioned above, the light facing surface of the silicon substrate may be a polished surface or a textured surface. The manufacturing method of the back contact cell comprises the following steps of forming a first passivation layer and a first doped semiconductor layer which are arranged in a stacked mode under the condition that the light facing surface of a silicon substrate is a textured surface and the mask layer is formed on the first doped semiconductor layer, and before subsequent operation, wherein the manufacturing method of the back contact cell further comprises the following steps: as shown in fig. 7, the glass layer of the spin-on doped glass 5, the layer of the spin-on doped semiconductor material and the layer of the spin-on passivation material on the light-facing surface and the side surfaces of the silicon substrate 11 are removed. Illustratively, a chain type cleaning apparatus may be employed, an
And removing the winding-plated doped glass layer, the winding-plated doped semiconductor material layer and the winding-plated passivation material layer in a mode that a roller floats on liquid or water. Next, as shown in fig. 8, under the mask action of the mask layer 151, texturing is performed on the light-facing surface of the silicon substrate 11 so that the light-facing surface is textured. Wherein, the portion of the backlight surface exposed outside the mask layer 151 will also be exposed
Forming a suede. In addition, the solution used in the texturing process and the processing conditions may be determined according to the actual application scenario, and 0 is not specifically limited herein. Next, as shown in fig. 9, the mask layer 151 may be removed using an HF solution. The concentration of the HF solution, and the removal time can be set according to actual requirements.
In the case of the foregoing technical solution, as described above, in the texturing process, the mask layer is formed by patterning the doped glass layer formed on the doped semiconductor material layer in the diffusion process by using a laser etching process
The obtained treatment is not a mask layer such as silicon nitride formed by 5 processes such as deposition after the first passivation layer and the first doped semiconductor layer which are arranged in a stacked manner are obtained, so that the manufacturing process of the back contact battery can be further simplified, and the back contact power is reduced
The manufacturing cost of the cell.
As described above, the back contact battery manufactured by the manufacturing method according to the embodiment of the present invention includes:
the semiconductor device comprises a silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer. It is composed of
As shown in fig. 13, the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked. And, the insulating layer 161 is at least on the second passivation
Between the layer 17 and the first doped semiconductor layer 141 for spacing the second passivation layer 17 from the first doped semiconductor layer 141. In the above case, as shown in fig. 11, after the first passivation layer 121 and the first doped semiconductor layer 141 are formed in a stacked manner and before the second passivation layer and the second doped semiconductor layer are formed in a stacked manner, the method for manufacturing the back contact cell further includes the steps of: an insulating layer is formed on the backlight surface.
As shown in fig. 10, a plasma enhanced atomic layer deposition process may be used to form a cap on the back side
A layer of insulating material 16 on the smooth surface and the first doped semiconductor layer 141. Next, as shown in fig. 11, the insulating material layer 16 may be patterned by a laser etching process or the like to expose a region where the backlight surface contacts with a second passivation layer 17 formed later. Wherein an insulating-material layer 16 covers the first passivation layer 121 and the first doping half arranged one above the other
Portions of the corresponding regions of the conductor layer 141 form insulating layers. The corresponding regions are regions where the first passivation layer 121 and the first 0-doped semiconductor layer 141, which are stacked, are adjacent to the second passivation layer and the second doped semiconductor layer, which are stacked.
It should be noted that, in the case of performing patterning processing on the insulating material layer by using a laser etching process, after a region where the backlight surface is in contact with a subsequently formed second passivation layer is exposed, the surface of the region damaged by high-temperature laser etching may be cleaned and repaired by using a wet etching process under the action of a mask of the remaining portion of the insulating material layer, so that the defect recombination rate of carriers at the interface is reduced, and simultaneously, the compactness of the second passivation layer formed on the region may be improved, the passivation effect of the second passivation layer on the region is further improved, and the photoelectric conversion efficiency of the back contact cell is improved.
As shown in fig. 13, a second passivation layer 17 and a second doped semiconductor layer 18, which are sequentially stacked on the back light surface, are formed along the thickness direction of the silicon substrate 11. Wherein the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked, and the conductivity types of the second doped semiconductor layer 18 and the first doped semiconductor layer 141 are opposite. Specifically, reference may be made to the foregoing information about the material, the thickness, and the like of the second passivation layer 17 and the second doped semiconductor layer 18, which is not described herein again.
In actual practice, as shown in fig. 12, a passivation material and a doped semiconductor material may be formed in sequence overlying the backlight surface and the remaining portions of the insulating material layer 16 using a chemical vapor deposition process or the like. Next, as shown in fig. 13, the passivation material and the doped semiconductor material may be patterned by using a laser etching process or the like, so that the remaining passivation material forms the second passivation layer 17 and the remaining doped semiconductor material forms the second doped semiconductor layer 18. Finally, the remaining portion of the insulating material layer 16 may be patterned by wet etching or the like under the mask action of the second doped semiconductor layer 18 to expose a portion of the first doped semiconductor layer 141. Wherein the remaining insulating material layer forms an insulating layer 161.
In some cases, as described above, when the manufactured back contact cell further includes the first transparent conductive layer, the second transparent conductive layer, the first electrode, and the second electrode, as shown in fig. 14, a transparent conductive material layer 21 covering the first doped semiconductor layer 141 and the second doped semiconductor layer 18 may be formed by using a physical vapor deposition process or the like. Next, as shown in fig. 15, an insulating trench may be formed through the transparent conductive layer, the second doped semiconductor layer 18 and the second passivation layer 17 using a laser etching process or the like to separate a portion of the transparent conductive material layer on the first doped semiconductor layer 141 from a portion of the transparent conductive material layer on the second doped semiconductor layer 18. The transparent conductive material layer at least forms a first transparent conductive layer 211 on the first doped semiconductor layer 141, and the transparent conductive material layer forms a second transparent conductive layer 212 on the second doped semiconductor layer 18. Finally, as shown in fig. 16, a first electrode 22 on the first transparent conductive layer 211 and a second electrode 23 on the second transparent conductive layer 212 may be formed by a screen printing process or the like.
The invention also provides the following specific examples to further illustrate the manufacturing method of the back contact battery of the invention, and the specific operation steps are as follows:
example 1:
the first step is as follows: and putting the N-type silicon wafer or the P-type silicon wafer into a groove type polishing and cleaning machine for polishing. Wherein the polishing solution is a KOH solution having a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81 ℃ to 87 ℃. The process time is 290s to 310s. After the polishing process, the surface appearance of the silicon substrate is a square structure with the size of 19-23 mu m, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40-44%.
The second step is that: a layer of tunnel oxide material overlying the back side of the silicon substrate and a layer of intrinsic polysilicon material overlying the layer of tunnel oxide material are formed in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace. Wherein the thickness of the tunneling oxide material layer is 1.2nm to 1.8nm, and the thickness of the intrinsic polycrystalline silicon material layer is 70nm to 170nm. In addition, a winding-plating passivation material layer and a winding-plating polysilicon material layer are sequentially formed on the side face and the light facing surface of the silicon substrate.
The third step: the intrinsic polysilicon material (Poly) layer is phosphorus doped in a phosphorus diffusion furnace such that the intrinsic polysilicon material layer forms an N-type doped polysilicon material layer. The diffusion sheet resistance of the N-type doped polysilicon material layer is 70-110 omega/sq. After diffusion treatment, phosphorosilicate glass layers are formed on the N-type doped polycrystalline silicon material layer and the winding-plated polycrystalline silicon material layer.
The fourth step: and patterning the part of the phosphosilicate glass layer corresponding to the backlight surface, the tunneling oxide material layer and the N-type doped polycrystalline silicon material layer by using a laser etching process to expose the region of the backlight surface corresponding to the P + region. And the rest part of the tunneling oxide material layer forms a first passivation layer, and the rest part of the N-type doped polycrystalline silicon material layer forms a first doped semiconductor layer. And forming a mask layer on the part of the phosphorosilicate glass layer, which is positioned on the first doped semiconductor layer.
The fifth step: in a chain type cleaning machine, the light facing surface of a silicon substrate faces downwards and enters an HF groove, and by means of a cleaning mode of a roller liquid carrying mode or a water floating mode, the parts of a phosphorosilicate glass layer, which are positioned on the side surface and the light facing surface of the silicon substrate, and a winding-plating passivation material layer and a winding-plating polycrystalline silicon material layer are removed through HF solution with the concentration of 9.5% -10.5% at normal temperature. Wherein the removal time is 55s to 65s. And then, putting the silicon substrate with the first passivation layer, the first doped semiconductor layer and the mask layer into a groove type cleaning machine for alkali texturing. Wherein the texturing solution comprises a KOH solution with the concentration of 2.5 percent to 3.5 percent and a texturing additive solution. The temperature of the texturing solution is 80-84 ℃, and the process time is 570-630 s. The etching amount is 0.5g to 0.7g, and the reflection rate of the light facing surface of the silicon substrate after the texturing treatment is 9 percent to 11 percent. The width of the tower base of the light facing surface is 1-3 mu m of small suede microstructure. At this time, the P + region of the backlight surface and the light facing surface are simultaneously finished with texturing processing. And finally, entering an HF groove to remove the mask layer, wherein the concentration of the HF solution is 9.5-10.5%, and treating for 95-105 s at normal temperature.
And a sixth step: in a Plasma Enhanced Atomic Layer Deposition (PEALD) apparatus, an aluminum oxide Layer and a silicon nitride Layer are sequentially deposited on a back surface and a light-facing surface. The thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm.
The seventh step: and using a laser to pattern the aluminum oxide layer and the silicon nitride layer on the backlight surface so as to remove the parts of the aluminum oxide layer and the silicon nitride layer on the P + region. The patterning process is designed corresponding to the silk screen pattern, and the laser type can be selected from green nanosecond, ultraviolet picosecond, green picosecond and ultraviolet nanosecond.
Eighth step: and carrying out a polishing process in a groove type polishing and cleaning machine. The polishing solution is 5.5 to 6.5 percent KOH solution, the temperature of the polishing solution is 81 to 87 ℃, and the process time is 170 to 190 seconds, so as to remove the laser damage generated in the seventh step. And meanwhile, carrying out laser grooving area polishing treatment. Finally, treatment was carried out for 25s to 35s in an HF solution at a concentration of 1% by weight.
The ninth step: in the chemical vapor deposition equipment, an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer which cover the backlight surface are sequentially formed. Wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the P-type doped amorphous silicon material layer is 10nm to 30nm.
The tenth step: and patterning the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer by using a laser, so that the remaining part of the intrinsic amorphous silicon material layer forms a second passivation layer, and the remaining part of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be selected from green nanosecond, ultraviolet picosecond, green picosecond and ultraviolet nanosecond.
The eleventh step: in the chain type cleaning machine, the back surface of the silicon substrate is faced downwards to enter an HF groove. Wherein the concentration of the HF solution is 29-31%, and the HF solution is treated at normal temperature for 175-185 s, and the cleaning mode is a roller liquid-carrying mode or a water floating mode. And after the laser etching treatment, removing the exposed parts of the aluminum oxide layer and the silicon nitride layer on the backlight surface to expose partial regions of the first doped semiconductor layer. And finally, sequentially entering a water tank and a drying tank to respectively clean and dry. Wherein the rest parts of the aluminum oxide layer and the silicon nitride layer on the backlight surface form an insulating layer.
The twelfth step: in a physical vapor deposition apparatus, a layer of transparent conductive material is formed overlying a backlight surface. The thickness of the transparent conductive material layer is 60nm to 100nm.
And a thirteenth step of: and removing the local transparent conductive material layer, the second doped semiconductor layer and the second passivation layer by using a laser etching process so as to realize the insulation of the N + region and the P + region.
The fourteenth step is that: the first electrode and the second electrode are formed by screen printing or the like. The resulting structure is shown in fig. 16.
Further, the invention also provides a back contact battery manufactured by the following comparative example, which comprises the following specific operation steps:
comparative example 1:
the first step is as follows: and putting the N-type silicon wafer or the P-type silicon wafer into a groove type polishing cleaning machine for polishing. Wherein the polishing solution is a KOH solution having a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81 ℃ to 87 ℃. The process time is 290s to 310s. After the polishing process, the surface appearance of the silicon substrate is a square structure with the size of 19-23 μm, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40-44%.
The second step is that: and forming a first silicon nitride layer covering the backlight surface of the silicon substrate by using a plasma enhanced chemical vapor deposition device. The first silicon nitride layer has a thickness of 190nm to 210nm and a refractive index of 2.3% to 2.5%. Wherein, the side surface and the light facing surface of the silicon substrate are provided with a silicon nitride layer.
The third step: in the tank cleaner, a silicon substrate formed with a first silicon nitride layer and a silicon substrate around which the silicon nitride layer is plated is put into an HF tank. Wherein the concentration of the HF solution is 0.5% to 1.5%. And treating at normal temperature for 25-35 s to remove the silicon nitride layer. And then, the silicon substrate with the first silicon nitride layer formed on the backlight surface enters an alkali tank for texturing treatment. The texturing solution includes a KOH solution having a concentration of 2% to 3%, and a texturing additive solution. The temperature of the texturing solution is 80 ℃ to 84 ℃. The process time is 760s to 800s. Then, the mixture enters a container filled with HNO 3 And performing suede smoothing treatment in the tank with HF mixed solution. The mixture ratio of the mixed solution is HNO 3 HF = 1. The total etching amount is 1.7g to 1.9g after the suede surface smoothing treatment. The reflectivity of the light-facing surface of the silicon substrate is 11 to 13 percent. And the width of the tower footing on the light facing surface is 3-5 mu m of a large matte microstructure. Finally, in an HF bath with a concentration of 8% by weight, and treated at normal temperature for 290s to 310s to remove the first silicon nitride layer remaining on the backlight surface.
The fourth step: in the chemical vapor deposition equipment, a first intrinsic amorphous silicon material layer, a phosphorus-doped N-type amorphous silicon material layer, a second silicon nitride layer and a second intrinsic amorphous silicon material layer are sequentially formed to cover the backlight surface. Wherein the thickness of the first intrinsic amorphous silicon material layer is 5nm to 20nm, the thickness of the N-type doped amorphous silicon material layer is 10nm to 30nm, the thickness of the second silicon nitride layer is 170nm to 230nm, and the thickness of the second intrinsic amorphous silicon material layer is 10nm to 30nm.
The fifth step: the second intrinsic amorphous silicon material layer is patterned using a laser to expose the P + region. The laser type can be selected from green light nanosecond, ultraviolet picosecond, green light picosecond and ultraviolet nanosecond;
and a sixth step: in the groove type cleaning equipment, a silicon substrate formed with a first intrinsic amorphous silicon material layer, an N-type doped amorphous silicon material layer, a second silicon nitride layer and a second intrinsic amorphous silicon material layer enters an HF groove, the concentration of HF solution is 7.5-8.5%, and the silicon substrate is treated for 190-210 s at normal temperature to remove the exposed part of the second silicon nitride layer. And then, etching the substrate in an alkali groove to remove the exposed parts of the first intrinsic amorphous silicon material layer and the N-type doped amorphous silicon material layer, so that a first passivation layer is formed on the rest part of the first intrinsic amorphous silicon material layer, and a first doped semiconductor layer is formed on the N-type doped amorphous silicon material layer. Wherein the etching solution comprises: KOH in a concentration of 0.4% to 0.6%, and H in a concentration of 0.1% to 0.2% 2 O 2 The temperature of the solution and the etching solution is 25 ℃, and the process time is 390 s-410 s.
The seventh step: in the chemical vapor deposition equipment, a third intrinsic silicon material layer and a P-type doped amorphous silicon material layer doped with boron are sequentially formed to cover the backlight surface. And a fourth intrinsic amorphous silicon material layer and a third silicon nitride layer are sequentially formed on the light facing surface. The thickness of the third intrinsic amorphous silicon material layer is 5nm to 30nm, the thickness of the p-type doped amorphous silicon material layer is 10nm to 25nm, the thickness of the fourth intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the third silicon nitride layer is 80nm to 105nm.
Eighth step: and patterning the third intrinsic silicon material layer and the P-type doped amorphous silicon material layer on the backlight surface by using a laser, so that the rest part of the third intrinsic silicon material layer forms a second passivation layer, and the rest part of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be selected from green nanosecond, ultraviolet picosecond, green picosecond and ultraviolet nanosecond.
The ninth step: and removing the exposed part of the second silicon nitride layer by using an HF solution to expose a partial region of the first doped semiconductor layer and form an insulating layer on the part of the second silicon nitride layer on the first doped semiconductor layer. Wherein the concentration of the HF solution is 7-9%, and the HF solution is treated at normal temperature for 380-420 s.
The tenth step: in a chemical vapor deposition apparatus, a layer of transparent conductive material is formed overlying a backlight surface. The thickness of the transparent conductive material layer is 60nm to 100nm.
The eleventh step: and etching the transverse junction of the first doped semiconductor layer and the second doped semiconductor layer by using a laser, and removing the local transparent conductive material layer, the local second passivation layer and the local second doped semiconductor layer, so that a first transparent conductive layer is formed on the part of the transparent conductive material layer on the first doped semiconductor layer, and a second transparent conductive layer is formed on the part of the transparent conductive material layer on the second doped semiconductor layer.
The twelfth step: the first electrode and the second electrode are formed by screen printing or the like. The resulting structure is shown in fig. 1.
Comparative example 2:
the first step is as follows: and putting the N-type silicon wafer or the P-type silicon wafer into a groove type polishing cleaning machine for polishing. Wherein the polishing solution is a KOH solution having a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81 ℃ to 87 ℃. The process time is 290s to 310s. After the polishing process, the surface appearance of the silicon substrate is a square structure with the size of 19-23 μm, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40-44%.
The second step is that: and forming a tunneling oxide material layer covering the backlight surface of the silicon substrate and an intrinsic polycrystalline silicon material layer positioned on the tunneling oxide material layer in a low-pressure chemical vapor deposition furnace. Wherein the thickness of the tunneling oxide material layer is 1.2nm to 1.8nm, and the thickness of the intrinsic polycrystalline silicon material layer is 70nm to 170nm. In addition, a winding-plating passivation material layer and a winding-plating polysilicon material layer are sequentially formed on the side face and the light facing surface of the silicon substrate.
The third step: and in a phosphorus diffusion furnace, carrying out phosphorus doping on the intrinsic polycrystalline silicon material layer so that the intrinsic polycrystalline silicon material layer forms an N-type doped polycrystalline silicon material layer. The diffusion sheet resistance of the N-type doped polysilicon material layer is 70-110 omega/sq. After diffusion treatment, phosphorosilicate glass layers are formed on the N-type doped polycrystalline silicon material layer and the winding-plated polycrystalline silicon material layer.
The fourth step: and forming a silicon nitride layer covering the backlight surface by using a plasma chemical vapor deposition device. The thickness of the silicon nitride layer is 40nm to 60nm, and the refractive index of the silicon nitride layer is 2.3 percent to 2.5 percent.
The fifth step: and patterning the silicon nitride layer on the backlight surface by using a laser to expose the region of the backlight surface corresponding to the P + region. The laser type can be selected from green nanosecond, ultraviolet picosecond, green picosecond and ultraviolet nanosecond.
And a sixth step: in the tank washer, the formed structure is put into an HF tank to remove the exposed portion of the phosphosilicate glass layer outside the silicon nitride of the backlight surface. The concentration of the HF solution is 0.5% to 1.5%, and the treatment is carried out at normal temperature for 25s to 35s. And then, the glass enters an alkali tank for texturing treatment, so that the areas exposed to the light facing surface and the backlight surface are textured. The texturing solution includes KOH at a concentration of 2.5% to 3.5%, and a texturing additive solution. The temperature of the texturing solution is 80-84 ℃, and the process time is 570-630 s. The etching amount for making the wool is 0.5g to 0.7g. The reflectivity of the smooth surface after the texturing treatment is 9 to 11 percent, and the width of the tower footing of the smooth surface is 1 to 3 mu m.
The seventh step: in the plasma enhanced atomic layer deposition equipment, an aluminum oxide layer and a silicon nitride layer which cover the light facing surface are sequentially formed. Wherein the thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm. Then treated in an HF solution at a concentration of 1% by weight for 30 seconds to perform a polishing treatment on the region exposed to the backlight surface.
Eighth step: in the chemical vapor deposition equipment, an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer which cover the backlight surface are sequentially formed. Wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 30nm, and the thickness of the p-type doped amorphous silicon layer is 10nm to 25nm.
The ninth step: and patterning the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer by using a laser, so that the remaining part of the intrinsic amorphous silicon material layer forms a second passivation layer, and the remaining part of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be selected from green nanosecond, ultraviolet picosecond, green picosecond and ultraviolet nanosecond.
The tenth step: and removing the exposed part of the silicon nitride layer by using an HF solution to expose a partial region of the first doped semiconductor layer. Wherein the concentration of the HF solution is 7-9%, and the HF solution is treated for 380-420 s at normal temperature.
The eleventh step: in a physical vapor deposition apparatus, a layer of transparent conductive material is formed overlying a backlight surface. The thickness of the transparent conductive material layer is 60nm to 100nm.
The twelfth step: and removing the local transparent conductive material layer, the second doped semiconductor layer and the second passivation layer by using a laser etching process so as to realize the insulation of the N + region and the P + region.
The thirteenth step: the first electrode and the second electrode are formed by screen printing or the like. The resulting structure is shown in fig. 2.
Table 1, among others, tests were performed on the back contact cells manufactured by the above example 1, comparative example 1 and comparative example 2, and parameters of the above three back contact cells were compared.
Table 1: comparison of parameters of back contact cells manufactured in example 1, comparative example 1 and comparative example 2
As shown in fig. 16, in the back contact cell fabricated in example 1, the insulating layer 161 is located at least between the second passivation layer 17 and the first doped semiconductor layer 141. Also, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer in a direction away from the silicon substrate 11. As shown in fig. 1, in the back contact cell manufactured in comparative example 1, the insulating layer 161 of silicon nitride material is formed only at the longitudinal boundary between the first doped semiconductor layer 141 and the second passivation layer 17. As shown in fig. 2, in the back contact cell manufactured in comparative example 2, a doped glass layer and an insulating layer 161 on the doped glass layer are formed only at the longitudinal boundary of the first doped semiconductor layer 141 and the second passivation layer 17. Based on this, as can be seen from table 1, the parallel resistance and the short-circuit current of the back contact cell manufactured in example 1 are higher than those of the back contact cells manufactured in comparative examples 1 and 2, respectively, and the open circuit voltage of the back contact cell manufactured in example 1 is lower than those of the back contact cells manufactured in comparative examples 1 and 2, thereby facilitating to reduce the risk of leakage of the back contact cell, and further making the conversion efficiency of the back contact cell manufactured in example 1 higher than those of the back contact cells manufactured in comparative examples 1 and 2.
In addition, as shown in fig. 16, in the back contact cell manufactured in example 1, an aluminum oxide layer and a silicon nitride layer on the aluminum oxide layer are sequentially formed on the light-facing surface in a direction away from the silicon substrate. As shown in fig. 1, in the back contact cell manufactured in comparative example 1, an amorphous silicon passivation layer and a silicon nitride layer on the amorphous silicon passivation layer are sequentially formed on the light-facing surface in a direction away from the silicon substrate. Therefore, because the amorphous silicon has the light absorption characteristic, the amorphous silicon passivation layer on the light facing surface generates parasitic absorption, and the light incident into the silicon substrate is reduced. Also, as previously mentioned, the amorphous silicon passivation layer is difficult to match with the light facing surface with small textured structure, and the aluminum oxide layer can match with the light facing surface with small textured structure. In this case, as can be seen from table 1, the light-facing surface pyramid width and the light-facing surface reflectivity of the back contact cell manufactured in example 1 are respectively smaller than those of the back contact cell manufactured in comparative example 1, so that the light-facing surface light trapping effect is enhanced, more light is incident into the silicon substrate, and finally the conversion efficiency of the back contact cell manufactured in example 1 is greater than that of the back contact cell manufactured in comparative example 1.
Furthermore, as shown in fig. 16, in the back contact cell manufactured in embodiment 1, the first passivation layer 121 and the first doped semiconductor layer 141 form a tunneling passivation contact structure. The second passivation layer 17 and the second doped semiconductor layer 18 constitute a hetero-contact structure. In contrast, as shown in fig. 1, in the back contact cell manufactured in comparative example 1, the first passivation layer 121 and the first doped semiconductor layer 141 constitute a hetero contact structure. While the second passivation layer 17 and the second doped semiconductor layer 18 also constitute a hetero-contact structure. Based on this, as described above, at high temperature, compared with the heterogeneous contact structure, the chemical property of the tunneling passivation contact structure is more stable, and thus the passivation effect on the tunneling passivation contact structure is smaller after the laser film opening process. Also, as can be seen from table 1, the N + region laser process window of the back contact cell fabricated in example 1 is larger than the N + region laser process window corresponding to the back contact cell fabricated in comparative example 1.
In summary, as can be seen from table 1, the filling factor of the back contact cell manufactured in example 1 is higher than the filling factor corresponding to the back contact cells manufactured in comparative example 1 and comparative example 2, i.e., the quality of the back contact cell manufactured in example 1 is better than that of the back contact cell manufactured in comparative example 1 and comparative example 2.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (13)
1. A back contact battery, comprising: a silicon substrate,
sequentially stacking a first passivation layer and a first doped semiconductor layer on a backlight surface of the silicon substrate along the thickness direction of the silicon substrate;
sequentially stacking a second passivation layer and a second doped semiconductor layer on the backlight surface along the thickness direction of the silicon substrate; wherein the second passivation layer and the second doped semiconductor layer which are arranged in a stacked manner cover partial regions of the first passivation layer and the first doped semiconductor layer which are arranged in a stacked manner, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite;
an insulating layer disposed on the backlight surface; the insulating layer is at least located between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer and the first doped semiconductor layer apart.
2. The back contact cell of claim 1, wherein the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is a doped polysilicon layer.
3. The back contact cell of claim 2, wherein the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer is a doped amorphous silicon layer.
4. The back contact battery of claim 1, further comprising: sequentially stacking an alumina layer and a silicon nitride layer on a light facing surface of the silicon substrate along a direction departing from the silicon substrate; or the like, or a combination thereof,
the back contact cell further comprises: and sequentially stacking a silicon oxide layer and a silicon nitride layer on a light facing surface of the silicon substrate along a direction departing from the silicon substrate.
5. The back contact cell of any one of claims 1-4, wherein the insulating layer comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence along a direction away from the silicon substrate; or the like, or, alternatively,
and the insulating layer comprises a silicon oxide layer and a silicon nitride layer which are sequentially stacked along the direction departing from the silicon substrate.
6. The back contact battery of any of claims 1-4, wherein the insulating layer has a thickness of 75nm to 125nm.
7. The back contact cell of any of claims 1-4, wherein the silicon substrate has a textured light-facing surface; the width of the tower base of the suede is 1-3 mu m.
8. A photovoltaic module comprising the back contact cell of any one of claims 1 to 7.
9. A method of manufacturing a back contact battery, comprising:
providing a silicon substrate;
forming a first passivation layer and a first doped semiconductor layer which are sequentially stacked on a backlight surface of the silicon substrate along the thickness direction of the silicon substrate;
forming an insulating layer on the backlight surface;
forming a second passivation layer and a second doped semiconductor layer which are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate; wherein the second passivation layer and the second doped semiconductor layer which are arranged in a stacking way cover partial areas of the first passivation layer and the first doped semiconductor layer which are arranged in a stacking way, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite; the insulating layer is at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer and the first doped semiconductor layer apart.
10. The method of claim 9, wherein forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement comprises:
sequentially forming a passivation material layer covering the backlight surface and an intrinsic semiconductor material layer positioned on the passivation material layer;
performing diffusion treatment on the intrinsic semiconductor material layer so that the intrinsic semiconductor material layer forms a doped semiconductor material layer and a doped glass layer is formed on the doped semiconductor material layer;
removing part of the doped glass layer on the doped semiconductor material layer by adopting a laser etching process; wherein, the residual part of the doped glass layer forms a mask layer;
and under the mask action of the mask layer, sequentially removing the part of the doped semiconductor material layer exposed outside the mask layer and the part of the passivation material layer exposed outside the mask layer to form the first passivation layer and the first doped semiconductor layer which are arranged in a stacked mode.
11. The method of manufacturing a back contact cell according to claim 10, wherein the doped glass layer has a thickness of 40nm to 60nm; and/or the presence of a gas in the gas,
the diffusion time of the diffusion treatment is 60min to 120min, and the diffusion temperature is 800 ℃ to 900 ℃.
12. The method of claim 10, wherein after forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement, and before forming the insulating layer on the backlight surface, the method further comprises:
removing the winding-plating doped glass layer, the winding-plating doped semiconductor material layer and the winding-plating passivation material layer which are positioned on the light facing surface and the side surface of the silicon substrate;
under the action of the mask layer, texturing is carried out on a light facing surface of the silicon substrate, so that the light facing surface is a textured surface;
and removing the mask layer.
13. The method of any of claims 9 to 12, wherein forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement comprises:
sequentially forming a passivation material layer covering the backlight surface and a doped semiconductor material layer positioned on the passivation material layer;
patterning the doped semiconductor material layer and the passivation material layer by adopting a laser etching process to form the first passivation layer and the first doped semiconductor layer which are arranged in a stacked manner; the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.
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| CN202211516779.3A CN115832065A (en) | 2022-11-29 | 2022-11-29 | Back contact battery, manufacturing method thereof and photovoltaic module |
| PCT/CN2023/118062 WO2024114031A1 (en) | 2022-11-29 | 2023-09-11 | Back contact cell, fabrication method therefor, and photovoltaic module |
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| CN202211516779.3A CN115832065A (en) | 2022-11-29 | 2022-11-29 | Back contact battery, manufacturing method thereof and photovoltaic module |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116053331A (en) * | 2023-03-31 | 2023-05-02 | 福建金石能源有限公司 | Back contact battery, manufacturing method thereof and photovoltaic module |
| CN117219693A (en) * | 2023-11-09 | 2023-12-12 | 天合光能股份有限公司 | Back contact solar cell and cell assembly |
| CN117423762A (en) * | 2023-12-15 | 2024-01-19 | 天合光能股份有限公司 | Solar cell, preparation method thereof, photovoltaic module and photovoltaic system |
| WO2024114031A1 (en) * | 2022-11-29 | 2024-06-06 | 隆基绿能科技股份有限公司 | Back contact cell, fabrication method therefor, and photovoltaic module |
| CN118198155A (en) * | 2024-05-14 | 2024-06-14 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery with polycrystalline silicon high-resistance region and preparation and application thereof |
| CN118213428A (en) * | 2024-05-21 | 2024-06-18 | 隆基绿能科技股份有限公司 | Back contact battery, manufacturing method thereof and photovoltaic module |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170033242A1 (en) * | 2015-07-27 | 2017-02-02 | Lg Electronics Inc. | Solar cell |
| CN106684160A (en) * | 2016-12-30 | 2017-05-17 | 中国科学院微电子研究所 | Back-junction back-contact solar cell |
| US20180294366A1 (en) * | 2015-12-07 | 2018-10-11 | Kaneka Corporation | Photoelectric conversion device and method for manufacturing same |
| CN113394304A (en) * | 2021-07-22 | 2021-09-14 | 浙江爱旭太阳能科技有限公司 | Solar cell and back contact structure thereof, cell module and photovoltaic system |
| CN113921625A (en) * | 2021-09-30 | 2022-01-11 | 泰州隆基乐叶光伏科技有限公司 | Back contact battery and manufacturing method thereof |
| WO2022012180A1 (en) * | 2020-07-14 | 2022-01-20 | 普乐新能源科技(徐州)有限公司 | Interdigitated back contact heterojunction solar cell based on lpcvd efficient amorphous silicon doping technology |
| CN114068731A (en) * | 2021-11-30 | 2022-02-18 | 福建金石能源有限公司 | Back contact heterojunction solar cell characterized by low laser damage and manufacturing method thereof |
| CN115207137A (en) * | 2022-09-16 | 2022-10-18 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| CN115312633A (en) * | 2022-10-11 | 2022-11-08 | 金阳(泉州)新能源科技有限公司 | Mask-layer-free combined passivation back contact battery and preparation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8525018B2 (en) * | 2009-09-07 | 2013-09-03 | Lg Electronics Inc. | Solar cell |
| KR20130050721A (en) * | 2011-11-08 | 2013-05-16 | 삼성에스디아이 주식회사 | Solar cell |
| CN113284961B (en) * | 2021-07-22 | 2021-09-28 | 浙江爱旭太阳能科技有限公司 | Solar cell and passivation contact structure thereof, cell module and photovoltaic system |
| CN114497290A (en) * | 2022-02-10 | 2022-05-13 | 福建金石能源有限公司 | Manufacturing method of back contact heterojunction solar cell |
| CN115832065A (en) * | 2022-11-29 | 2023-03-21 | 隆基绿能科技股份有限公司 | Back contact battery, manufacturing method thereof and photovoltaic module |
-
2022
- 2022-11-29 CN CN202211516779.3A patent/CN115832065A/en active Pending
-
2023
- 2023-09-11 WO PCT/CN2023/118062 patent/WO2024114031A1/en unknown
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170033242A1 (en) * | 2015-07-27 | 2017-02-02 | Lg Electronics Inc. | Solar cell |
| US20180294366A1 (en) * | 2015-12-07 | 2018-10-11 | Kaneka Corporation | Photoelectric conversion device and method for manufacturing same |
| CN106684160A (en) * | 2016-12-30 | 2017-05-17 | 中国科学院微电子研究所 | Back-junction back-contact solar cell |
| WO2022012180A1 (en) * | 2020-07-14 | 2022-01-20 | 普乐新能源科技(徐州)有限公司 | Interdigitated back contact heterojunction solar cell based on lpcvd efficient amorphous silicon doping technology |
| CN113394304A (en) * | 2021-07-22 | 2021-09-14 | 浙江爱旭太阳能科技有限公司 | Solar cell and back contact structure thereof, cell module and photovoltaic system |
| CN113921625A (en) * | 2021-09-30 | 2022-01-11 | 泰州隆基乐叶光伏科技有限公司 | Back contact battery and manufacturing method thereof |
| CN114068731A (en) * | 2021-11-30 | 2022-02-18 | 福建金石能源有限公司 | Back contact heterojunction solar cell characterized by low laser damage and manufacturing method thereof |
| CN115207137A (en) * | 2022-09-16 | 2022-10-18 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and preparation method thereof |
| CN115312633A (en) * | 2022-10-11 | 2022-11-08 | 金阳(泉州)新能源科技有限公司 | Mask-layer-free combined passivation back contact battery and preparation method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024114031A1 (en) * | 2022-11-29 | 2024-06-06 | 隆基绿能科技股份有限公司 | Back contact cell, fabrication method therefor, and photovoltaic module |
| CN116053331A (en) * | 2023-03-31 | 2023-05-02 | 福建金石能源有限公司 | Back contact battery, manufacturing method thereof and photovoltaic module |
| CN117219693A (en) * | 2023-11-09 | 2023-12-12 | 天合光能股份有限公司 | Back contact solar cell and cell assembly |
| CN117219693B (en) * | 2023-11-09 | 2024-04-05 | 天合光能股份有限公司 | Back contact solar cell and cell assembly |
| CN117423762A (en) * | 2023-12-15 | 2024-01-19 | 天合光能股份有限公司 | Solar cell, preparation method thereof, photovoltaic module and photovoltaic system |
| CN118198155A (en) * | 2024-05-14 | 2024-06-14 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery with polycrystalline silicon high-resistance region and preparation and application thereof |
| CN118213428A (en) * | 2024-05-21 | 2024-06-18 | 隆基绿能科技股份有限公司 | Back contact battery, manufacturing method thereof and photovoltaic module |
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| Publication number | Publication date |
|---|---|
| WO2024114031A1 (en) | 2024-06-06 |
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