CN115831860B

CN115831860B - Level shifter, semiconductor device and preparation method thereof

Info

Publication number: CN115831860B
Application number: CN202310182769.9A
Authority: CN
Inventors: 赵亮亮; 李勇; 顾学强
Original assignee: Smic Pioneer Integrated Circuit Manufacturing Shaoxing Co ltd
Current assignee: Smic Pioneer Integrated Circuit Manufacturing Shaoxing Co ltd
Priority date: 2023-03-01
Filing date: 2023-03-01
Publication date: 2023-05-23
Anticipated expiration: 2043-03-01
Also published as: CN115831860A

Abstract

The invention provides a level shifter, a semiconductor device and a preparation method thereof. In the level shifter, the adjusting area is set in at least one isolation doped area, and a groove can be formed in the adjusting area or the adjusting area can also be a non-implanted area, so that the whole ion quantity in the isolation doped area is reduced, the difficulty that the isolation doped area is transversely exhausted is reduced, and the whole pressure resistance of the level shifter is improved. In addition, the semiconductor device provided by the invention can also ensure that the isolation structure of the level shifter has higher withstand voltage, for example, 20V can be achieved, the withstand voltage requirement of more than 15V is met, and no leakage phenomenon between a high-voltage side circuit and a drain terminal is ensured.

Description

Level shifter, semiconductor device and preparation method thereof

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a level shifter, a method for manufacturing the level shifter, a semiconductor device, and a method for manufacturing the semiconductor device.

Background

The high voltage power gate driver chip is typically implemented using a process compatible with the high voltage circuit and the low voltage circuit. The control signal from the low-voltage side circuit is converted into the control signal of the high-voltage side circuit through a Level Shifter (Level Shifter) between the high-voltage side circuit and the low-voltage side circuit so as to be transmitted to the high-voltage side circuit for controlling the high-voltage side circuit, and the Level conversion between the high-voltage side circuit and the low-voltage side circuit is realized.

The isolation structure is arranged on the periphery of the level shifter and used for isolating the high-voltage side circuit from the level shifter and preventing leakage from affecting functions among devices. Currently, commonly used isolation structures include, for example: dielectric isolation (isolation of device structures in a substrate by using an insulating medium such as oxide), self-isolation (isolation between devices is realized by means of self-depletion layer withstand voltage), junction isolation (isolation by using the principle of PN reverse bias), and the like. When the isolation structure is provided, it is generally necessary to ensure the isolation performance between the high-voltage side circuit and the level shifter while ensuring sufficient withstand voltage of the isolation structure itself.

Therefore, how to improve the breakdown voltage of the level shifter while ensuring the voltage-resistant performance of the isolation structure is always an important research topic in the field.

Disclosure of Invention

The invention aims to provide a level shifter and a preparation method thereof, which can effectively improve the breakdown voltage of the level shifter and optimize the voltage resistance of a device.

To this end, the invention provides a level shifter comprising: a substrate having a doped layer of a first doping type; a field effect transistor including a drain region of a first doping type, a source region of the first doping type, and a gate structure formed on the substrate and located between the source region and the drain region; and the isolation structure is positioned at the periphery of the field effect transistor, comprises at least one isolation doped region with a second doping type formed in the doped layer, and is provided with an adjustment region inside the at least one isolation doped region, wherein a groove is formed in the adjustment region or the adjustment region is a non-implantation region.

Optionally, the grooves are also filled with undoped materials or materials of the first doping type.

Optionally, the non-implanted region is a region not subjected to ion implantation in the ion implantation process of the isolation doped region.

Optionally, the isolation doped region is provided with a plurality of adjustment regions, and the plurality of adjustment regions are sequentially arranged in the isolation doped region along the extension direction of the isolation doped region.

Optionally, a distance between the adjusting region and a side boundary of the adjacent isolation doped region is greater than or equal to 1 μm; and/or, the distance between adjacent adjustment areas is greater than or equal to 1 μm. And the maximum lateral dimension of the adjustment region is 2 μm to 5 μm.

Optionally, the substrate comprises a base with a second doping type and an epitaxial layer with a first doping type which are sequentially arranged from bottom to top, and the field effect transistor is formed on the epitaxial layer; and the isolation structure comprises at least two isolation doped regions which are sequentially arranged from bottom to top and are connected with each other, wherein the isolation doped region at the bottommost layer extends upwards from the substrate into the epitaxial layer.

Optionally, the isolation doped region in the isolation structure includes a first shallow well region of the second doping type extending inward from the top surface of the epitaxial layer into the epitaxial layer. And the level shifter further comprises a second shallow well region of a second doping type extending inwards from the top surface of the epitaxial layer into the epitaxial layer, wherein the second shallow well region is located on one side of the gate structure close to a source region, the source region is formed in the second shallow well region, and the first shallow well region extends from the outer side of the drain region to the second shallow well region around the field effect transistor and is connected with the second shallow well region.

Optionally, the isolation doped region in the isolation structure further comprises a first deep well region and a first buried region of a second doping type, wherein the first deep well region and the first buried region are located below the first shallow well region and are sequentially connected from top to bottom. And the level shifter further comprises a second deep well region and a second buried region, wherein the second deep well region is positioned below the second shallow well region and is sequentially connected from top to bottom, the second deep well region is formed by extending from the outer side of the drain region to the second deep well region in a surrounding manner, and is connected with the second deep well region, and the first buried region is formed by extending from the outer side of the drain region to the second buried region in a surrounding manner, and is connected with the second buried region in a surrounding manner.

Optionally, the level shifter further includes a plurality of third buried regions disposed side by side, the plurality of third buried regions being arranged between the source region and the drain region, and the third buried regions extending from the substrate up into the epitaxial layer.

Optionally, the level shifter further includes a third well region of the first doping type, the third well region being located on a side of the gate structure near a drain region, the drain region being formed in the third well region.

The invention also provides a preparation method of the level shifter, which comprises the following steps: a field effect transistor is formed on a substrate, the field effect transistor including a drain region of a first doping type, a source region of the first doping type, the drain region and the source region being formed within the substrate, and a gate structure formed on the substrate between the source region and the drain region. Wherein the substrate has a doped layer of a first doping type, and the method for manufacturing the level shifter further comprises: forming an isolation structure on the periphery of the field effect transistor, wherein the isolation structure comprises forming at least one isolation doped region with a second doping type in the doped layer, and setting an adjustment region in the at least one isolation doped region, wherein a groove is formed in the adjustment region or the adjustment region is a non-implanted region.

Optionally, the preparation method of the isolation structure includes: forming a mask layer on the substrate, wherein the mask layer completely exposes the region of the isolation structure; performing an ion implantation process of a second doping type to form at least one isolation doping region; and etching at least the adjustment region in the isolation doped region of the topmost layer to form the groove in at least the isolation doped region of the topmost layer.

Optionally, after forming the groove, the method further includes: and filling undoped materials or materials of the first doping type into the grooves.

Optionally, the preparation method of the isolation structure includes: forming a mask layer on the substrate, wherein a shielding pattern is formed on the adjustment area of the isolation structure on the mask layer, so that the mask layer covers the adjustment area and partially exposes the area of the isolation structure; an ion implantation process of a second doping type is performed to form an isolation doped region, and ions are not implanted in the adjustment region to form the non-implanted region.

Optionally, the preparation method of the isolation structure includes: performing an ion implantation process of a second doping type to form a first shallow well region; and simultaneously implanting and forming a second shallow well region in the process of performing the ion implantation process, wherein the second shallow well region is positioned on one side of the gate structure close to a source region, the source region is formed in the second shallow well region, and the first shallow well region extends from the outer side of the drain region to the second shallow well region and is connected with the second shallow well region around the field effect transistor.

Optionally, the substrate includes a base of the second doping type and an epitaxial layer of the first doping type sequentially arranged from bottom to top. The preparation method of the isolation structure comprises the following steps: performing an ion implantation process of a second doping type on the substrate before forming the epitaxial layer to form a first buried region of the second doping type in the substrate; and in the process of performing an epitaxial process to form the epitaxial layer on the substrate, ions in the first buried region are upwardly diffused into the epitaxial layer, and performing ion implantation processes of a second doping type on the epitaxial layer twice in sequence to sequentially form a first deep well region and a first shallow well region, wherein the bottom of the first deep well region is connected with the first buried region, and the bottom of the first shallow well region is connected with the first deep well region.

Optionally, forming a second buried region on the low voltage side of the transistor region in addition to the first buried region of the isolation structure, the first buried region extending from the high voltage side of the transistor region around the transistor region to the low voltage side of the transistor region to connect the second buried region; forming a second deep well region on the low-voltage side of the transistor region in addition to the first deep well region of the isolation structure, the first deep well region extending from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region to connect the second deep well region; and forming a second shallow well region on the low-voltage side of the transistor region in the first shallow well region of the isolation structure, wherein the first shallow well region extends from the high-voltage side of the transistor region to the low-voltage side of the transistor region around the transistor region so as to be connected with the second shallow well region.

In addition, the invention also provides a semiconductor device which comprises the level shifter. And, the steps of the method for manufacturing the level shifter as described above are correspondingly included for the method for manufacturing the semiconductor device; alternatively, processing is performed on a substrate having a level shifter as described above to prepare the semiconductor device.

In the level shifter provided by the invention, the adjusting area is also arranged in at least one isolation doped area, and the adjusting area can be provided with the groove or can be a non-injection area, so that the whole ion quantity in the isolation doped area is reduced, the difficulty of the isolation doped area in transverse depletion is reduced, and the whole pressure resistance of the level shifter is improved. In addition, by arranging the adjusting area, the isolation structure of the level shifter can be ensured to have higher withstand voltage (for example, 20V can be achieved, and the withstand voltage requirement of more than 15V is met), so that no leakage phenomenon exists between the high-voltage side circuit and the drain terminal.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device with a level shifter according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of another structure of a semiconductor device with a level shifter according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a semiconductor device with a level shifter according to an embodiment of the present invention.

Fig. 4 is a partial enlarged view of an isolated doped region with an adjustment region in an embodiment of the present invention.

Fig. 5 is a graph comparing simulated breakdown voltages of a level shifter when no adjustment region is provided in an isolation doped region and when a drain terminal of the level shifter is shorted to a high-side circuit.

Fig. 6 is a simulation diagram of breakdown voltage between a high-side circuit and a drain terminal of the level shifter when the level shifter is in an operating state with an adjustment region provided.

Fig. 7-15 are schematic structural diagrams of a semiconductor device with a level shifter according to an embodiment of the present invention during the fabrication process.

Wherein, the reference numerals are as follows: 100-a substrate; 110P-substrate; a 120N-epitaxial layer; 200-field effect transistor; 200S-source region; 200D-drain region; 200G-gate structure; 200B-a first contact region; 210-a second isolation oxide layer; 220-field oxide layer; 300-isolation structures; 310-a first isolation oxide layer; 510/520/530/540/550/560-mask layer; 561-mask pattern; PBL 1-a first buried region; a PBL 2-second buried region; PBL 3-third buried region; NBL-a fourth buried region; DPW 1-a first deep well region; DPW 2-a second deep well region; PW 1-a first shallow well region; PW 2-a second shallow well region; NW 1-third well region; NW 2-fourth well region.

Detailed Description

The level shifter, the semiconductor device and the manufacturing method thereof according to the present invention are described in further detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It will be appreciated that relative terms such as "above," "below," "top," "bottom," "above," and "below" as illustrated in the figures may be used to describe various element relationships to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element.

Fig. 1 is a schematic structural diagram of a semiconductor device with a level shifter according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of another semiconductor device with a level shifter according to an embodiment of the present invention. As shown in fig. 1 and 2, the level shift device provided in this embodiment includes: a substrate 100, a field effect transistor 200 formed on said substrate 100, an isolation structure 300 formed outside said field effect transistor 200.

Wherein the substrate 100 has a doped layer of a first doping type. In a specific example, the substrate 100 includes, for example, a base 110P and an epitaxial layer 120N formed on the base 110P, and the base 110P is specifically a base of a second doping type, and the epitaxial layer 120N is specifically an epitaxial layer of a first doping type, so that the epitaxial layer 120N forms a doped layer of the first doping type of the substrate 100.

It should be noted that, the first doping type and the second doping type are opposite doping types, for example, the first doping type is N-type, and the second doping type is P-type; alternatively, the first doping type is P-type and the second doping type is N-type. In this embodiment, the first doping type is N-type and the second doping type is P-type.

Further, the field effect transistor 200 specifically includes a drain region 200D of the first doping type, a source region 200S of the first doping type, and a gate structure 200G, the drain region 200D and the source region 200S are specifically formed within a doped layer of the first doping type (i.e., the epitaxial layer 120N) of the substrate 100, and the gate structure 200G is formed on the substrate 100 and between the source region 200S and the drain region 200D. In this embodiment, the field effect transistor 200 is, for example, an LDMOS transistor, wherein the epitaxial layer 120N located in the transistor region can be used to form a drift region of the LDMOS transistor.

With continued reference to fig. 1 and 2, an isolation structure 300 is disposed on the outer side of the field effect transistor 200, where the isolation structure 300 is used to isolate the high side circuit from the field effect transistor 200, and prevent leakage from affecting the function between devices. In one example, the isolation structure 300 may surround the transistor region from a high voltage side of the transistor region (i.e., a side near the drain region 200D) to a low voltage side of the transistor region (i.e., a side near the source region 200S).

The isolation structure 300 includes at least one isolation doped region of a second doping type (for example, a P-type isolation region) specifically formed in the doped layer of the first doping type of the substrate 100, so as to implement device isolation by using a PN junction isolation technology, and by performing PN reverse bias on the PN junction isolation, the PN junction isolation structure can be expanded by a depletion layer, so as to improve breakdown resistance of the device.

In a specific example, the isolation structure 300 is formed on the epitaxial layer 120N and penetrates the epitaxial layer 120N to reach the substrate 110P. Further, the isolation structure 300 includes at least two isolation doped regions sequentially disposed from bottom to top and connected to each other, so as to penetrate through the epitaxial layer 120N in the height direction, wherein the isolation doped region at the bottommost layer extends from the substrate 110P up into the epitaxial layer 120N. In this embodiment, the isolation structure 300 includes three isolation doped regions, including a first buried region PBL1 of a second doping type, a first deep well region DPW1 of the second doping type, and a first shallow well region PW1 of the second doping type, which are sequentially arranged from bottom to top and are connected to each other, where the first shallow well region PW1 is a well region with a doping depth shallower than the first deep well region DPW1, and the first deep well region DPW1 is a well region with a doping depth deeper than the first shallow well region PW 1. Specifically, the first shallow well region PW1 extends inward from the top surface of the substrate 100 and overlaps the underlying first deep well region DPW1 partially in the height direction, the first deep well region DPW1 overlaps the underlying first buried region PBL1 partially in the height direction, and the first buried region PBL1 spans the interface between the epitaxial layer 120N and the substrate 110P, so that the first shallow well region PW1, the first deep well region DPW1 and the first buried region PBL1 are connected up and down and penetrate the epitaxial layer 120N.

It should be appreciated that the isolation structure 300 in this embodiment includes 3 isolation doped regions, and in other examples, the isolation structure 300 may include two isolation doped regions (e.g., only the first shallow well region PW1 and the first buried region PBL1 connected up and down) or more than three isolation doped regions, so long as the isolation doped regions within the isolation structure 300 may be connected to each other and extend through the epitaxial layer 120N.

In addition, the isolation structure 300 may further include a first isolation oxide layer 310, the first isolation oxide layer 310 being formed on the top surface of the substrate 100 over the isolation doped region. The first isolation oxide layer 310 may be formed by, for example, a local oxidation isolation process (Local Oxidation of Silicon, LOCOS), and when the substrate 100 is a silicon substrate, the field oxide layer 310 may be a silicon oxide layer.

With continued reference to fig. 1 and fig. 2, an adjustment region 320 is further disposed in at least one of the isolation doped regions of the isolation structure 300, for adjusting the overall ion doping amount of the isolation doped region, reducing the overall ion amount of the isolation doped region, so as to facilitate reducing the difficulty of the isolation doped region being laterally depleted, and improving the breakdown voltage of the level shifter. Wherein the tuning region 320 may be provided at least in the topmost spacer doped region.

In one example, the tuning region 320 may include a recess formed in the isolation doped region, as shown in the cross-sectional schematic view of fig. 3. The recess is, for example, at least one recess formed by etching a portion of the substrate of the isolation doped region after ion implantation of the substrate 100 to form the isolation doped region, where the P doped region in the isolation doped region is partially removed, thereby reducing the overall doping amount in the isolation doped region (i.e., reducing the amount of P-type ions in the isolation doped region). The recess extends inward from the top surface of the substrate to a predetermined depth, for example, the recess is formed in the first shallow well region PW1 and optionally extends downward into the first deep well region DPW1 and may extend even further downward into the first buried region PBL1 in this embodiment. In addition, undoped materials can be filled in the grooves; and optionally filling the recess with a material of the first doping type in order to further reduce the amount of ion doping in the isolation doped region.

In another example, the adjustment region 320 may include a non-implanted region formed in the isolation doped region, wherein the non-implanted region is specifically a region that is not ion-implanted in the ion implantation process of the isolation doped region, and the overall doping amount in the isolation doped region may be reduced (i.e., the P-type ion amount in the isolation doped region is reduced). Specifically, before the ion implantation process is performed to form the isolation doped region, a shielding pattern can be added in the corresponding mask pattern, so that implantation of the shielded region to form a non-implanted region can be avoided during ion implantation. In this embodiment, the non-implantation region may be formed by partially shielding during at least one ion implantation process in the first shallow well region PW1, the first deep well region DPW1 and the first buried region PBL 1.

Further, a plurality of adjustment regions 320 may be disposed in the isolation doped region, and the plurality of adjustment regions 320 may be sequentially arranged in the isolation doped region along the extension direction of the isolation doped region. For example, referring to fig. 1, the plurality of adjustment regions 320 are arranged in two rows, and each row of adjustment regions 320 is sequentially arranged along the extending direction of the isolation doped region; alternatively, as shown in fig. 2, the plurality of adjustment regions 320 are arranged in a single row in compliance with the extension direction of the isolation doped region. Of course, in other examples, the plurality of adjustment regions 320 may be arranged in other ways, which are not limited herein.

Next, referring to the enlarged partial view of the isolation doped region shown in fig. 4, the D1 direction is the extension direction of the isolation doped region, and the D2 direction is the cross-sectional direction perpendicular to the extension direction of the isolation doped region. Wherein, the spacing S1 between the adjustment regions 320 and the adjacent side boundary of the isolation doped region is 1 μm or more, and the spacing between the adjacent adjustment regions 320 may be 1 μm or more (for example, the spacing S3 between the adjacent adjustment regions 320 in the D1 direction is 1 μm or more, and the spacing S2 between the adjacent adjustment regions 320 in the D2 direction may be 1 μm or more).

Further, the cross-sectional shape of the adjustment region 320 parallel to the substrate surface may be circular, elliptical, diamond-shaped, rectangular, etc., and the maximum lateral dimension S4 of the adjustment region 320 may be, for example, between 2 μm and 5 μm. It should be appreciated that the shape and size of the adjustment region 320 and the distance between the adjustment region 320 and the adjacent side boundary of the isolation doped region are not limited thereto, and may be correspondingly adjusted according to the actual doping concentration and size of the isolation doped region, for example.

With continued reference to fig. 1-2 and 3, a second shallow well region PW2 of a second doping type is also formed in the substrate 100, the second shallow well region PW2 extending from the top surface of the substrate 100 down to the inside of the substrate, and the second shallow well region PW2 is formed on the low voltage side of the transistor region (i.e., on the side of the gate structure 200G near the source region 200S) and the source region 200S may be formed within the second shallow well region PW 2. In addition, the portion of the gate structure 200G near the source region 200S also covers the second shallow well region PW2, and when an on voltage is applied to the gate structure 200G of the field effect transistor 200, a conductive channel is formed in the second shallow well region PW2 covered by the gate structure 200G, so as to enable current to flow between the source region 200S, the conductive channel, and the drift region to the drain region 200D, i.e., the second well region PW2 is used to form a body region of the channel inversion type of the field effect transistor 200.

A first contact region 200B (specifically, a Bulk contact region) of a second doping type is further formed in the second shallow well region PW2, and an ion doping concentration of the first contact region 200B is greater than that of the second shallow well region PW2, so as to electrically induce the second shallow well region PW2 through the first contact region 200B. In this embodiment, the first contact region 200B is formed on a side of the source region 200S away from the gate structure 200G, and a second isolation oxide layer 210 is further disposed between the first contact region 200B and the source region 200S.

In a specific example, the second shallow well region PW2 and the first shallow well region PW1 may be formed simultaneously in the same ion implantation process, so that the second shallow well region PW2 and the first shallow well region PW1 have the same parameters, i.e., the doping depth and the doping concentration of the second shallow well region PW2 and the first shallow well region PW1 in the isolation structure 300 may be substantially the same. In particular, the first shallow well PW1 of the isolation structure 300 may be extended horizontally from the outside of the drain region 200D around the field effect transistor 200 to the low voltage side of the transistor region, such that the first shallow well PW1 is connected to the second shallow well PW2 in the horizontal direction, and such that the first shallow well PW1 and the second shallow well PW2 connected to each other surround the field effect transistor 200.

It should be noted that, because the second shallow well region PW2 and the first shallow well region PW1 are formed simultaneously in the same ion implantation process, in order to ensure the performance of the field effect transistor 200, the doping concentration and the doping depth of the second shallow well region PW2 need to be satisfied, so that the doping concentration and the doping depth of the first shallow well region PW1 are difficult to be directly adjusted in the ion implantation process. Based on this, in this embodiment, by forming the recess 320, the first shallow well PW1 is partially removed, so that the overall ion doping amount in the first shallow well PW1 can be greatly reduced on the basis that the second shallow well PW2 is not affected, which is beneficial to reducing the difficulty of the lateral depletion of the isolation doped region; or, the local position of the isolation region is shielded when the ion implantation process is carried out, the whole ion quantity of the formed isolation doped region is reduced, and a non-implanted region is correspondingly generated.

In this embodiment, a second deep well region DPW2 of a second doping type and a second buried region PBL2 of a second doping type are further formed in the substrate 100, the second deep well region DPW2 and the second buried region PBL2 are sequentially formed below the second shallow well region PW2 and are connected to each other, the doping depth and the doping concentration of the second deep well region DPW2 may be the same as those of the first deep well region DPW1 in the isolation structure 300, and the doping depth and the doping concentration of the second buried region PBL2 may be the same as those of the first buried region PBL1 in the isolation structure 300. Specifically, the second deep well region DPW2 and the first deep well region DPW1 may be formed simultaneously in the same ion implantation process, and the second buried region PBL2 and the first buried region PBL1 may also be formed simultaneously in the same ion implantation process. That is, the second shallow well region PW2 is extended inward from the top surface of the substrate 100 and partially overlaps the second deep well region DPW2 thereunder in the height direction, the second deep well region DPW2 partially overlaps the second buried region PBL2 thereunder in the height direction, and the second buried region PBL2 extends downward from the epitaxial layer 120N to the base 110P so that the second shallow well region PW2, the second deep well region DPW2, and the second buried region PBL2 are connected up and down and penetrate the epitaxial layer 120N.

Also, the first buried region PBL1 and the first deep well region DPW1 in the isolation structure 300 may be horizontally extended from the outside of the drain region 200D around the field effect transistor 200 to the low voltage side of the transistor region (i.e., a side close to the source region 200S) such that the first deep well region DPW1 is horizontally connected to the second deep well region DPW2 and the first buried region PBL1 is horizontally connected to the second buried region PBL2, and such that the interconnected first deep well region DPW1 and second deep well region DPW2, and the interconnected first buried region PBL1 and second buried region PBL2 surround the field effect transistor 200.

It is considered that the second shallow well region PW2, the second deep well region DPW2 and the second buried region PBL2 connected up and down on the low voltage side of the transistor region (i.e., the side close to the source region 200S) are also used to realize an isolation effect, which is horizontally connected to the isolation structure 300 to isolate the field effect transistor 200. That is, the first shallow well region PW1, the first deep well region DPW1, and the first buried region PBL1 within the isolation structure 300 are connected one by one to the second shallow well region PW2, the second deep well region DPW2, and the second buried region PBL2, thereby forming an isolation ring surrounding the field effect transistor 200.

That is, the isolation doped region of the isolation structure 300 in this embodiment can be adjusted correspondingly according to the doping condition of the low voltage side. For example, on the low voltage side (i.e., the side close to the source region 200S), the depth of the second shallow well PW2 designed to meet the performance requirement of the field effect transistor 200 is smaller, and at this time, the second deep well DPW2 may be additionally disposed so that the second shallow well PW2, the second deep well DPW2 and the second buried region PBL2 connected up and down may reach the substrate 110P to achieve isolation, and at this time, the first shallow well PW1, the first deep well DPW1 and the first buried region PBL1 may be correspondingly disposed in the isolation structure 300; on the contrary, when the depth of the designed second shallow well PW2 is larger and can be vertically connected with the second buried region PBL2 below, the second deep well DPW2 can be omitted, and the first deep well DPW1 can be correspondingly omitted in the isolation structure 300, and only the first shallow well PW1 and the first buried region PBL1 are provided.

With continued reference to fig. 1 and 2, a third well region NW1 of the first doping type is also formed in the substrate 100, the third well region NW1 being located on the high voltage side of the transistor region (i.e., on the side of the gate structure 200G adjacent to the drain region 200D), the drain region 200D being formed in the third well region NW 1. The ion doping concentration of the third well NW1 may be between the ion doping concentration of the drain region 200D and the ion doping concentration of the epitaxial layer 120N, so that the third well NW1 may be used to form a buffer, so as to avoid a larger change of the ion doping concentration when the drain region 200D directly reaches the epitaxial layer 120N.

Optionally, a field oxide layer 220 is further formed on the surface of the substrate 100, the field oxide layer 220 is located between the second shallow well region PW2 and the drain region 200D, and the gate structure 200G further extends to cover the field oxide layer 220 to form a field plate structure. The field oxide layer 220 may be formed by, for example, a local oxidation isolation process (Local Oxidation of Silicon, LOCOS), and when the substrate 100 is a silicon substrate, the field oxide layer 220 may be a silicon oxide layer. In this embodiment, the drain region 200D is formed between the field oxide layer 220 and the first isolation oxide layer 310. And, the field oxide layer 220, the first isolation oxide layer 310, and the second isolation oxide layer 210 may be formed simultaneously using a partial oxidation isolation process in the same process step.

With continued reference to fig. 1 and 2, in an example, a plurality of third buried regions PBL3 disposed side by side are further formed in the substrate 100, and the plurality of third buried regions PBL3 are disposed in a transistor region, specifically between the source region 200S and the drain region 200D, more specifically under the gate structure 200G and the field oxide layer 220. And, the third buried region PBL3 extends downward from the epitaxial layer 120N into the substrate 110P (or it can be considered that the third buried region PBL3 extends upward from the substrate 110P into the epitaxial layer 120N), by providing the third buried region PBL3, the depletion level of the drift region of the field effect transistor 200 under the field oxide layer 220 (in the epitaxial layer 120N) is further increased. And, the plurality of third buried regions PBL3 of small width dimension are arranged side by side (the width dimension of the third buried regions PBL3 may be smaller than that of the first buried regions PBL1, for example), the ion concentration of the second doping type in the region can be effectively prevented from being too high.

Further, a semiconductor device having the level shifter described above is provided in the present embodiment, and the semiconductor device further includes a high-voltage side circuit. Referring to fig. 1 and 2, the high side circuit is disposed on the high side of the level shifter (i.e., the side near the drain region 200D) and on the side of the isolation structure 300 remote from the field effect transistor 200. The high-voltage side circuit includes a fourth well region NW2 with a first doping type, and a second contact region with the first doping type is further formed in the fourth well region NW2 for realizing electrical connection with the outside. And, the high side circuit further includes a fourth buried region NBL of the first doping type extending from the substrate 110P up into the epitaxial layer 120N.

During operation of the semiconductor device, the body contact region Bulk (i.e., the first contact region 200B) and the source region 200S may be connected to a low potential port, the gate structure 200G may be connected to an operating voltage (e.g., 25V), the drain region 200D and a high side circuit (e.g., the second contact region in the fourth well region NW 2) may be connected to a high potential port (wherein the drain region 200D is, for example, 600V and the high side circuit is, for example, 615V), and during this process, the isolation between the drain region 200D and the high side circuit may be achieved by the isolation structure 300.

As described above, in this embodiment, the adjusting region 320 is disposed in the isolation doped region, so as to adjust the overall ion doping amount of the isolation doped region, reduce the overall ion amount of the isolation doped region, and facilitate reducing the difficulty of the isolation doped region being laterally depleted, thereby improving the breakdown voltage of the potentiometer.

The simulation results shown in reference 5 in detail simulate a comparison graph of breakdown voltage bv_d when the isolation doped region is provided with the adjustment region 320 and the device drain terminal is short-circuited with the high-voltage side circuit when the adjustment region 320 is not provided (i.e., the overall voltage-withstanding performance of the electric potential shifter is compared), as shown in fig. 5, the breakdown voltage bv_d1 when the adjustment region 320 is not provided is only 173.7V, however, the breakdown voltage bv_d2 after the adjustment region 320 is provided can be increased to 674.5V, and the voltage-withstanding performance of the device is greatly improved.

Next, referring to another simulation result shown in fig. 6, it simulates a breakdown voltage bv_h between the high-side circuit and the drain terminal when the adjustment region 320 is set in an operating state, where the breakdown voltage bv_h is obtained, for example: the drain region 200D is kept connected to the 600V potential, and a scanning voltage stepped up from 600V (specifically, a scanning voltage continuously stepped up from 600V for the second contact region of the fourth well region NW 4) is applied to the high-voltage side circuit until breakdown occurs. As shown in fig. 6, after the adjustment region 320 is set, the breakdown voltage bv_h between the high-voltage side circuit and the drain terminal can be increased to 20V, so as to meet the voltage-withstanding requirement (greater than 15V) of the isolation structure 300, and ensure that no leakage occurs between the high-voltage side circuit and the drain terminal.

The level shifter and the semiconductor device described above, and the method of manufacturing the same are described in detail below. As shown in fig. 1 and fig. 2, the preparation method of the level shifter in this embodiment specifically includes: a field effect transistor 200 is formed on a substrate 100, said field effect transistor 200 comprising a drain region 200D of a first doping type, a source region 200S of a first doping type and a gate structure 200G, said drain region 200D and said source region 200S being formed within said substrate 100, said gate structure 200G being formed on said substrate 100 between said source region 200S and said drain region 200D. And, the preparation method of the level shifter further comprises the following steps: forming an isolation structure 300 on the periphery of the field effect transistor 200, wherein the isolation structure 300 comprises at least one isolation doped region of the second doping type, and an adjustment region is further set in the at least one isolation doped region, and a groove is formed in the adjustment region or the adjustment region is a non-implantation region. In addition, the preparation method of the semiconductor device comprises the step of preparing the level shifter by adopting the method.

The method for preparing the isolation structure 300 may include: an ion implantation process of the second doping type is performed to form a first shallow well region PW1 (i.e., an isolation doped region in the isolation structure 300). During the ion implantation process, a second shallow well region PW2 is also formed by implantation, the second shallow well region PW2 is located at a side of the gate structure 200G near the source region 200S, the source region 200S is formed in the second shallow well region PW2, and the first shallow well region PW1 extends from the outside of the drain region 200D around the field effect transistor 200 to the second shallow well region PW2 to be connected to the second shallow well region PW 2.

As described above, the adjustment region 320 is set in at least one of the isolation doped regions within the isolation structure 300. The method for forming the groove in the adjustment area 320 includes, for example: forming a mask layer on the substrate 100, the mask layer completely exposing regions of the isolation structures; then, performing a second doping type ion implantation process to form at least one isolation doped region (including the first shallow well region PW 1); next, at least the tuning region 320 in the topmost spacer doped region is etched to form the recess in at least the topmost spacer doped region. In a further aspect, after forming the groove, the method further includes: and filling undoped materials or materials of the first doping type into the grooves.

In a specific example, the topmost isolation doped region is a first shallow well region PW1, and a second shallow well region PW2 is also formed by implantation while the first shallow well region PW1 is formed, based on which the doping depths and the doping concentrations of the first shallow well region PW1 and the second shallow well region PW2 are identical or nearly identical. It should be appreciated that the formation of the recess by etching the first shallow well PW1 after the ion implantation may result in a decrease in the total amount of ions in the first shallow well PW1, and may further cause the ions to diffuse into the tuning region 320 to decrease the ion concentration of the first shallow well PW1 in the non-tuning region as the subsequent high temperature process proceeds.

In another example, the forming method for the adjustment region 320 to be a non-implantation region includes, for example: forming a mask layer on the substrate 100, the mask layer forming a shielding pattern in the adjustment region 320 of the isolation structure to partially expose the region of the isolation structure; next, an ion implantation process of a second doping type is performed to form an isolation doped region (including the first shallow well region PW 1), and ions are not implanted into the adjustment region 320 to form the non-implanted region.

Specifically, in the process of performing an ion implantation process to form an isolation doped region, the total amount of ions finally implanted in the isolation region is reduced by shielding a part of the isolation region from being implanted. Similarly, as the subsequent high temperature process proceeds, ions may be diffused into the non-implanted region to reduce the ion concentration of the isolation doped region in the non-tuned region.

In a further aspect, the substrate 100 has a doped layer of the first doping type. In this embodiment, the substrate 100 includes a base 110P and an epitaxial layer 120N formed on the base 110P, and the base 110P is specifically a base of a second doping type, and the epitaxial layer 120N is specifically an epitaxial layer of a first doping type, so that the epitaxial layer 120N forms a doped layer of the first doping type of the substrate 100.

And, the isolation structure 300 specifically includes at least two isolation doped regions (for example, P-type isolation doped regions) of the second doping type formed in the substrate 100, where the at least two isolation doped regions are sequentially disposed from bottom to top and are connected to each other, and the isolation doped region at the bottommost layer extends downward from the epitaxial layer 120N into the substrate 110P (it can also be considered that the isolation doped region at the bottommost layer extends upward from the substrate 110P into the epitaxial layer 120N). In a specific example, the isolation doped region may also extend from the high voltage side of the transistor region around the transistor region to the low voltage side of the transistor region. In this embodiment, the isolation structure 300 specifically includes: the first buried region PBL1 of the second doping type, the first deep well region DPW1 of the second doping type and the first shallow well region PW1 of the second doping type are connected with each other sequentially from bottom to top.

In an alternative embodiment, the method for preparing the isolation structure 300 may be as shown in fig. 8, 9, and 11-13: referring first to fig. 8, a substrate 110P is provided, and a patterned mask layer 520 is formed on the substrate 110P before the epitaxial layer 120N is formed; performing a second doping type ion implantation process (e.g., a P-type ion implantation process) on the substrate 110P under the mask of the mask layer 520 to form a first buried region PBL1; next, referring to fig. 9, an epitaxial process is performed to form an epitaxial layer 120N on the substrate 110P, and ions of the first buried region PBL1 may be further diffused upward into the epitaxial layer 120N during the epitaxial formation of the epitaxial layer 120N; next, referring to fig. 11, a patterned mask layer 540 is formed on the epitaxial layer 120N, and a second doping type ion implantation process (e.g., a P-type ion implantation process) is performed on the epitaxial layer 120N under the mask of the mask layer 540 to form a first deep well region DPW1; next, referring to fig. 13, a patterned mask layer 560 is formed on the epitaxial layer 120N, in this example, the mask layer 560 is formed with a blocking pattern 561 within the adjustment region 320 of the isolation structure so that only a region of the isolation structure is partially exposed, and then an ion implantation process of a second doping type (e.g., a P-type ion implantation process) is performed under the mask of the mask layer 560 to form a first shallow well region PW1, and the region covered by the blocking pattern 561 within the first shallow well region PW1 is not implanted with ions to form a non-implanted region.

In addition, while the first buried region PBL1, the first deep well region DPW1 and the first shallow well region PW1 of the isolation structure 300 are fabricated, a second buried region PBL2, a second deep well region DPW2 and a second shallow well region PW2 are correspondingly formed on the low voltage side, wherein the first buried region PBL1 and the second buried region PBL2 are connected to each other to form a ring structure, the first deep well region DPW1 and the second deep well region DPW2 are connected to each other to form a ring structure, and the first shallow well region PW1 and the second shallow well region PW2 are connected to each other to form a ring structure, thereby forming a ring-shaped isolation ring.

In an example, the method for manufacturing the isolation structure 300 further includes: the first isolation oxide layer 310 may be prepared, and particularly, as shown in fig. 12, the first isolation oxide layer 310 may be formed using a local oxidation isolation process (LOCOS). In this embodiment, the second isolation oxide layer 210 and the field oxide layer 220 are formed simultaneously with the preparation of the first isolation oxide layer 310.

One specific manufacturing method of the semiconductor device having the level shifter, which includes the manufacturing process of the level shifter and the manufacturing process of other circuits (e.g., high-side circuits), is described in detail below with reference to fig. 7 to 15.

Referring first to fig. 7, a substrate 110P is provided, wherein the substrate 110P is a substrate of a second doping type. In this embodiment, the substrate 110P is a P-type substrate, which may be doped with boron ions (B), for example, with an ion concentration of 1E13cm-3 to 1.5E15cm-3. Next, a mask layer 510 is formed on the substrate 110P, and an ion implantation process (e.g., an N-type ion implantation process) of a first doping type is performed under the mask of the mask layer 510 to form a fourth buried region NBL in the region of the high-side circuit. Thereafter, the mask layer 510 may be removed.

Next, referring to fig. 8, a mask layer 520 is formed on the substrate 110P, the mask layer 520 defining a pattern of a first buried region PBL1 and a pattern of a second buried region PBL2, the pattern of the first buried region PBL1 being located in the isolation region, the pattern of the second buried region PBL2 being located at a low voltage side of the transistor region, wherein the first buried region PBL1 surrounds a periphery of the transistor region and connects the second buried region PBL2; thereafter, a second doping type ion implantation process (e.g., a P-type ion implantation process) may be performed under the mask of the mask layer 520 to form first and second buried regions PBL1 and PBL2 within the substrate 110P. In this embodiment, a pattern of the third buried region PBL3 is further defined in the mask layer 520, and the pattern of the third buried region PBL3 is located in the transistor region, so that the third buried region PBL3 can be formed in the transistor region at the same time when the second doping type ion implantation process (e.g., P-type ion implantation process) is performed.

In a specific example, the first buried region PBL1, the second buried region PBL2 and the third buried region PBL3 may be specifically doped with boron, the implantation energy thereof is, for example, 20Kev to 100Kev, and the ion doping concentration thereof is, for example, 6E10cm ^-3 -6E14cm ^-3 。

Next, referring to fig. 9, an epitaxial layer 120N is epitaxially formed on the substrate 110P, and ions in the first, second, third and fourth buried regions PBL1, PBL2, PBL3 and NBL may be extended upward from the substrate 110P into the epitaxial layer 120N during the epitaxial formation of the epitaxial layer 120N. Wherein the epitaxial layer 120N is specifically an epitaxial layer of the first doping type, and the thickness thereof is, for example, 4 μm-9 μm; and the epitaxial layer 120N is doped with phosphorus, for example, with a doping concentration of 1E14 cm ^-3 -1.6E16 cm ^-3 。

Next, referring to fig. 10, a mask layer 530 is formed on the epitaxial layer 120N, the mask layer 530 defining a pattern of a third well region, and an ion implantation process of a first doping type (e.g., an N-type ion implantation process) may be performed under the mask of the mask layer 530 to form a third well region NW1 within the epitaxial layer 120N. In this embodiment, a pattern of the fourth well region NW2 is further defined in the mask layer 530, where the pattern of the fourth well region NW2 is located in the region of the high-voltage side circuit, so that the fourth well region NW2 can be formed simultaneously in the region of the high-voltage side circuit when the ion implantation process (e.g., the N-type ion implantation process) of the first doping type is performed. Thereafter, the mask layer 530 may be removed.

Next, referring to fig. 11, a mask layer 540 is formed on the epitaxial layer 120N, where the mask layer 540 defines a pattern of a first deep well region DPW1 and a pattern of a second deep well region DPW2, and the first deep well region DPW1 surrounds the periphery of the transistor region and is connected to the second deep well region DPW2; thereafter, an ion implantation process (e.g., a P-type ion implantation process) of a second doping type may be performed under the mask of the mask layer 540 to form the first and second deep well regions DPW1 and DPW2 within the epitaxial layer 120N. The bottom of the first deep well region DPW1 is connected to the first buried region PBL1 below the first deep well region DPW1, and the bottom of the second deep well region DPW2 is connected to the second buried region PBL2 below the second deep well region DPW2.

Next, referring to fig. 12, a first isolation oxide layer 310 is formed on the surface of the epitaxial layer 120N, where the first isolation oxide layer 310 is formed above the isolation doped region, and is used to form an isolation structure 300, so as to enhance the isolation performance of the isolation structure 300. The first isolation oxide layer 310 may be formed by a local oxidation isolation process (Local Oxidation of Silicon, LOCOS), for example, and specifically includes: a mask layer 550 is formed on the epitaxial layer 120N, and then an oxidation process is performed to form the first isolation oxide layer 310, after which the mask layer 550 may be removed. In this embodiment, the first isolation oxide layer 310 is formed, and the field oxide layer 220 and the second isolation oxide layer 210 are also formed.

Referring next to fig. 13, a mask layer 560 is formed on the epitaxial layer 120N, the mask layer 560 defining a pattern of a first shallow well region PW1 and a pattern of a second shallow well region PW2, wherein the first shallow well region PW1 surrounds the periphery of the transistor region and is connected to the second shallow well region PW2, and the mask layer 560 further forms a shielding pattern 561 in the region of the first shallow well region PW1 to define a pattern of a non-implanted region; thereafter, a second doping type ion implantation process (e.g., a P-type ion implantation process) may be performed under the mask of the mask layer 560 to form a first shallow well region PW1 and a second shallow well region PW2 in the epitaxial layer 120N, while a non-implantation region is also formed in the first shallow well region PW 1. And the bottom of the first shallow well region PW1 is connected to the first deep well region DPW1 below the first shallow well region PW1, and the bottom of the second shallow well region PW2 is connected to the second deep well region DPW2 below the second shallow well region PW2. Thus, an isolation ring can be formed on the periphery of the transistor region, and the second shallow well region PW2 is also used to form the channel inversion body of the field effect transistor.

Next, referring to fig. 14, an oxidation process is performed to form a gate oxide layer on the epitaxial layer 120N, and then a gate structure 200G is formed on the epitaxial layer 120N, wherein the gate structure 200G covers a portion of the second shallow well region PW2. In this embodiment, the gate structure 20G further extends to cover the field oxide layer 220 to form a field plate structure, so as to improve the voltage-withstanding performance of the device.

In a further aspect, a sidewall (not shown) may also be formed on the sidewall of the gate structure 200G. The preparation method of the side wall specifically comprises the following steps: depositing a side wall material, wherein the side wall material covers the top surface and the side wall of the grid structure 200G and also covers the surface of the substrate outside the grid structure; and then, performing an etching back process to remove the side wall material on the top surface of the gate structure and remove the side wall material on the top surface of the substrate, and keeping the side wall material of the side wall of the gate structure 200G to form the side wall.

Next, referring to fig. 15, an ion implantation process (e.g., an N-type ion implantation process) of a first doping type is performed to form a source region 200S and a drain region 200D, the source region 200S being formed in the second shallow well region PW2, and the drain region 200D being formed in the third well region NW 1. In this embodiment, the second contact region of the first doping type may also be formed simultaneously in the fourth well region NW2 in this step.

With continued reference to fig. 15, a second doping type ion implantation process (e.g., a P-type ion implantation process) is performed to form a first contact region 200B, the first contact region 200B is formed within the second shallow well region PW2, and the ion doping concentration of the first contact region 200B is higher than that of the second shallow well region PW 2.

In the method for manufacturing the semiconductor device shown in fig. 7 to 15, the manufacturing process of the level shifter and the manufacturing process of other circuits (for example, a high-voltage side circuit) are specifically included. However, in other examples, in the case of manufacturing a semiconductor device, the manufacturing process for the level shifter therein is not limited to the above-described method (i.e., may not be formed using the above-described method), as long as the structure of the level shifter as described above can be manufactured, and the manufacturing process of other circuits (for example, a high-voltage side circuit) can be combined on the basis of this. That is, in other examples, the method for manufacturing a semiconductor device includes processing on a substrate having a level shifter as described above to manufacture the semiconductor device, which still falls within the scope of the present invention.

It should be noted that, in the present description, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. And, while the present invention has been disclosed in terms of preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated. It should also be recognized that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses.

Claims

1. A level shifter, comprising:

a substrate having a doped layer of a first doping type;

a field effect transistor including a drain region of a first doping type, a source region of the first doping type, and a gate structure formed on the substrate and located between the source region and the drain region, the source region and the drain region both being formed within the doping layer;

the isolation structure is positioned at the periphery of the field effect transistor, the isolation structure comprises at least one isolation doped region with a second doping type formed in the doped layer, a plurality of adjustment regions are arranged in the at least one isolation doped region and are sequentially distributed along the extending direction of the isolation doped region, and grooves are formed in the adjustment regions or the adjustment regions are non-implanted regions.

2. The level shifter of claim 1, wherein the recess is further filled with an undoped material or a first doping type material.

3. The level shifter of claim 1, wherein the non-implanted region is a region of the isolation doped region that is not ion implanted during an ion implantation process.

4. The level shifter of claim 1, wherein a plurality of adjustment regions are arrayed within the isolation doped region.

5. The level shifter of claim 1, wherein the substrate comprises a base of a second doping type and an epitaxial layer of a first doping type disposed in sequence from bottom to top, the field effect transistor being formed on the epitaxial layer;

and the isolation structure comprises at least two isolation doped regions which are sequentially arranged from bottom to top and are connected with each other, wherein the isolation doped region at the bottommost layer extends upwards from the substrate into the epitaxial layer.

6. The level shifter of claim 5, wherein the isolation doped region in the isolation structure comprises a first shallow well region of a second doping type extending inward into the epitaxial layer from a top surface of the epitaxial layer; the method comprises the steps of,

The level shifter further includes a second shallow well region of a second doping type extending inwardly into the epitaxial layer from a top surface of the epitaxial layer, the second shallow well region being located on a side of the gate structure adjacent to a source region, the source region being formed within the second shallow well region, and the first shallow well region extending from outside the drain region around the field effect transistor to the second shallow well region to connect with the second shallow well region.

7. The level shifter of claim 6, wherein the isolation doped region in the isolation structure further comprises a first deep well region of a second doping type and a first buried region of a second doping type located below the first shallow well region and connected in sequence from top to bottom; the method comprises the steps of,

the level shifter further comprises a second deep well region of a second doping type and a second buried region of a second doping type which are positioned below the second shallow well region and sequentially connected from top to bottom, the first deep well region extends from the outer side of the drain region to the second deep well region to be connected with the second deep well region in a surrounding manner of the field effect transistor, and the first buried region extends from the outer side of the drain region to the second buried region to be connected with the second buried region in a surrounding manner of the field effect transistor.

8. The level shifter of claim 5, further comprising a plurality of third buried regions disposed side-by-side, the plurality of third buried regions being disposed between the source region and the drain region, and the third buried regions extending from the substrate up into the epitaxial layer.

9. The level shifter of claim 1, further comprising a third well region of the first doping type, the third well region being located on a side of the gate structure adjacent to a drain region, the drain region being formed within the third well region.

10. A semiconductor device comprising a level shifter according to any one of claims 1-9.

11. A method of manufacturing a level shifter, comprising: forming a field effect transistor on a substrate, wherein the field effect transistor comprises a drain region with a first doping type, a source region with the first doping type and a grid structure, the drain region and the source region are formed in the substrate, and the grid structure is formed on the substrate and is positioned between the source region and the drain region;

the substrate is provided with a doped layer with a first doping type, the source region and the drain region are both formed in the doped layer, and the preparation method of the level shifter further comprises the following steps: forming an isolation structure on the periphery of the field effect transistor, wherein the isolation structure comprises forming at least one isolation doped region with a second doping type in the doped layer, and setting a plurality of adjustment regions in the at least one isolation doped region, wherein the plurality of adjustment regions are sequentially arranged along the extending direction of the isolation doped region, and grooves are formed in the adjustment regions or the adjustment regions are non-implanted regions.

12. The method of manufacturing a level shifter of claim 11, wherein the method of manufacturing an isolation structure comprises:

forming a mask layer on the substrate, wherein the mask layer completely exposes the region of the isolation structure;

performing an ion implantation process of a second doping type to form at least one isolation doping region; the method comprises the steps of,

and etching at least the adjusting area in the isolation doped area of the topmost layer so as to form the groove in at least the isolation doped area of the topmost layer.

13. The method of manufacturing a level shifter of claim 12, further comprising, after forming the recess: and filling undoped materials or materials of the first doping type into the grooves.

14. The method of manufacturing a level shifter of claim 11, wherein the method of manufacturing an isolation structure comprises:

forming a mask layer on the substrate, wherein a shielding pattern is formed on the adjustment area of the isolation structure on the mask layer, so that the mask layer covers the adjustment area and partially exposes the area of the isolation structure;

an ion implantation process of a second doping type is performed to form an isolation doped region, and ions are not implanted in the adjustment region to form the non-implanted region.

15. The method of manufacturing a level shifter of claim 11, wherein the method of manufacturing an isolation structure comprises: performing an ion implantation process of a second doping type to form a first shallow well region;

and simultaneously implanting and forming a second shallow well region in the process of performing the ion implantation process, wherein the second shallow well region is positioned on one side of the gate structure close to a source region, the source region is formed in the second shallow well region, and the first shallow well region extends from the outer side of the drain region to the second shallow well region and is connected with the second shallow well region around the field effect transistor.

16. The method of manufacturing a level shifter of claim 15, wherein the substrate comprises a base of a second doping type and an epitaxial layer of a first doping type arranged in sequence from bottom to top; the preparation method of the isolation structure comprises the following steps:

performing an ion implantation process of a second doping type on the substrate before forming the epitaxial layer to form a first buried region of the second doping type in the substrate; the method comprises the steps of,

in the process of performing an epitaxial process to form the epitaxial layer on the substrate, ions in the first buried region are upwardly diffused into the epitaxial layer, and ion implantation processes of a second doping type are sequentially performed on the epitaxial layer twice to sequentially form a first deep well region and a first shallow well region, wherein the bottom of the first deep well region is connected with the first buried region, and the bottom of the first shallow well region is connected with the first deep well region.

17. The method of manufacturing a level shifter of claim 16, wherein a first buried region of the isolation structure is manufactured, and a second buried region is further formed at a low voltage side of the transistor region, the first buried region extending from a high voltage side of the transistor region around the transistor region to the low voltage side of the transistor region to connect the second buried region;

forming a second deep well region on the low-voltage side of the transistor region in addition to the first deep well region of the isolation structure, the first deep well region extending from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region to connect the second deep well region; the method comprises the steps of,

a second shallow well region is also formed in the low-voltage side of the transistor region in the first shallow well region of the isolation structure, the first shallow well region extending from the high-voltage side of the transistor region around the transistor region to the low-voltage side of the transistor region to connect the second shallow well region.

18. A method of manufacturing a semiconductor device, comprising the steps of the method of manufacturing a level shifter according to any one of claims 11 to 17;

alternatively, it includes: processing is performed on a substrate having a level shifter according to any one of claims 1 to 9 to produce the semiconductor device.