CN115831813A

CN115831813A - Method, device, equipment and medium for selecting wafer test batches

Info

Publication number: CN115831813A
Application number: CN202211414119.4A
Authority: CN
Inventors: 陶少杰; 陈娟
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2023-03-21

Abstract

The application provides a method, a device, equipment and a medium for selecting wafer test batches. And calculating a first relative error value taking the wafer batch newly arriving at the station as the test wafer batch according to the test information, and a second relative error value not taking the wafer batch as the test wafer batch. The relative error can reflect the credibility of the measurement, so that the first relative error value and the second relative error value can be compared to determine whether to use the wafer batch as a test batch. The above process can alleviate the problem of using the wafer lot not meeting the testing requirement for testing in the related art, and the selection logic of the testing lot does not need to be reset when the requirement ratio of the process station is updated.

Description

Method, device, equipment and medium for selecting wafer test batches

Technical Field

The embodiment of the application relates to the field of semiconductor equipment manufacturing, in particular to a method, a device, equipment and a medium for selecting wafer test batches.

Background

In order to improve the yield of semiconductor devices, some of the processing stations select a portion of the received wafer lots for a process Test (TECN). In practical applications, the required ratio of the test is set for the platform by the relevant personnel. I.e., the ratio of the number of lots used by the station for testing to the total number of lots entering the station. The lots for testing are then sorted in a conventional manner, such as by Lot (Lot) end-of-Lot (end-of-Lot) sorting, by Lot-to-station order sorting, and by Lot-to-Lot cycle sorting.

In practical applications, lots of wafers that do not meet the testing requirements often exist in the production line. The above selection method has the possibility of using the wafer lot that does not meet the testing requirement as the test, thereby affecting the process efficiency and the product yield. When the required ratio of the process stations is updated, the selection method needs to reset the selection logic of the test batches, such as reassigning the selection sequence to the stations, resetting the cycle range and the number of selections in the cycle, etc.

Disclosure of Invention

The embodiment of the application provides a method, a device, equipment and a medium for selecting wafer test batches, which are used for selecting the wafer test batches in a process station so as to improve the process efficiency and the product yield. When the required ratio of the process station is updated, the selection logic of the test batch is not required to be reset.

In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a method for selecting a wafer test lot, where the method includes:

after any wafer batch is monitored to reach a target process station, acquiring test information of the target process station; wherein, the testing information includes the total number of wafer lots that have arrived at the target process station, the number of testing wafer lots that have been selected by the target process station, and the required ratio of the target process station to the testing wafer lots;

determining a first relative error value when the wafer batch is used for testing and a second relative error value when the wafer batch is not used for testing according to the total number of the wafer batches, the number of the tested wafer batches and the required ratio;

determining whether to use the wafer batch for the test of the target process station according to the first relative error value and the second relative error value.

In some possible embodiments, before determining the first ratio and the second ratio according to the total number of the wafer lots and the number of the test wafer lots, the method further comprises:

determining that the wafer batch meets a preset clamping control condition;

the method further comprises the following steps:

monitoring whether any wafer batch meets the preset clamping control condition or not after reaching the target process station;

and if the wafer batch does not meet the preset clamping condition, not using the wafer batch as the test of the target process station.

In some possible embodiments, the preset stuck condition includes at least any one or a combination of the following conditions:

the method comprises the steps that firstly, whether a batch tail code of a wafer batch is a tail code for representing a test is judged;

second, whether the wafer batch is tested by the target process station or not is judged;

and thirdly, judging whether the total testing times of the wafer batch testing is larger than the testing time threshold value or not.

In some possible embodiments, the determining a first relative error value for the wafer lot to be tested and a second relative error value for the wafer lot not to be tested according to the total number of the wafer lots, the number of test wafer lots and the requirement ratio includes:

determining a first ratio of the number of test wafer lots to the total number of wafer lots when the wafer lots are used for testing and a second ratio of the number of test wafer lots to the total number of wafer lots when the wafer lots are not used for testing according to the total number of wafer lots and the number of test wafer lots;

determining the first relative error value and the second relative error value according to the first ratio, the second ratio and the demand ratio.

In some possible embodiments, the determining the first relative error value and the second relative error value according to the first ratio, the second ratio and the demand ratio comprises:

determining a first absolute error value and a second absolute error value according to the first ratio, the second ratio and the required ratio;

and determining the first relative error value according to the first absolute error value and the required ratio, and determining the second relative error value according to the second absolute error value and the required ratio.

In some possible embodiments, the determining a first absolute error value and a second absolute error value according to the first ratio, the second ratio, and the demand ratio includes:

and taking the absolute value of the difference between the first ratio and the required ratio as the first absolute error value, and taking the absolute value of the difference between the second ratio and the required ratio as the second absolute error value.

In some possible embodiments, the relative error value is determined by the following formula, the relative error value comprising the first relative error value and the second relative error value:

wherein Ratio is the demand Ratio, and Ratio1 is the first Ratio or the second Ratio; when Ratio1 is the first Ratio, δ is the first relative error value; when Ratio1 is the second Ratio, δ is the second relative error value.

In some possible embodiments, the determining whether to use the wafer lot for the testing of the target process station according to the first relative error value and the second relative error value includes:

when the first relative error value is less than or equal to the second relative error value, the wafer batch is used for the test of the target process station.

In some possible embodiments, the wafer lot carries identification information that indicates a total number of times the wafer lot participates in the test at each target process station; after the determining whether to use the wafer lot for the test of the target process station according to the first relative error value and the second relative error value, the method further comprises:

if the wafer batch is determined to be used for the test of the target process station, adding a test identifier for representing the requirement ratio in the identification information of the wafer batch, and updating the total test times in the identification information.

In a second aspect, an embodiment of the present application provides an apparatus for selecting wafer test lots, where the apparatus includes:

the information module is configured to acquire test information of a target process station after monitoring that any wafer batch reaches the target process station; wherein the testing information includes the total number of wafer lots that have arrived at the target process station, the number of testing wafer lots selected by the target process station, and the ratio of the demand of the target process station for the testing wafer lots;

an error module configured to determine a first relative error value for the wafer lot to be used for testing and a second relative error value for the wafer lot not to be used for testing according to the total number of the wafer lots, the number of the test wafer lots and the requirement ratio;

a testing module configured to perform a test for determining whether to use the wafer lot for the target process station according to the first relative error value and the second relative error value.

In some possible embodiments, before performing the determining the first ratio and the second ratio according to the total number of the wafer lots and the number of the test wafer lots, the error module is further configured to:

determining that the wafer batch meets a preset clamping control condition;

the error module is further configured to:

and if the wafer batch does not meet the preset clamping condition, not using the wafer batch as the test of the target process platform.

the method comprises the steps that firstly, whether a batch tail code of a wafer batch is a tail code for representing a test or not is judged;

In some possible embodiments, the determining a first relative error value for the wafer lot to be tested and a second relative error value for the wafer lot not to be tested according to the total number of the wafer lots, the number of test wafer lots and the requirement ratio is performed, and the error module is configured to:

In some possible embodiments, said determining said first and second relative error values as a function of said first ratio, said second ratio and said demand ratio is performed, said error module being configured to:

determining a first absolute error value and a second absolute error value according to the first ratio, the second ratio and the demand ratio;

In some possible embodiments, performing the determining a first absolute error value and a second absolute error value as a function of the first ratio, the second ratio, and the demand ratio, the testing module is configured to:

wherein Ratio is the demand Ratio, and Ratio1 is the first Ratio or the second Ratio; when Ratio1 is the first Ratio, δ is the first relative error value; when the Ratio1 is the second Ratio, δ is the second relative error value.

In some possible embodiments, the test module is configured to perform a test of determining whether to use the wafer lot for the target process station according to the first relative error value and the second relative error value, the test module configured to:

In some possible embodiments, the wafer lot carries identification information that indicates a total number of times the wafer lot participates in the test at each target process station; after performing the test of determining whether to use the wafer lot for the target process station according to the first relative error value and the second relative error value, the test module is further configured to:

and if the wafer batch is determined to be used for the test of the target process platform, adding a test identifier representing the required ratio in the identification information of the wafer batch, and updating the total test times in the identification information.

In a third aspect, an embodiment of the present application further provides an electronic device, including a memory and a processor, where the memory stores a computer program that is executable on the processor, and when the computer program is executed by the processor, the processor is caused to implement the steps of any one of the above-mentioned methods in the first aspect.

In a fourth aspect, this application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements the steps of any one of the methods in the first aspect.

In a fifth aspect, an embodiment of the present application is a computer program product, which includes computer instructions stored in a computer-readable storage medium; when the processor of the computer device reads the computer instructions from the computer readable storage medium, the processor executes the computer instructions, causing the computer device to perform the steps of any of the methods of the first aspect described above.

According to the technical scheme provided by the embodiment of the application, after any wafer batch is monitored to reach the target process station, the test information of the target process station is acquired. The testing information includes the total number of the wafer lots currently received by the target process station, the number of the selected testing wafer lots, and the required ratio of the target process station to the testing wafer lots. Determining a first relative error value of the newly arrived wafer batch as a test wafer batch and a second relative error value not as the test wafer batch according to the test information. Since the relative error can reflect the credibility of the measurement, the first relative error value and the second relative error value can be compared to determine whether to use the wafer lot as a test lot. The above process can alleviate the problem of using the wafer lot not meeting the testing requirement for testing in the related art, and the selection logic of the testing lot does not need to be reset when the requirement ratio of the process station is updated.

Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the present disclosure. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Fig. 1 is an overall flowchart of a method for selecting wafer test lots according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a relative error calculation according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another relative error calculation provided by an embodiment of the present application;

FIG. 4 is a schematic diagram illustrating a comparison between the present application and a conventional selection method provided in the embodiments of the present application;

FIG. 5 is a line graph comparing the present application with conventional selection methods provided in the examples of the present application;

FIG. 6 is a flowchart illustrating the overall process of selecting a test wafer lot at a station according to an embodiment of the present disclosure;

fig. 7 is a structural diagram of a device 700 for selecting wafer test lots according to an embodiment of the present disclosure;

fig. 8 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

The terms "first" and "second" in the description and claims of the present application and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the term "comprises" and any variations thereof, which are intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. The "plurality" in the present application may mean at least two, for example, two, three or more, and the embodiments of the present application are not limited.

As mentioned above, in the current semiconductor manufacturing process, the wafer lots for testing are selected by conventional methods such as selecting according to the end code of the wafer lots, selecting according to the arrival sequence of the wafer lots, and selecting within a fixed lot number period. These three options are described below.

The selection method is performed according to the end code of the wafer batch, namely, the fixed end code of the wafer batch used for testing is arranged on the process platform, and the wafer batch of the end code is used as the wafer batch for testing. Because the number of the tail codes is limited (the tail numbers are values 0-9), in order to avoid test conflicts, after a certain process station is provided with the fixed tail code used for the test, the fixed tail code can not be used as the test setting by other process stations. This will cause a certain degree of influence on both the testing efficiency and precision, and because the end codes of each wafer batch on the production line are randomly distributed, it will cost a lot of human resources to measure the selection ratio, and there are problems of human error and low efficiency.

The wafer lots to be tested are selected according to the arrival sequence of the wafer lots, that is, the wafer lots to be tested are selected according to the cycle of the arrival wafer lots, for example, when the required ratio is 10%, every 10 wafer lots are used as a cycle, the 1 st lot, the 11 th lot and the 21 st lot \8230needto be used for the arrival. Since the selection method selects the test wafer lots according to the fixed lots, there is a risk that the wafer lots not meeting the test conditions on the production line are used for testing, which may cause unpredictable risk to the process. In addition, the selection mode has a limit on the required ratio, and the proportion precision of minimum selection cannot be lower than 10%. And a regular required ratio, for example, a ratio of 10%, 15%, 20% such as a ratio floating in units of 5%, is set. Settings like 17%, 18% cannot be realized. The demand ratio is typically set manually, and can be modified at any time during the processing of the wafer batch according to business requirements. The demand Ratio is a requirement for the real Ratio (Branch Ratio) in the station, for example, 5% of the demand Ratio means that the real Ratio for testing in the station should reach 5%. BranchRatio is the ratio of the number of test lots that are used for testing by a station to the total number of lots that have arrived at the station.

The above-mentioned method of selecting from the fixed lot number period is to select the first M lots meeting the testing condition from every N lots of wafer lots arriving at the station for testing. For example, every 10 lots of wafer lots are used as a cycle, and the first M lots meeting the test conditions are selected from the 10 lots of wafer lots at the destination station for testing. The problem with this selection is that if there are not enough lots of wafers in a single cycle to meet the test conditions, the real ratio used for testing in that cycle will be lower than the required ratio.

Further, if the above conditions exist in multiple cycles, errors will be accumulated and the on-line production test will be affected. In addition, the cycle setting for the wafer lots in the selection method usually does not exceed 20 lots per cycle, because the larger the number of wafer lots in a single cycle, the more concentrated the wafer lots selected for testing by the selection method. The smaller the number of wafer lots in a single cycle, the higher the probability of the error between the Branch Ratio and the demand Ratio, and therefore, the selection range of the cycle setting of the wafer lots in the selection method is mostly 10 to 20 lot cycles. This results in a particle selection accuracy (i.e., the above-mentioned required ratio) of up to 5% and only an integral multiple of 5%, which has a problem of low particle selection accuracy and large limitation.

In addition, each of the above-mentioned selection methods has a similar problem in that when the requirement ratio of the process stations is updated, the selection methods should re-set the selection logic of the test lots, such as re-assigning the selection sequence to the stations, re-setting the cycle range and the number of selections within the cycle, etc., which causes additional labor burden and resource loss.

In order to solve the above problems, the inventive concept of the embodiments of the present application is: after any wafer batch is monitored to reach the target process station, the test information of the target process station is obtained. The testing information includes the total number of the wafer lots currently received by the target process station, the number of the selected testing wafer lots, and the required ratio of the target process station to the testing wafer lots. Determining a first relative error value of the wafer batch newly arriving at the station as a test wafer batch according to the test information, and a second relative error value of the wafer batch not as the test wafer batch. Since the relative error can reflect the credibility of the measurement, the first relative error value and the second relative error value can be compared to determine whether to use the wafer lot as a test lot. The above process can alleviate the problem of using the wafer lot not meeting the testing requirement for testing in the related art, and the selection logic of the testing lot does not need to be reset when the requirement ratio of the process station is updated.

Referring to fig. 1, fig. 1 is a general flowchart of a method for selecting wafer test lots according to an embodiment of the present application, which specifically includes:

step 101: after any wafer batch is monitored to reach a target process station, acquiring test information of the target process station; wherein the testing information includes the total number of wafer lots that have arrived at the target process station, the number of testing wafer lots selected by the target process station, and the ratio of the demand of the target process station for the testing wafer lots;

the process station is used for carrying out process preparation on the semiconductor equipment on the production line. In order to increase the yield, a certain number of wafer lots are required to be set for some process stations for process testing, and these process stations are the target process stations in step 101.

In order to further increase the yield of the product, the embodiment of the present application sets a predetermined clamping condition for the wafer lot to be tested according to the process requirement in the actual production process. The preset stuck condition in the embodiment of the present application at least includes any one or a combination of the following conditions:

some manufacturers will set up a Mapping Table (Mapping Table) for recording the wafer lots available for testing, i.e. the wafer lots with the tail code in the tail Table can be used as the test selection for the process station. When the end code of the wafer lot newly arriving at the station is not in the end code table, the wafer lot is not suitable for testing, otherwise, unpredictable risk is caused to the process.

according to the process configuration, the tested wafer lot has the possibility of returning to the process station after testing. In order to increase the testing precision, the same wafer batch should not be tested many times in the same process station. Therefore, when the wafer lot is detected to be tested at the target process station, the wafer lot can be set to be not used for the test of the target process station.

And the third condition is whether the total testing times for executing the wafer batch test is greater than the testing time threshold value.

Lots are sent to multiple processing stations along with the processing of the production line, i.e., the lots may have been tested by multiple target processing stations before being sent to the target processing station. In order to improve the testing accuracy, a reasonable threshold value can be set, and when the total testing times of any wafer batch participating in the testing is greater than the testing time threshold value, the wafer batch is not used for testing any target process station.

In practice, a Script program can be used to mount Script program code for each target process station, which is triggered when any wafer lot arrives at the station. Specifically, the test tag can be set for the wafer lot by field setting, and the tag records the data such as the end code of the wafer lot, whether the test of the current target process station is executed, and the total number of tests that have been executed. Therefore, after any wafer batch reaches the target process station, whether the wafer batch meets the preset clamping control condition or not is determined by monitoring the label.

In the embodiment of the present application, if the wafer lot does not satisfy any of the preset chucking conditions, the wafer lot is not used for the test of the current target process station. Accordingly, when the wafer lot satisfies all of the predetermined chucking conditions, the determination of step 102 is performed on the wafer lot, and it is determined whether to use the wafer lot for the test of the currently arriving target process station through the following step 102.

Step 102: determining a first relative error value when the wafer batch is used for testing and a second relative error value when the wafer batch is not used for testing according to the total number of the wafer batches, the number of the tested wafer batches and the required ratio;

before describing the above step 102, a concept of "relative error" will be described first.

Relative error refers to the value obtained by multiplying the ratio of the absolute error caused by measurement to the agreed measured true value by 100%, expressed as a percentage. Specifically, the formula is shown in the following formula (1):

wherein, δ is relative error, Δ is absolute error, y is real measurement result, and t is appointed measured true value. The relative error is used to determine the degree of confidence in the reaction measurement.

As described in step 101, after the wafer lot arrives at the target process station, the testing information of the target process station is acquired. The testing information includes the total number of lots that have arrived at the target process station, the number of testing lots that have been used by the target process station for testing, and the required ratio of the target process station to the testing requirements.

Taking the selection of the lot for testing in the target process station as a measure of the data, the concept of introducing the above-mentioned relative error is obtained. In the measurement process, the agreed measured true value t is the required ratio of the target process station to the testing requirement. The real measurement result is the real ratio used as the test by the target process station, i.e. the branch ratio mentioned above.

When the step 102 is executed, the relative error value corresponding to the wafer lot is determined according to the following formula (2):

In practice, a first ratio between the number of test wafer lots when the wafer lot is used for testing and the total number of wafer lots is determined according to the total number a of wafer lots and the number b of test wafer lots, and a second ratio between the number of test wafer lots when the wafer lot is not used for testing and the total number of wafer lots is determined. For example, the total number a of wafer lots is 10, and the number b of test wafer lots is 1. If the current lot reaches the target process station, the lot a is always updated to 11, and if the lot is used for testing, b is updated to 2, and then the first ratio is obtained: b/a =2/11; accordingly, if the lot is not used as a test, b does not need to be updated and remains 1. b/a =1/11.

And then determining a first relative error value delta Y and a second relative error value delta N according to the first Ratio Y, the second Ratio N and the requirement Ratio of the test. Specifically, as shown in fig. 2, a first absolute error value | Ratio y-Ratio | representing a measured absolute error Δ may be obtained by substituting the first Ratio y as a true measurement result y and the required Ratio as an agreed measured true value t into the above formula (1). The first absolute error value is an absolute value of a difference between the first ratio and the required ratio. Correspondingly, a second absolute error value | Ratio n-Ratio | of the measured absolute error Δ can be obtained by substituting the second Ratio as the true measurement result y and the required Ratio as the agreed measured true value t into the above formula (1), where the second absolute error value is the absolute value of the difference between the second Ratio and the required Ratio. And then determining a first relative error value delta Y and a second relative error value delta N according to the first absolute error value | Ratio-Ratio |, the second absolute error value | Ratio-Ratio |, and the requirement Ratio by the formula (2).

In the application scenario shown in fig. 3, before the wafer lot 1 reaches the target process station a, the test information of the target process station a is: when lot 1 reaches target station a, the total number of lots a =20, the number of test lots b =3 used for testing by the target station, and the Ratio of demand at the target station =15%, the total number of lots a =20+1=21 is updated.

Then, a first ratio of the number of test lots to the total number of wafer lots when wafer lot 1 is used as a test wafer is calculated to be = (3 + 1)/21, and a second ratio of the test lot to the total number of wafer lots when wafer lot 1 is not used as a test wafer is calculated to be 3/21. Then, a first relative error value δ Y = | Ratio Y-Ratio |/Ratio 100% is determined according to the first Ratio Y and the demand Ratio, and a second relative error value δ N = | Ratio N-Ratio |/Ratio 100% is determined according to the second Ratio N and the demand Ratio. Finally, by comparing δ Y and δ N, it is determined whether the wafer lot is to be used as a test according to step 103 below.

Step 103: determining whether to use the wafer batch for the test of the target process station according to the first relative error value and the second relative error value.

As mentioned previously, the relative error is used to reflect the degree of confidence in the measurement. Therefore, if the first relative error value is smaller than the second relative error value, it indicates that the relative error generated when the wafer lot is used for testing is smaller than the relative error generated when the wafer lot is not used for testing. That is, the wafer lot used for testing tends to be more toward the predetermined demand ratio.

Thus, when the first relative error value is less than or equal to the second relative error value, the wafer lot may be used for testing of the target process station. Otherwise, the wafer lot is not used for testing of the target process station. That is, if δ Y is less than or equal to δ N, the wafer lot is used for testing; if δ Y > δ N, the wafer lot is not used for testing.

Next, as shown in fig. 4, fig. 4 shows an example of testing 40 lots with a requirement ratio of 20% at the process station, which respectively adopts the above-described first selection method according to the sequence from the station, second selection method according to the fixed lot number period, and comparison of the selection data for the test wafer lot selection according to the present invention.

In the following, each 10 batches are taken as a period, and first, the sorted data of the first mode and the second mode are compared to each other, so that the sorted data of the first mode and the second mode are identical in an ideal state. However, the first method cannot select the test wafer lot satisfying the required ratio when the wafer lot not satisfying the condition is encountered, and the second method can adapt to the problem to some extent in the cycle, but cannot select the test wafer lot satisfying the required ratio when the wafer lots not satisfying the condition are continuously present.

Specifically, referring to the 31-40 batches of picking data in FIG. 4, the ideal picking data for the first and second modes are the same. The ideal state is that there is no situation in which the current wafer lot is determined by the process station to be used as the test, but the wafer lot cannot be tested because it does not satisfy the test condition (i.e. corresponds to the case marked with "x" in fig. 4). Then, the selection data of 1-10 lots is reviewed, and when the wafer lots meeting the unsatisfied condition in the cycle, the test wafer lot number meeting the required ratio cannot be selected in a mode. Although the second method can be adapted to a certain degree in the cycle, it can be found by referring to the selection data of 11-30 lots that the second method also cannot select the test wafer lots satisfying the required ratio when there are consecutive wafer lots not satisfying the condition.

At this time, it can be found by looking at the selection data of the present application, that the present application does not relate to the concept of cycle selection, and although there may be a case that the ratio does not satisfy the requirement in the cycle (for example, only one batch is selected for testing in the 11-20 batches corresponding to the cycle 2, and the ratio does not satisfy the requirement in the cycle), the present application can dynamically adjust the wafer batch used for testing according to the comparison of the relative errors, so as to satisfy the requirement to the maximum extent of the final testing accuracy. Namely, 8 batches are selected for testing in the final 40 batches in total, the real ratio is 8/40 × 100% =20%, and the requirement of the demand ratio of 20% is met.

In addition, as shown in fig. 5, fig. 5 shows the linear comparison result between the selection data corresponding to each selection manner in fig. 4 and the requirement ratio, and it can be seen visually from fig. 5 that, in the whole selection process, the linear curve for selecting the test wafer batch by using the technical scheme of the present application can tend to the requirement ratio more, the error floating between the whole process and the requirement ratio is small, and the overall fluctuation of the curve is relatively flat, so that the situation that the real-time error is too large or too small can be greatly reduced by using the technical scheme of the present application.

To facilitate understanding of the technical solutions provided in the embodiments of the present application, fig. 6 shows a flowchart of the whole selecting process after any wafer lot arrives at the target process station, which specifically includes:

step 601: after monitoring that any wafer batch arrives at the station, acquiring test information of the station; the testing information includes the total number of wafer lots that have arrived at the station, the number of testing wafer lots that have been used for testing by the station, and the ratio of the demands of the station on the testing wafer lots.

Step 602: monitoring whether the wafer batch meets a preset clamping condition or not;

step 603: if the preset clamping condition is not met, the wafer batch is not used for the test of the current station;

step 604: if the preset clamping control condition is met, determining a first relative error value when the wafer batch is used for testing and a second relative error value when the wafer batch is not used for testing according to the testing information based on a relative error algorithm;

step 605: judging whether the first relative error value is larger than the second relative error value;

step 606: if the second relative error value is less than or equal to the first relative error value, the wafer batch is used as the test wafer batch of the station; otherwise, the step 603 is executed to not use the wafer lot for the testing at the station.

In the process, after any wafer batch is monitored to reach the target process station, the test information of the target process station is acquired. And calculating a first relative error value taking the wafer batch newly arriving at the station as the test wafer batch according to the test information, and a second relative error value not taking the wafer batch as the test wafer batch. Since the relative error can reflect the credibility of the measurement, the first relative error value and the second relative error value can be compared to determine whether to use the wafer lot as a test lot. Therefore, the problem that the wafer batches which do not meet the testing requirements are used for testing in the related art is relieved, and the selection logic of the testing batches is not required to be reset when the requirement ratio of the process station is updated.

As mentioned above, the embodiment of the present application adds identification information for detecting the default chucking condition to the wafer lot. Therefore, when the wafer lot is determined to be used for the test of the target process station through the above process, a test identifier for indicating that the wafer lot participates in the test of the current target process station needs to be added to the identifier information of the wafer lot, and the total test times in the identifier information is updated, that is, the total test times is increased by one. Therefore, when the wafer batch flows through other target process stations from the production line, the other target process stations can carry out card control condition verification on the wafer batch according to the updated identification information.

Based on the same inventive concept, the embodiment of the present application provides a device 700 for selecting wafer test batches, specifically as shown in fig. 7, including:

an information module 701 configured to acquire test information of a target process station after monitoring that any wafer batch reaches the target process station; wherein the testing information includes the total number of wafer lots that have arrived at the target process station, the number of testing wafer lots selected by the target process station, and the ratio of the demand of the target process station for the testing wafer lots;

an error module 702 configured to determine a first relative error value for the wafer lot to be tested and a second relative error value for the wafer lot not to be tested according to the total number of the wafer lots, the number of the test wafer lots and the requirement ratio;

a testing module 703 configured to perform a test for determining whether to use the wafer lot for the target process station according to the first relative error value and the second relative error value.

determining that the wafer batch meets a preset clamping control condition;

the error module is further configured to:

In some possible embodiments, the testing module is configured to perform the test of determining whether to use the wafer lot for the target process station according to the first relative error value and the second relative error value, and the testing module is configured to:

In some possible embodiments, the wafer lot carries identification information that indicates a total number of times the wafer lot participates in the test at each target process station; after performing the test to determine whether to use the wafer lot for the target process station according to the first and second relative error values, the test module is further configured to:

The electronic device 130 according to this embodiment of the present application is described below with reference to fig. 8. The electronic device 130 shown in fig. 8 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 8, the electronic device 130 is represented in the form of a general electronic device. The components of the electronic device 130 may include, but are not limited to: the at least one processor 131, the at least one memory 132, and a bus 133 that connects the various system components (including the memory 132 and the processor 131).

Bus 133 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.

The memory 132 may include readable media in the form of volatile memory, such as Random Access Memory (RAM) 1321 and/or cache memory 1322, and may further include Read Only Memory (ROM) 1323.

Memory 132 may also include a program/utility 1325 having a set (at least one) of program modules 1324, such program modules 1324 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

The electronic device 130 may also communicate with one or more external devices 134 (e.g., keyboard, pointing device, etc.), with one or more devices that enable a user to interact with the electronic device 130, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 130 to communicate with one or more other electronic devices. Such communication may occur via input/output (I/O) interfaces 135. Also, the electronic device 130 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 136. As shown, network adapter 136 communicates with other modules for electronic device 130 over bus 133. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with electronic device 130, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, to name a few.

In an exemplary embodiment, a computer-readable storage medium comprising instructions, such as the memory 132 comprising instructions, executable by the processor 131 of the apparatus to perform the method described above is also provided. Alternatively, the computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

In an exemplary embodiment, a computer program product is also provided, which includes computer program/instructions, when executed by the processor 131, to implement any one of the wafer test lot selection methods provided herein.

In an exemplary embodiment, aspects of a method for selecting a wafer test lot provided by the present application may also be implemented in the form of a program product, which includes program code for causing a computer device to execute the steps of the method for selecting a wafer test lot according to various exemplary embodiments of the present application described above in this specification when the program product runs on the computer device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The selected program product for a wafer test lot of embodiments of the present application may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on an electronic device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the PowerPC programming language or similar programming languages. The program code may execute entirely on the consumer electronic device, partly on the consumer device, as a stand-alone software package, partly on the consumer electronic device and partly on a remote electronic device, or entirely on the remote electronic device or server. In the case of remote electronic devices, the remote electronic devices may be connected to the consumer electronic device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external electronic device (e.g., through the internet using an internet service provider).

It should be noted that although in the above detailed description several units or sub-units of the apparatus are mentioned, such a division is merely exemplary and not mandatory. Indeed, the features and functions of two or more units described above may be embodied in one unit, according to embodiments of the application. Conversely, the features and functions of one unit described above may be further divided into embodiments by a plurality of units.

Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable image scaling apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable image scaling apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable image scaling apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable image scaling device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method for selecting wafer test batches, the method comprising:

after monitoring that any wafer batch reaches a target process station, acquiring test information of the target process station; wherein, the testing information includes the total number of wafer lots that have arrived at the target process station, the number of testing wafer lots that have been selected by the target process station, and the required ratio of the target process station to the testing wafer lots;

2. The method of claim 1, wherein before determining the first ratio and the second ratio based on the total number of wafer lots and the number of test wafer lots, the method further comprises:

determining that the wafer batch meets a preset clamping control condition;

the method further comprises the following steps:

3. The method according to claim 2, wherein the preset stuck condition comprises at least any one or a combination of the following conditions:

4. The method of claim 1, wherein determining a first relative error value for testing the wafer lot and a second relative error value for testing the wafer lot without the wafer lot according to the total number of wafer lots, the number of test wafer lots and the requirement ratio comprises:

and determining the first relative error value and the second relative error value according to the first ratio, the second ratio and the requirement ratio.

5. The method of claim 4, wherein determining the first and second relative error values as a function of the first ratio, the second ratio, and the demand ratio comprises:

6. The method of claim 5, wherein determining a first absolute error value and a second absolute error value based on the first ratio, the second ratio, and the demand ratio value comprises:

7. The method of claim 4, wherein the relative error value is determined by the following equation, the relative error value comprising the first relative error value and the second relative error value:

8. The method of claim 1, wherein the determining whether to use the wafer lot for the testing of the target process station according to the first and second relative error values comprises:

9. The method of any of claims 1-8, wherein the wafer lot carries identification information that characterizes a total number of times the wafer lot participates in the test at each target process station; after the determining whether to use the wafer lot for the test of the target process station according to the first relative error value and the second relative error value, the method further comprises:

10. An apparatus for selecting wafer test lots, the apparatus comprising:

an error module configured to determine a first relative error value for using the wafer lot for testing and a second relative error value for not using the wafer lot for testing according to the total number of the wafer lots, the number of test wafer lots and the required ratio;

11. An electronic device, comprising:

a memory for storing program instructions;

a processor for calling program instructions stored in said memory and for executing the steps comprised by the method of any one of claims 1 to 9 in accordance with the obtained program instructions.

12. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program comprising program instructions that, when executed by a computer, cause the computer to perform the method of any of claims 1-9.

13. A computer program product, the computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the method according to any of claims 1-9.