CN115831789A - Preparation method of battery piece - Google Patents
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- CN115831789A CN115831789A CN202211430229.XA CN202211430229A CN115831789A CN 115831789 A CN115831789 A CN 115831789A CN 202211430229 A CN202211430229 A CN 202211430229A CN 115831789 A CN115831789 A CN 115831789A
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Abstract
The invention discloses a preparation method of a battery piece, which comprises the following steps: step S100: providing a textured N-type silicon wafer, and carrying out doping treatment on the front surface of the silicon wafer to form a front-surface doped layer; step S101: reacting the back surface of the silicon wafer after alkali polishing with oxygen in the air to generate a first oxide layer; step S102: testing the thickness TH1 of the first oxide layer; step S103: depositing a tunneling oxide layer on the surface of the first oxide layer; step S104: testing the total thickness TH2 of the tunneling oxide layer and the first oxide layer; step S105: calculating the thickness TH3= TH2-TH1 of the tunneling oxide layer; step S106: in step S105, if the tunneling oxide layer thickness TH3 is less than 1.2nm or greater than 2.0nm, the steps S100 to S105 are performed again after the adjustment process. Compared with the prior art, the method has the advantages that the thickness measuring step is additionally arranged before the tunneling oxide layer is deposited, so that the test result of the thickness of the tunneling oxide layer is more accurate, and favorable conditions are created for the subsequent production of the battery piece.
Description
Technical Field
The invention relates to the technical field of photovoltaic cells, in particular to a preparation method of a cell.
Background
TOPCon is a Tunnel Oxide Passivated Contact (Passivated Contact) solar cell technology based on the selective carrier principle, the cell structure is an N-type silicon substrate cell, a layer of Tunnel Oxide is prepared on the back of the cell, then a layer of doped polycrystalline silicon layer is deposited, and the passivation Contact structure is formed by the Tunnel Oxide Passivated Contact and the doped polycrystalline silicon layer, so that the surface recombination and the metal Contact recombination are effectively reduced.
The current market general method for testing the thickness of the tunneling oxide layer comprises the following steps:
firstly, the whole cell slice utilizes SEM to observe the cross section and utilizes a measuring tool carried by the system to directly measure, fragments need to be tested in the mode, and the test result is different from person to person;
and the second is direct measurement by an ellipsometer, and the relative value is measured and calculated in such a way, so that the test result is higher than the actual value.
Disclosure of Invention
The invention aims to provide a preparation method of a battery piece, which aims to solve the technical problem that the thickness measuring part of a tunneling oxide layer in the prior art is accurate and create favorable conditions for producing a compliant battery piece.
The invention provides a preparation method of a battery piece, which comprises the following steps:
step S100: providing a textured N-type silicon wafer, and carrying out doping treatment on the front surface of the silicon wafer to form a front-surface doped layer;
step S101: manufacturing a polished surface on the back surface of a silicon wafer, and reacting the back surface of the silicon wafer with oxygen in the air to generate a first oxide layer after alkali polishing;
step S102: testing the thickness TH1 of the first oxide layer;
step S103: depositing a tunneling oxide layer on the surface of the first oxide layer;
step S104: testing the total thickness TH2 of the tunneling oxide layer and the first oxide layer;
step S105: calculating the thickness TH3= TH2-TH1 of the tunneling oxide layer;
step S106: in the step S105, if the thickness TH3 of the tunnel oxide layer is smaller than 1.2nm or larger than 2.0nm, the steps S100 to S105 are executed again after the adjustment process until the thickness TH3 of the tunnel oxide layer is 1.2 to 2.0nm.
Step S107: depositing a passivation film layer on the front surface and the back surface of the silicon wafer respectively;
step S108: and respectively preparing metal electrodes on the front surface and the back surface of the silicon wafer.
In the above method for manufacturing a battery plate, preferably, the step S103 further includes:
step S1031: ensuring that the temperature of the furnace tube of the diffusion furnace reaches a set value, and setting the temperature range to be 500-800 ℃;
step S1032: putting a silicon wafer into a furnace tube;
step S1033: pumping the pressure to a bottom pressure, testing the leakage rate and ensuring the air tightness to be qualified;
step S1034: raising the temperature of the furnace tube to a target value of 550-650 ℃;
step S1035: stabilizing the temperature of each temperature zone of the furnace tube at a target value of 550-650 ℃;
step S1036: constant-temperature high-concentration oxidation, maintaining for the first time, controlling the pressure at 700000-1000000mTorr, controlling the temperature at the first temperature, and maintaining the oxygen flow at the first flow;
step S1037: pumping away the oxygen remaining in the step S1066;
step S1038: cooling the furnace tube to room temperature;
step S1039: filling the tube with nitrogen, reducing the pressure difference between the inside and the outside of the tube, and taking out the sample piece to be tested.
The above method for preparing a battery piece, wherein the adjusting process in step S106 is preferably:
if the tunneling oxide layer thickness TH3 is smaller than 1.2nm in step S105, increasing the first time, increasing the first temperature, and increasing the first flow rate;
if the tunneling oxide layer thickness TH3 is greater than 2.0nm in step S105, decreasing the first time, decreasing the first temperature, and decreasing the first flow rate;
in the above method for manufacturing a battery piece, preferably, in step S103, the tunnel oxide layer is deposited in a diffusion furnace tube, and the silicon piece is sent out of the diffusion furnace tube at a predetermined temperature.
The preparation method of the battery piece is characterized in that the preset temperature is preferably 20-25 ℃.
In the above method for manufacturing a battery piece, preferably, in step S104, after the silicon piece is sent out of the diffusion furnace tube, plastic packaging and winding are performed for a preset time to isolate air.
The preparation method of the battery piece is preferably, wherein the preset time is 20min to 30min.
In the above method for manufacturing a battery plate, preferably, in the steps S102 and S104, a plurality of silicon plates are distributed in a quartz boat at intervals in a horizontal direction, and one silicon plate located in the middle is selected to measure thickness data.
In the above method for manufacturing a battery plate, it is preferable that the thickness data is measured by a laser ellipsometer in the steps S102 and S104.
In the above method for manufacturing a battery piece, preferably, the first oxide layer has a thickness TH1 of 0.4 to 0.6nm, and a total thickness TH2 of the tunneling oxide layer and the first oxide layer is 1.7 to 2.4nm.
Compared with the prior art, the method adds a thickness measuring step before depositing the tunneling oxide layer, so that the thickness measuring result of the tunneling oxide layer is more accurate, and favorable conditions are created for the subsequent production of the battery piece.
Drawings
Fig. 1 is a schematic structural diagram of a battery cell provided in an embodiment of the invention;
fig. 2 is a flowchart of a method for manufacturing a battery cell according to an embodiment of the present invention.
Description of reference numerals:
the method comprises the following steps of 1-a silicon chip, 2-a front surface, 3-a back surface, 4-a first oxide layer, 5-a tunneling oxide layer, 6-a back surface doped layer, 7-a back surface passivation layer, 8-a front surface doped layer, 9-a front surface passivation layer, 10-a first electrode and 11-a second electrode.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The TOPCon (Tunnel Oxide passivation Contacts) cell is a solar cell with a passivated contact of a tunneling Oxide layer based on the selective carrier principle. The back surface of the metal electrode is usually in a combined structure of an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer, so that a passivation contact effect is realized, the metal electrode is not in direct contact with c-Si, the reduction of the combination of carriers is facilitated, and the separation and collection of the carriers are realized.
The thickness of the tunneling oxide layer is an important parameter, excellent interface passivation and carrier selective collection can be achieved within a proper thickness range, and the thickness of the oxide layer before the process of producing the tunneling oxide layer is ignored in a traditional method for testing the thickness of the tunneling oxide layer (the surface of a silicon wafer after alkali polishing is sensitive to the environment, and the oxide layer grows faster), so that the actual value is large, and troubles are caused for the development of a subsequent tunneling structure.
In order to measure the thickness of the tunneling oxide layer more accurately and obtain better battery conversion efficiency, the embodiment of the invention provides a preparation method of a battery piece.
In the examples provided herein, referring to fig. 1, the prepared battery piece includes:
the solar cell comprises a silicon wafer 1, wherein the silicon wafer 1 is provided with a front surface 2 and a back surface 3, the front surface 2 and the back surface 3 are arranged oppositely along the thickness direction of the silicon wafer 1, the front surface 2 is a light receiving surface facing the sunlight irradiation direction, and the back surface 3 is a surface opposite to the front surface 2. The silicon wafer 1 may be, for example, a wafer including a crystalline semiconductor containing a dopant of the first conductivity type. The crystalline semiconductor may be polycrystalline silicon, monocrystalline silicon, or quasi-monocrystalline silicon, a specific type of the crystalline semiconductor is not limited by the embodiment of the present invention, and the first conductive type dopant may be an N-type dopant such As a V-group element including phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), or a P-type dopant including a III-group element such As boron (B), aluminum (Al), gallium (Ga), indium (In).
And the tunneling oxide layer 5 is positioned on the back surface 3, and the tunneling oxide layer 5 is used for performing interface passivation on the back surface 3 of the silicon wafer 1, so that the recombination of carriers at the interface is reduced, and the transmission efficiency of the carriers is ensured.
In the embodiments provided herein, the tunnel oxide layer 5 includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride. The materials have good interface dangling bond passivation effect and tunneling effect, and the thickness of the tunneling oxide layer 5 is 0.85nm-1.9nm. Specifically, the thickness of the tunnel oxide layer 5 is 0.85nm, 0.9nm, 1.0nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 1.9nm, or the like, but may be other values within the above range, and is not limited thereto.
The tunneling oxide layer 5 allows many photons to tunnel into the back doping layer 6 and simultaneously blocks few photons from passing through, so that many photons are transversely transported in the back doping layer 6 and collected by the first electrode 10, the tunneling oxide layer 5 and the back doping layer 6 form a passivation contact structure of the tunneling oxide layer 5, excellent interface passivation and carrier selective collection can be achieved, carrier recombination is reduced, and photoelectric conversion efficiency of the solar cell is improved. It is noted that the tunnel oxide layer 5 may not in practice have a perfect tunnel barrier, since it may for example contain defects such as pinholes, which may cause other charge carrier transport mechanisms (e.g. drift, diffusion) to dominate over the tunnel effect.
A back doped layer 6 formed on the surface of the tunnel oxide layer 5. In the embodiment provided in the present application, the back doped layer 6 is formed by doping amorphous silicon, microcrystalline silicon, polysilicon, etc. with N-type dopants. In the embodiment provided by the application, the back side doping layer 6 is a doped polysilicon layer, and a first doping element of the doped polysilicon layer is matched with a first conductive type dopant of the silicon wafer 1; in one possible embodiment, when the silicon wafer 1 is an N-type crystal silicon wafer 1, the first doping element of the doped polysilicon layer is phosphorus; when the silicon wafer 1 is a P-type crystal silicon wafer 1, the first doping element of the doped polycrystalline silicon layer is boron. The back surface doping layer 6 has a thickness of 20nm to 300nm, and may be 20nm, 40nm, 50nm, 80nm, 100nm, 120nm, 150nm, 200nm, 220nm, 250nm, or 300nm, for example. Other values within the range are also possible and are not limited herein.
And the back passivation layer 7 is arranged on the back doping layer 6, and the back passivation layer 7 comprises at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer and a silicon oxynitride layer. The back passivation layer 7 can passivate the back surface 3 of the cell, reduce the carrier recombination speed of the back surface 3 and improve the photoelectric conversion efficiency.
A first electrode 10, wherein the first electrode 10 penetrates through the back passivation layer 7 to form an electrical contact with the back passivation layer 7, and in some embodiments, the material of the first electrode 10 includes at least one conductive metal material such as silver, aluminum, copper, nickel, and the like. As an optional technical solution of the present application, an opening may be formed in the back passivation layer 7, so that the first electrode 10 is electrically contacted with the back passivation layer 7 after passing through the opening, thereby reducing a contact area between the metal electrode and the back passivation layer 7, further reducing contact resistance, and improving open-circuit voltage.
The front-surface doping layer 8 is positioned on the front surface 2 of the silicon wafer 1, and a second doping element of the front-surface doping layer 8 is opposite to a first conductive type dopant of the silicon wafer 1; in one possible embodiment, when the silicon wafer 1 is an N-type crystalline silicon wafer 1, the second doping element of the front-side doping layer 8 is boron; when the silicon wafer 1 is a P-type crystal silicon wafer 1, the second doping element of the front-side doping layer 8 is phosphorus.
The front passivation layer 9 is located on the front doped layer 8, and the front passivation layer 9 can play a role in passivating the front surface 2 of the silicon wafer 1, so that the composition of carriers at an interface is reduced, the transmission efficiency of the carriers is improved, and the photoelectric conversion efficiency of the cell is further improved. Optionally, the front passivation layer 9 includes a stacked structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer.
The second electrode 11, after penetrating the front passivation layer 9, forms an electrical contact with the front doped layer 8, and in some embodiments, the material of the second electrode 11 includes at least one conductive metal material such as silver, aluminum, copper, nickel, and the like.
Based on the cell provided by the above embodiment, between the tunneling oxide layer 5 and the silicon wafer 1, since the surface of the silicon wafer 1 after alkali polishing is sensitive to the environment and the oxide layer grows faster, the first oxide layer 4 may exist, and the existence of the first oxide layer 4 may affect the measurement of the thickness of the tunneling oxide layer 5.
Based on this, the present application provides a method for manufacturing a battery piece, after a tunneling oxide layer 5 with a suitable thickness is manufactured, a subsequent process is performed, specifically, referring to fig. 2, the method includes the following steps:
step S100: providing a textured N-type silicon wafer 1, doping the front surface 2 of the silicon wafer 1 to form a front surface doping layer 8, wherein the front surface doping layer 8 can be used as a part of the silicon wafer 1, namely, P-type doping elements are diffused into the front surface 2 of the original silicon wafer 1 through a high-temperature diffusion process to form the front surface doping layer 8. Optionally, the P-type doping element is boron, and the doping source is boron tribromide or boron trichloride;
step S101: the manufacturing of a polished surface is carried out on the back surface 3 of the silicon wafer 1, so that a flat texture shape is formed, the uniformity and compactness of the deposition of the subsequent tunneling oxide layer 5 are facilitated, the surface of the silicon wafer 1 after alkali polishing is sensitive to the environment, the oxide layer grows fast, the back surface 3 of the silicon wafer 1 reacts with oxygen in the air to generate a first oxide layer 4, the first oxide layer 4 has a certain thickness, the existence of the first oxide layer 4 is often ignored when the thickness of the tunneling oxide layer 5 is measured in the prior art, and the measurement of the subsequent tunneling oxide layer 5 is not accurate;
step S102: the thickness TH1 of the first oxide layer 4 is measured, in a possible implementation manner, the thickness data is measured by a laser ellipsometer, the laser ellipsometer irradiates a sample with light in a determined polarization state, and calculates optical characteristics (such as refractive index and film thickness) of the sample by measuring the polarization state of reflected light, and the structure of the laser ellipsometer and the method for measuring the thickness by using the laser ellipsometer can refer to the content in the prior art, which is not described herein again;
step S103: depositing a tunneling oxide layer 5 on the surface of the first oxide layer 4, wherein in the embodiment provided by the application, the tunneling oxide layer 5 is prepared by any one of a low-pressure chemical vapor deposition method, a high-temperature thermal oxidation method, a nitric acid oxidation method and an ozone oxidation method;
step S104: testing the total thickness TH2 of the tunneling oxide layer 5 and the first oxide layer 4, in a possible implementation manner, after the silicon wafer 1 is sent out of the diffusion furnace tube, plastic-packaging and winding are performed for a preset time to isolate air, so as to avoid interference of oxidation, improve detection accuracy, and the total thickness TH2 of the tunneling oxide layer 5 and the first oxide layer 4 is also measured by a laser ellipsometer, which is not described herein again;
step S105: calculating the thickness TH3= TH2-TH1 of the tunneling oxide layer 5, in order to improve the measurement precision and avoid air interference at two sides, a plurality of silicon wafers 1 are distributed in a quartz boat at intervals in the horizontal direction, one silicon wafer 1 positioned in the middle is selected to measure thickness data, and the left side and the right side of the silicon wafer 1 are both adjacent silicon wafers 1, so that the air flow interference is reduced;
step S106: in the step S105, if the thickness TH3 of the tunnel oxide layer 5 is less than 1.2nm or greater than 2.0nm, the steps S100 to S105 are executed again after the adjustment process is performed until the thickness TH3 of the tunnel oxide layer 5 is 1.2 to 2.0nm, in the embodiment provided by the present application, the thickness TH1 of the first oxide layer 4 is 0.4 to 0.6nm, the total thickness TH2 of the tunnel oxide layer 5 and the first oxide layer 4 is 1.7 to 2.4nm, the thickness TH3 of the tunnel oxide layer 5 is between 1.2 to 2.0nm, the thickness of the tunnel oxide layer 5 is too large, the tunneling effect of most carriers is affected, the carriers are difficult to transmit through the tunnel oxide layer 5, the photoelectric conversion efficiency of the battery is gradually reduced, and the thickness of the tunnel oxide layer 5 is too small, which is not favorable for the tunneling and passivation effects of the tunnel oxide layer 5;
step S107: depositing passivation film layers on the front surface 2 and the back surface 3 of the silicon wafer 1, respectively, in the embodiment provided by the present application, the passivation film layer on the front surface 2 includes a front passivation layer 9, and the passivation film layer on the back surface includes a back passivation layer 7 and a back doped layer 6, and the forming process thereof can refer to the content of the prior art and is not limited herein;
step S108: in the embodiment provided by the present application, the metal electrode on the front surface 2 is a first electrode 10, the first electrode 10 on the back surface 3 is a second electrode 11, and the methods for preparing the first electrode 10 and the second electrode 11 can refer to the contents of the prior art and are not limited herein.
In an embodiment provided by the present application, the step S103 further includes:
step S1031: ensuring that the furnace tube temperature of the diffusion furnace reaches a set value, and setting the temperature range to be 500-800 ℃;
step S1032: putting a silicon wafer 1 into a furnace tube;
step S1033: pumping the pressure to a bottom pressure, testing the leakage rate and ensuring the air tightness to be qualified;
step S1034: raising the temperature of the furnace tube to a target value of 550-650 ℃;
step S1035: stabilizing the temperature of each temperature zone of the furnace tube at a target value of 550-650 ℃;
step S1036: constant temperature high concentration oxidation, maintaining the first time, controlling the pressure at 700000-1000000mTorr, controlling the temperature at the first temperature, and maintaining the oxygen flow at the first flow, wherein the first time, the first temperature and the first flow are variable parameter values, the specific value is determined according to the result measured in step S105, if the thickness TH3 of the tunneling oxide layer 5 in step S105 is less than 1.2nm, the first time is increased, the first temperature is increased, and the first flow is increased; if the thickness TH3 of the tunneling oxide layer 5 is greater than 2.0nm in the step S105, the first time is reduced, the first temperature is reduced, and the first flow rate is reduced, wherein the value range of the first time is 100-1000S, the value range of the first temperature is 550-650 ℃, the value range of the first flow rate is 10000-50000sccm, and the adjustment priority is as follows in the range of the first time: the first temperature > the first flow > the first time, and the first temperature is preferably adjusted so as to better control the thickness of the tunneling oxide layer 5;
step S1037: pumping away the oxygen remaining in the step S1066;
step S1038: cooling the furnace tube to room temperature;
step S1039: in the embodiment provided by the present application, the silicon wafer 1 is sent out of the diffusion furnace tube at a preset temperature, in a feasible embodiment, the preset temperature is 20 ℃ to 25 ℃.
When the thickness TH3 of the tunneling oxide layer 5 is less than 1.2nm, the N-type dopant easily penetrates through the tunneling oxide layer 5 when the back doped layer 6 is formed, the tunneling oxide layer 5 cannot play a passivation role, and when the thickness TH3 of the tunneling oxide layer 5 is less than 1.2nm and less than 2.0nm, the tunneling of carriers is mainly used for transmission; when the thickness TH3 of the tunneling oxide layer 5 is more than 2.0nm, the carriers are mainly transmitted through pinholes (pinholes) in the tunneling oxide layer 5, although the pinhole density is high, the transmission is beneficial, but the pinhole density is not beneficial to passivation, and the carrier transmission is limited; the thickness TH3 of the tunneling oxide layer 5 is set to be less than 1.2nm and greater than 2.0nm, namely, the tunneling effect and the passivation effect are balanced, and the efficiency advantage is maximized.
Claims (10)
1. The preparation method of the battery piece is characterized by comprising the following steps:
step S100: providing a textured N-type silicon wafer, and doping the front surface of the silicon wafer to form a front doped layer;
step S101: manufacturing a polished surface on the back surface of a silicon wafer, and reacting the back surface of the silicon wafer with oxygen in the air to generate a first oxide layer after alkali polishing;
step S102: testing the thickness TH1 of the first oxide layer;
step S103: depositing a tunneling oxide layer on the surface of the first oxide layer;
step S104: testing the total thickness TH2 of the tunneling oxide layer and the first oxide layer;
step S105: calculating the thickness TH3= TH2-TH1 of the tunneling oxide layer;
step S106: in the step S105, if the thickness TH3 of the tunnel oxide layer is smaller than 1.2nm or larger than 2.0nm, the steps S100 to S105 are executed again after the adjustment process until the thickness TH3 of the tunnel oxide layer is 1.2 to 2.0nm.
Step S107: respectively depositing a passivation film layer on the front surface and the back surface of the silicon wafer;
step S108: and respectively preparing metal electrodes on the front surface and the back surface of the silicon wafer.
2. The method for preparing the battery piece according to claim 1, wherein the step S103 further comprises:
step S1031: ensuring that the temperature of the furnace tube of the diffusion furnace reaches a set value, and setting the temperature range to be 500-800 ℃;
step S1032: putting a silicon wafer into a furnace tube;
step S1033: pumping the pressure to a bottom pressure, testing the leakage rate and ensuring the air tightness to be qualified;
step S1034: raising the temperature of the furnace tube to a target value of 550-650 ℃;
step S1035: stabilizing the temperature of each temperature zone of the furnace tube at a target value of 550-650 ℃;
step S1036: constant-temperature high-concentration oxidation, maintaining for the first time, controlling the pressure at 700000-1000000mTorr, controlling the temperature at the first temperature, and maintaining the oxygen flow at the first flow;
step S1037: pumping away the oxygen remaining in the step S1066;
step S1038: cooling the furnace tube to room temperature;
step S1039: filling the tube with nitrogen, reducing the pressure difference between the inside and the outside of the tube, and taking out the sample piece to be tested.
3. The method for preparing the battery piece according to claim 2, wherein the adjusting process in the step S106 is specifically as follows:
if the tunneling oxide layer thickness TH3 is smaller than 1.2nm in step S105, increasing the first time, increasing the first temperature, and increasing the first flow rate;
if the tunneling oxide layer thickness TH3 is greater than 2.0nm in step S105, the first time is decreased, the first temperature is decreased, and the first flow rate is decreased.
4. The method for producing a battery sheet according to claim 1, characterized in that: in step S103, the tunneling oxide layer is deposited in a diffusion furnace tube, and the silicon wafer is sent out of the diffusion furnace tube at a preset temperature.
5. The method for producing a battery piece according to claim 4, characterized in that: the preset temperature is 20-25 ℃.
6. The method for producing a battery piece according to claim 4, characterized in that: in step S104, after the silicon wafer is sent out of the diffusion furnace tube, plastic packaging and winding are performed for a preset time to isolate air.
7. The method for producing a battery piece according to claim 6, characterized in that: the preset time is 20min-30min.
8. The method for producing a battery sheet according to claim 1, characterized in that: in the step S102 and the step S104, a plurality of silicon wafers are distributed in the quartz boat at intervals in the horizontal direction, and one silicon wafer located in the middle is selected to measure thickness data.
9. The method for producing a battery sheet according to claim 1, characterized in that: in the steps S102 and S104, the thickness data is measured by using a laser ellipsometer.
10. The method for producing a battery piece according to claim 1, characterized in that: the thickness TH1 of the first oxide layer is 0.4-0.6nm, and the total thickness TH2 of the tunneling oxide layer and the first oxide layer is 1.7-2.4nm.
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| CN202211430229.XA CN115831789A (en) | 2022-11-15 | 2022-11-15 | Preparation method of battery piece |
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| CN202211430229.XA CN115831789A (en) | 2022-11-15 | 2022-11-15 | Preparation method of battery piece |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117117044A (en) * | 2023-10-24 | 2023-11-24 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and primary annealing preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117117044A (en) * | 2023-10-24 | 2023-11-24 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and primary annealing preparation method thereof |
| CN117117044B (en) * | 2023-10-24 | 2024-01-09 | 金阳(泉州)新能源科技有限公司 | Combined passivation back contact battery and primary annealing preparation method thereof |
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