CN115831722A - Method for manufacturing semiconductor structure - Google Patents
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- CN115831722A CN115831722A CN202310023923.8A CN202310023923A CN115831722A CN 115831722 A CN115831722 A CN 115831722A CN 202310023923 A CN202310023923 A CN 202310023923A CN 115831722 A CN115831722 A CN 115831722A
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Abstract
The invention relates to a preparation method of a semiconductor structure. The method comprises the following steps: providing a substrate; forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions which are distributed at intervals in the substrate; a side groove is arranged between the top edge of the shallow trench isolation structure and the active region; forming a first dielectric layer on the upper surface of the active region; forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove; forming a second dielectric layer on the upper surface of the hard mask layer; etching the second dielectric layer and the hard mask layer to obtain a graphical dielectric layer and a graphical hard mask layer, wherein openings are formed in the graphical dielectric layer and the graphical hard mask layer, and part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side groove are exposed out of the openings; the exposed side groove is provided with a residual hard mask layer; and removing the residual hard mask layer. The method can save cost.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure.
Background
With the development of semiconductor technology, in the conventional technology, the Hard Mask layer (HM) is usually removed before the gate dielectric layer is grown, however, the Hard Mask layer is prone to have residual (residual) small particles in the edge groove due to the problem of step height difference (step height) of the active region and the edge groove (divot) phenomenon easily occurring in the formation process of the shallow trench isolation structure. In the subsequent wet removal process, the dielectric layer is removed, so that the small-particle hard mask layer remained in the edge groove falls into the cleaning groove, and the cleaning solution in the cleaning groove can be filled with a large amount of small-particle residues of the hard mask layer. The cleaning solution in the cleaning tank usually needs to be reused, so that small particle residues can randomly adhere to the surface of the wafer to be cleaned subsequently, and if the cleaning solution in the cleaning tank is frequently replaced, the problem of high cost exists.
Disclosure of Invention
In view of the above, it is necessary to provide a method for manufacturing a semiconductor structure, which solves the problem of high cost of frequent cleaning solution replacement in the conventional technology.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate; a side groove is arranged between the top edge of the shallow trench isolation structure and the active region;
forming a first dielectric layer on the upper surface of the active region;
forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove;
forming a second dielectric layer on the upper surface of the hard mask layer;
etching the second dielectric layer and the hard mask layer to obtain a graphical dielectric layer and a graphical hard mask layer, wherein openings are formed in the graphical dielectric layer and the graphical hard mask layer, and part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side groove are exposed out of the openings; the exposed side groove is internally provided with a residual hard mask layer;
and removing the residual hard mask layer.
In one embodiment, the method further comprises:
removing the graphical dielectric layer and the exposed first dielectric layer to expose part of the active region;
and forming a gate dielectric layer on the exposed upper surface of the active region.
In one embodiment, after forming the gate dielectric layer on the exposed upper surface of the active region, the method further includes:
forming a grid structure on the upper surface of the grid dielectric layer;
and forming a source region and a drain region in the active region on two opposite sides of the gate structure.
In one embodiment, the material of the first dielectric layer, the material of the second dielectric layer, and the material of the shallow trench isolation structure are the same.
In one embodiment, the first dielectric layer includes a silicon oxide layer, the second dielectric layer includes a silicon oxide layer, the hard mask layer includes a silicon nitride layer, and the shallow trench isolation structure includes a silicon oxide isolation structure.
In one embodiment, the removing the residual hard mask layer includes:
and taking the graphical dielectric layer as a protective layer of the graphical hard mask layer, and removing the residual hard mask layer by utilizing a first wet cleaning process.
In one embodiment, the removing the patterned dielectric layer and the exposed first dielectric layer includes:
and simultaneously removing the patterned dielectric layer and the exposed first dielectric layer by utilizing a second wet cleaning process.
In one embodiment, the cleaning solution of the first wet cleaning process comprises phosphoric acid; the cleaning liquid of the second wet cleaning process comprises hydrofluoric acid diluent.
In one embodiment, the second dielectric layer and the hard mask layer are etched by a dry etching process.
In one embodiment, the etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer includes:
forming a photoresist layer on the upper surface of the second dielectric layer;
patterning the photoresist layer to obtain a patterned photoresist layer;
and etching the second dielectric layer and the hard mask layer based on the graphical photoresist layer to obtain the graphical dielectric layer and the graphical hard mask layer.
In the preparation method of the semiconductor structure, the shallow trench isolation structure is formed in the substrate and isolates a plurality of active regions arranged at intervals in the substrate; a side groove is arranged between the top edge of the shallow trench isolation structure and the active region; forming a first dielectric layer on the upper surface of the active region; forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove; forming a second dielectric layer on the upper surface of the hard mask layer; etching the second dielectric layer and the hard mask layer to obtain a graphical dielectric layer and a graphical hard mask layer, wherein openings are formed in the graphical dielectric layer and the graphical hard mask layer, and part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side groove are exposed out of the openings; the exposed side groove is provided with a residual hard mask layer; therefore, the exposed residual hard mask layer in the side groove can be removed, so that the hard mask layer with small particles is difficult to remain in the cleaning groove, the cleaning liquid in the cleaning groove does not need to be frequently replaced, and the cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating a structure formed in a conventional method for removing a hard mask layer according to an embodiment;
FIG. 2 is a schematic diagram illustrating a structure formed in a conventional method for removing a hard mask layer according to an embodiment;
FIG. 3 is a schematic diagram illustrating a structure formed in a conventional method for removing a hard mask layer according to an embodiment;
FIG. 4 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to one embodiment;
fig. 5 is a schematic cross-sectional view illustrating the structure obtained in step S102 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 6 is a schematic cross-sectional view of the structure obtained in step S103 of the method for fabricating a semiconductor structure provided in one embodiment;
fig. 7 is a schematic cross-sectional view illustrating a structure obtained in step S104 of the method for fabricating a semiconductor structure according to an embodiment;
fig. 8 is a schematic cross-sectional view of the structure obtained in step S105 of the method for fabricating a semiconductor structure provided in one embodiment;
fig. 9 is a schematic cross-sectional view illustrating a structure obtained in step S106 of the method for fabricating a semiconductor structure provided in an embodiment;
fig. 10 is a schematic cross-sectional view of the structure obtained in step S107 of the method for fabricating a semiconductor structure provided in one embodiment;
FIG. 11 is a schematic flow chart diagram illustrating a method for fabricating a semiconductor structure, in accordance with one embodiment;
fig. 12 is a schematic cross-sectional view of a structure obtained in step S1101 of a method for manufacturing a semiconductor structure provided in an embodiment;
fig. 13 is a schematic cross-sectional view illustrating a structure obtained in step S1102 in the method for fabricating a semiconductor structure according to an embodiment;
FIG. 14 is a schematic flow chart diagram of a method for fabricating a semiconductor structure, as provided in one embodiment;
fig. 15 is a schematic cross-sectional view of the structure obtained in step S1402 in the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 16 is a flowchart illustrating a step S106 of a method for fabricating a semiconductor structure according to an embodiment;
fig. 17 is a schematic cross-sectional view of the structure obtained in step S1061 of the method for fabricating a semiconductor structure according to an embodiment;
fig. 18 is a schematic cross-sectional view of the structure obtained in step S1062 of the method for fabricating a semiconductor structure according to an embodiment;
fig. 19 is a schematic cross-sectional view of the structure obtained in step S1063 of the method for manufacturing a semiconductor structure provided in one embodiment.
Description of reference numerals: 10-substrate, 101-shallow trench isolation structure, 102-active region, 1011-side groove, 20-first dielectric layer, 30-hard mask layer, 301-patterned hard mask layer, 302-residual hard mask layer, 40-second dielectric layer, 401-patterned dielectric layer, 402-opening, 50-gate dielectric layer, 60-gate structure, 70-photoresist layer, 701-patterned photoresist layer and 80-dielectric layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the conventional technology, referring to fig. 1 to 3, the step of removing the hard mask layer is to first form a patterned photoresist layer 701 on the upper surface of the hard mask layer 30, referring to fig. 1, then etch the hard mask layer based on the patterned photoresist layer 701 to form the patterned hard mask layer 301 and expose a portion of the dielectric layer 80, and remove the patterned photoresist layer 701 after the etching is finished. At this time, since the shallow trench isolation structure 101 is easy to form the side groove (divot) 1011 during the formation process, the side groove 1011 may have the residual hard mask layer 302 therein during the formation process of the patterned hard mask layer 301, as shown in fig. 2. Then, the structure obtained in fig. 2 is placed in a cleaning tank, and is cleaned by using a specific cleaning solution to remove the exposed dielectric layer 80, and in the cleaning process, as shown in fig. 3, since the cleaning solution can only remove the dielectric layer 80 but cannot remove the hard mask layer 30, the residual hard mask layer 302 will fall into the cleaning tank, and as the process proceeds, the cleaning solution in the cleaning tank will fill a large amount of the residual hard mask layer 302. The cleaning solution in the cleaning tank generally needs to be reused, so that the residual hard mask layer 302 randomly adheres to the surface of the wafer to be cleaned subsequently, and if the cleaning solution in the cleaning tank is frequently replaced, the cost is high.
Referring to fig. 4, the present application provides a method for fabricating a semiconductor structure, including:
s101: providing a substrate;
s102: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate; a side groove is arranged between the top edge of the shallow trench isolation structure and the active region;
s103: forming a first dielectric layer on the upper surface of the active region;
s104: forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove;
s105: forming a second dielectric layer on the upper surface of the hard mask layer;
s106: etching the second dielectric layer and the hard mask layer to obtain a graphical dielectric layer and a graphical hard mask layer, wherein openings are formed in the graphical dielectric layer and the graphical hard mask layer, and part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side groove are exposed out of the openings; the exposed side groove is provided with a residual hard mask layer;
s107: and removing the residual hard mask layer.
In step S101, referring to step S101 in fig. 4 and fig. 5, a substrate 10 is provided.
The substrate 10 may include, but is not limited to, at least one of a silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate, and specifically, the substrate 10 may be any one of a silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate, or may be a composite substrate in which two or more of them are combined, and the embodiment is not limited herein.
In step S102, please refer to step S102 in fig. 4 and fig. 5, a shallow trench isolation structure 101 is formed in the substrate 10, and the shallow trench isolation structure 101 isolates a plurality of active regions 102 arranged at intervals in the substrate 10; an edge groove 1011 is formed between the top edge of the shallow trench isolation structure 101 and the active region 102.
The insulating dielectric material filled in the Shallow Trench Isolation structure 101 (STI) may be one or a combination of silicon dioxide, fluorosilicone glass, undoped Silicate Glass (USG), or tetraethyl orthosilicate.
In step S103, referring to step S103 in fig. 4 and fig. 6, a first dielectric layer 20 is formed on the upper surface of the active region 102.
In step S104, please refer to step S104 in fig. 4 and fig. 7, a hard mask layer 30 is formed on the upper surface of the first dielectric layer 20 and the upper surface of the shallow trench isolation structure 101; the hard mask layer 30 fills the edge trenches 1011.
The Hard Mask layer (HM) 30 may be titanium nitride (TiN), silicon nitride (SiN), or silicon dioxide (SiO) 2 ) One or more of the above.
For the convenience of describing the present embodiment, the shallow trench isolation structure 101 shown in fig. 4 is higher than the first dielectric layer 20, so that the hard mask layer on the shallow trench isolation structure 101 and the hard mask layer on the first dielectric layer 20 have a certain height difference. Of course, in an actual application scenario, the height of the hard mask layer on the shallow trench isolation structure 101 may be equal to the height of the hard mask layer on the first dielectric layer 20, or the height of the hard mask layer on the shallow trench isolation structure 101 may be lower than the height of the hard mask layer on the first dielectric layer 20, which is not limited herein.
In step S105, referring to step S105 of fig. 4 and fig. 8, a second dielectric layer 40 is formed on the upper surface of the hard mask layer 30.
Optionally, the first dielectric layer 20 and the second dielectric layer 40 may be prepared by the same process steps and the same process machine; further, the thicknesses of the first dielectric layer 20 and the second dielectric layer 40 may be the same.
In step S106, please refer to step S106 in fig. 4 and fig. 9, the second dielectric layer 40 and the hard mask layer 30 are etched to obtain the patterned dielectric layer 401 and the patterned hard mask layer 301, an opening 402 is formed in the patterned dielectric layer 401 and the patterned hard mask layer 301, and the opening 402 exposes a portion of the upper surface of the first dielectric layer 20, a portion of the shallow trench isolation structure 101, and a portion of the side groove 1011; the exposed edge trenches 1011 have a residual hard mask layer 302 therein.
It is to be understood that the shape of the opening 402 and the exposed area of the opening 402 shown in fig. 9 are only for convenience of describing the embodiment, and in an actual application environment, the opening 402 may have other shapes or expose other different areas, and the embodiment is not limited herein.
In step S107, please refer to step S107 in fig. 4 and fig. 10, the residual hard mask layer 302 is removed.
Because the residual hard mask layer in the edge groove 1011 is exposed, and the patterned dielectric layer 401 covers the patterned hard mask layer 301 at this time, due to the protection effect of the patterned dielectric layer 401, the residual hard mask layer 302 can be removed while the patterned hard mask layer is remained, so that the residual hard mask layer 302 in the exposed edge groove can be completely removed without damaging the structure of the patterned hard mask layer.
In the method for manufacturing the semiconductor structure of the embodiment, the shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate; a side groove is arranged between the top edge of the shallow trench isolation structure and the active region; forming a first dielectric layer on the upper surface of the active region; forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove; forming a second dielectric layer on the upper surface of the hard mask layer; etching the second dielectric layer and the hard mask layer to obtain a graphical dielectric layer and a graphical hard mask layer, wherein openings are formed in the graphical dielectric layer and the graphical hard mask layer, and part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side groove are exposed out of the openings; the exposed side groove is provided with a residual hard mask layer; therefore, the exposed residual hard mask layer in the side groove can be removed, so that the residual hard mask layer is difficult to remain in the cleaning groove in the subsequent process steps, the cleaning liquid in the cleaning groove does not need to be frequently replaced, and the cost can be reduced.
Referring to fig. 11, in an embodiment, the method for fabricating a semiconductor structure of the present invention may further include the following steps:
s1101: removing the graphical dielectric layer and the exposed first dielectric layer to expose part of the active region;
s1102: and forming a gate dielectric layer on the exposed upper surface of the active region.
In step S1101, referring to step S1101 in fig. 11 and fig. 12, the patterned dielectric layer 401 and the exposed first dielectric layer 20 are removed to expose a portion of the active region 102.
In step S1102, referring to step S1102 of fig. 11 and fig. 13, a gate dielectric layer 50 is formed on the exposed upper surface of the active region 102.
The Gate dielectric layer 50 may include a Gate Oxide (GOX). Optionally, the forming process of the gate oxide layer may be a furnace tube process or other oxidation processes, and this embodiment is not limited herein.
Referring to fig. 14, in an embodiment, after the step S1002, the following steps may be further included:
s1401: forming a gate structure 60 on the upper surface of the gate dielectric layer 50;
s1402: source and drain regions are formed in the active region 102 on opposite sides of the gate structure 60.
In step S1401, referring to step S1401 of fig. 14 and fig. 15, a gate structure 60 is formed on an upper surface of the gate dielectric layer 50.
In step S1402, referring to step S1402 in fig. 14 and fig. 15, a source region (not shown) and a drain region (not shown) are formed in the active region 102 on opposite sides of the gate structure 60.
In one embodiment, the material of the first dielectric layer 20, the material of the second dielectric layer 40, and the material of the shallow trench isolation structure 101 are the same.
Based on the above embodiments, in one embodiment, the first dielectric layer 20 includes a silicon oxide layer, the second dielectric layer 40 includes a silicon oxide layer, the hard mask layer 30 includes a silicon nitride layer, and the shallow trench isolation structure 101 includes a silicon oxide isolation structure.
On the basis of the foregoing embodiment, in an embodiment, the foregoing step S107 includes: the patterned dielectric layer 401 is used as a protective layer of the patterned hard mask layer 301, and the residual hard mask layer 302 is removed by a first wet cleaning process.
The wet cleaning is a cleaning mode requiring introduction of a cleaning solution, the wet cleaning may include steam cleaning, solution soaking cleaning, rotary spraying cleaning and the like, the cleaning solution for wet cleaning may include deionized water, an acid cleaning solution and the like, and when the wet cleaning process is performed, the corresponding cleaning solution may be selected according to a material to be removed to perform the wet cleaning. For example, when it is desired to remove silicon oxide, an acidic cleaning solution such as phosphoric acid or the like is generally used; when silicon nitride removal is desired, a Hydrofluoric Acid (DHF) diluent or the like is generally used. Different cleaning solutions can not be mixed to use usually, need use different washing tanks to preserve, and in order to practice thrift the cost, the cleaning solution in the wet cleaning usually needs to use repeatedly many times, if there is the residue of small granule in the cleaning solution, then these residues float on other wafers at random very easily in the washing of next time and cause the pollution to the wafer, lead to having great influence to the follow-up production technology step of wafer, consequently keep the pure very important of cleaning solution.
On the basis of the foregoing embodiment, in an embodiment, the foregoing step S1101 includes: the patterned dielectric layer 401 and the exposed first dielectric layer 20 are simultaneously removed by a second wet cleaning process.
It should be noted that, since the material of the first dielectric layer 20 is the same as the material of the second dielectric layer 40, the material of the patterned dielectric layer 401 is also the same as the material of the exposed first dielectric layer 20, so that the patterned dielectric layer 401 and the exposed first dielectric layer 20 can be removed simultaneously by using the second wet cleaning process; in addition, although the material of the first dielectric layer 20 is the same as the material of the shallow trench isolation structure 101, when the second wet cleaning process is performed, the material filled in the shallow trench isolation structure 101 may be slightly lost, but in an actual process, the thickness of the first dielectric layer 20 is relatively thin, and the second wet cleaning process is not performed for a long time, so the loss of the shallow trench isolation structure 101 at this time may be almost negligible, and the performance of a subsequently formed semiconductor device may not be affected.
On the basis of the above embodiment, in one embodiment, the cleaning liquid of the first wet cleaning process includes phosphoric acid; the cleaning liquid of the second wet cleaning process comprises hydrofluoric acid diluent.
In one embodiment, in the step S106, a dry etching process is used to etch the second dielectric layer 40 and the hard mask layer 30.
When the second dielectric layer 40 is etched, the hard mask layer 30 is used as an etching stop layer of the second dielectric layer 40 for etching; after the etching of the second dielectric layer 40 is completed, when the hard mask layer 30 is etched, the first dielectric layer 20 is etched as an etching stop layer of the hard mask layer 30. Both etching processes can be carried out in the same dry etching machine, and can be realized by only changing main etching gas (main gas).
Referring to fig. 16, in an embodiment, the step S106 includes:
s1061: forming a photoresist layer on the upper surface of the second dielectric layer;
s1062: patterning the photoresist layer to obtain a patterned photoresist layer;
s1063: and etching the second dielectric layer and the hard mask layer based on the graphical photoresist layer to obtain the graphical dielectric layer and the graphical hard mask layer.
In step S1061, referring to step S1061 in fig. 16 and fig. 17, a photoresist layer 70 is formed on the upper surface of the second dielectric layer 40.
In step S1062, referring to step S1062 in fig. 16 and fig. 18, the photoresist layer 70 is patterned to obtain a patterned photoresist layer 701.
In step S1063, referring to step S1063 of fig. 16 and fig. 19, the second dielectric layer 40 and the hard mask layer 30 are etched based on the patterned photoresist layer 701 to obtain the patterned dielectric layer 401 and the patterned hard mask layer 301.
In one embodiment, after the step S1063, the following steps may be further included: the patterned photoresist layer 701 is removed to form the structure obtained in step S106.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active regions which are distributed at intervals in the substrate; a side groove is arranged between the top edge of the shallow trench isolation structure and the active region;
forming a first dielectric layer on the upper surface of the active region;
forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove;
forming a second dielectric layer on the upper surface of the hard mask layer;
etching the second dielectric layer and the hard mask layer to obtain a graphical dielectric layer and a graphical hard mask layer, wherein openings are formed in the graphical dielectric layer and the graphical hard mask layer, and part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side groove are exposed out of the openings; the exposed side groove is internally provided with a residual hard mask layer;
and removing the residual hard mask layer.
2. The method of claim 1, further comprising:
removing the graphical dielectric layer and the exposed first dielectric layer to expose part of the active region;
and forming a gate dielectric layer on the exposed upper surface of the active region.
3. The method of claim 2, wherein after forming a gate dielectric layer on the exposed upper surface of the active region, the method further comprises:
forming a grid structure on the upper surface of the grid dielectric layer;
and forming a source region and a drain region in the active region on two opposite sides of the gate structure.
4. The method of claim 2, wherein the material of the first dielectric layer, the material of the second dielectric layer, and the material of the shallow trench isolation structure are the same.
5. The method of claim 4, wherein the first dielectric layer comprises a silicon oxide layer, the second dielectric layer comprises a silicon oxide layer, the hard mask layer comprises a silicon nitride layer, and the shallow trench isolation structure comprises a silicon oxide isolation structure.
6. The method of claim 2, wherein said removing the residual hardmask layer comprises:
and taking the graphical dielectric layer as a protective layer of the graphical hard mask layer, and removing the residual hard mask layer by utilizing a first wet cleaning process.
7. The method of claim 6, wherein the removing the patterned dielectric layer and the exposed first dielectric layer comprises:
and simultaneously removing the patterned dielectric layer and the exposed first dielectric layer by utilizing a second wet cleaning process.
8. The method for fabricating a semiconductor structure according to claim 7, wherein the cleaning solution of the first wet cleaning process comprises phosphoric acid; the cleaning liquid of the second wet cleaning process comprises hydrofluoric acid diluent.
9. The method of claim 1, wherein the second dielectric layer and the hard mask layer are etched by a dry etching process.
10. The method of claim 1, wherein the etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer comprises:
forming a photoresist layer on the upper surface of the second dielectric layer;
patterning the photoresist layer to obtain a patterned photoresist layer;
and etching the second dielectric layer and the hard mask layer based on the graphical photoresist layer to obtain the graphical dielectric layer and the graphical hard mask layer.
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| RU2252768C1 (en) * | 2004-01-05 | 2005-05-27 | Чаков Владимир Владимирович | Method for production of peloid water extract |
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