CN115810609A - Fuse trimming structure, preparation method thereof and integrated circuit - Google Patents
Fuse trimming structure, preparation method thereof and integrated circuit Download PDFInfo
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Abstract
The invention discloses a fuse trimming structure, a preparation method thereof and an integrated circuit, and relates to the technical field of trimming of integrated circuit chips. The fuse trimming structure comprises an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the second insulating layer towards the first insulating layer. The fuse trimming structure can solve the problem that the first insulating layer is easily damaged when the fuse is fused, thereby avoiding the fuse trimming structure from generating leakage current and further improving the reliability of an IC.
Description
Technical Field
The invention relates to the technical field of trimming of integrated circuit chips, in particular to a fuse trimming structure, a preparation method thereof and an integrated circuit.
Background
With the increasing requirements of high performance indexes of integrated circuits, the chip design is subject to increasingly obvious high-precision requirements, and particularly, for the design of high-precision and high-speed digital-to-analog converters, analog-to-digital converters, reference source circuits and the like, because of unavoidable factors such as process errors, the capacitance and resistance values of chips produced by a process factory have certain process errors, and the errors can directly influence the performance indexes of the circuits. In order to solve the problem of the process errors, before the chip is normally used, a trimming technology is needed to correct the chip, so that the circuit parameters are more accurate and the consistency is better.
Fuse Trimming (Fuse Trimming) is a method of changing the state of a circuit by applying a voltage to blow a connection (generally a Fuse) in the circuit when a large current passes through the connection. At present, the fuse trimming technique is widely applied to integrated circuits, and is often used for setting parameters such as high circuit precision, frequency change, resistance adjustment and the like before leaving a factory so as to achieve the purposes of changing circuit characteristics and improving production yield. A conventional fuse trimming structure generally utilizes a voltage source (or a current source) to blow a fuse, so as to change a circuit state to achieve the purpose of trimming. Since the fusing current cannot be precisely controlled due to the fluctuation of the manufacturing process, a larger fusing current is generally used to ensure that the fuse can be completely fused. However, the application of a large current ensures that the fuse is completely blown, and also has an inevitable negative effect that the application of a large current causes the insulating layer below the fuse to be damaged. And the dielectric layer is damaged, which will cause leakage current to occur from the VCC under the substrate through the substrate and the dielectric layer and between the two conductive terminals connected to the fuse pad. On one hand, the generation of leakage current will adversely affect the trimming accuracy; on the other hand, after the fuse trimming structure generating the leakage current is used for a long time, the leakage current is increased, and even the IC fails when the leakage current is serious.
Disclosure of Invention
The invention provides a fuse trimming structure, a preparation method thereof and an integrated circuit, which can solve the problem that a first insulating layer is easily damaged when a fuse is fused, thereby avoiding the fuse trimming structure from generating leakage current and further improving the reliability of an IC.
In order to solve the technical problems, the invention adopts the following technical scheme:
the invention provides a fuse trimming structure which comprises an N-type substrate, a first insulating layer, a fuse layer and a second insulating layer, wherein the first insulating layer is positioned on the N-type substrate; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the second insulating layer towards the first insulating layer. The fuse trimming structure can solve the problem that the first insulating layer is easily damaged when the fuse is fused, thereby avoiding the fuse trimming structure from generating leakage current and further improving the reliability of an IC.
In one possible embodiment, an orthographic projection width of the P-type region on the N-type substrate is greater than a first width, and the first width is a distance between orthographic projections of the first bonding pad and the second bonding pad on the N-type substrate.
In one possible embodiment, the orthographic projection of the P-type region on the N-type substrate coincides with the N-type substrate.
In one possible embodiment, the fuse layer is polysilicon. Compared with the existing metal fuse, the fuse wire adopting the polysilicon fuse wire can be fused under the action of relatively low fusing current, so that the fuse wire trimming structure adopting the polysilicon fuse wire is more suitable for being arranged at the internal position of an integrated circuit chip.
In one possible embodiment, the fuse layer includes a first portion and two second portions located at opposite ends of the first portion, the two second portions corresponding to the first pad and the second pad, respectively; wherein the thickness of the first portion is less than the thickness of the second portion. The fuse wire layer is arranged to be thin in the middle and thick on two sides, so that on one hand, the fuse wire is easier to fuse; on the other hand, the problem that the first insulating film is damaged by a large blowing current can be improved to some extent.
In one possible embodiment, the first insulating layer includes an insulating layer main body and two insulating layer end portions located at two opposite ends of the insulating layer main body, and the two insulating layer end portions correspond to the first pad and the second pad, respectively; wherein, the thickness of the two insulating layer end portions is larger than the thickness of the insulating layer main body. Thus, the possibility that the first insulating film is broken can be further reduced.
The invention also provides a preparation method of the fuse trimming structure, which comprises the following steps: providing an N-type substrate; forming a P-type region on an N-type substrate, wherein the P-type region and the N-type substrate form a PN junction together; forming a first insulating layer on the P-type region, wherein the first insulating layer covers the P-type region; forming a fuse layer on the first insulating layer, wherein the fuse layer is provided with a first bonding pad and a second bonding pad which are spaced, and the fuse layer and the N-type substrate are electrically isolated by the first insulating layer; forming a second insulating layer on the fuse layer to cover the fuse layer; and opening a first window exposing the first bonding pad and a second window exposing the second bonding pad on the second insulating layer through a photoetching process. The fuse trimming structure prepared by the preparation method of the fuse trimming structure can solve the problem that the first insulating layer is easily damaged when the fuse is fused, so that the fuse trimming structure can be prevented from generating leakage current, and the reliability of an IC (integrated circuit) can be improved.
In one possible embodiment, forming a P-type region on an N-type substrate, the P-type region and the N-type substrate together forming a PN junction, includes: and forming a P-type region in the N-type substrate by an ion implantation process, wherein the upper surface of the P-type region is flush with the upper surface of the N-type substrate, and the P-type region and the N-type substrate together form a PN junction.
In one possible embodiment, forming a P-type region on an N-type substrate, the P-type region and the N-type substrate together forming a PN junction, includes: and forming a P-type area on the N-type substrate through a deposition process or a sputtering process, wherein the P-type area covers the upper surface of the N-type substrate, and the P-type area and the N-type substrate jointly form a PN junction.
The invention also provides an integrated circuit which comprises the fuse trimming structure. The integrated circuit adopting the fuse trimming structure can avoid the influence on the trimming precision caused by the leakage current generated by the fuse trimming structure, and can improve the reliability of an IC.
The fuse trimming structure provided by the invention has the beneficial effects that:
the fuse trimming structure comprises an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the second insulating layer towards the first insulating layer. The P-type region is formed between the first insulating layer of the fuse trimming structure and the N-type substrate, so that the N-type substrate and the P-type region jointly form a PN junction which is conducted towards the first insulating layer along the second insulating layer. Thus, even if the first insulating layer under the fuse layer is damaged due to a large blowing current applied to the fuse layer for effectively blowing the fuse layer, leakage current generated in a direction from the VCC of the N-type substrate toward the PAD or the GND is prevented due to the PN junction. By adopting the fuse trimming structure provided by the application, the leakage current can be effectively reduced, and the reliability of an IC (integrated circuit) can be improved.
Drawings
The invention is further described with reference to the accompanying drawings:
fig. 1 is a schematic view illustrating a trimming principle provided by a fuse trimming structure according to the present application;
fig. 2 is a schematic structural diagram of a fuse trimming structure according to the present application;
fig. 3 is a second schematic structural diagram of a fuse trimming structure provided in the present application;
FIG. 4 is a schematic diagram illustrating a fuse layer of the fuse trimming structure of the present application being blown;
fig. 5 is a schematic flow chart of a manufacturing method of the fuse trimming structure provided in the present application.
Reference numbers: a 10-N type substrate; 20-a first insulating layer; 30-a fuse layer; 40-a second insulating layer; 41-a first window; 42-a second window; 51-a first pad; 52-second bonding pad; 60-P type region.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the chip manufacturing process, under the influence of factors such as process deviation, circuit mismatch and different chip production batches, the parameters of the produced chip and the expected value of the design simulation have great deviation, which brings great difficulty to the design of the analog circuit with higher requirement on the parameters. Therefore, when a designer designs a circuit, a trimming circuit is added to the chip. After the chip is manufactured by the process line, the chip is firstly required to be tested, parameters which do not meet the circuit requirements are subjected to one-time permanent programming by using the trimming circuit, and the parameter adjustment of the circuit is completed, so that the circuit parameters are closer to preset values, and the design requirements are met.
The trimming principle of the fuse trimming structure provided in the present application can be illustrated by the following simple examples. Assuming a resistor network as shown in fig. 1 exists inside the chip, the designer requires to obtain a precise resistor, and the actual resistor may be larger or smaller. The fuse acts as a switch, and the state of the switch is changed by selectively blowing or not blowing each fuse, thereby changing each resistance (R respectively) in the circuit 1 、R 2 And R 3 ) So that the resulting total resistance (resistance and R in the integrated circuit) is AB ) The accurate resistance meeting the design requirement is achieved. Of course, the adjustment of the resistance value by the fuse trimming technique is only an example given in the present application, and the fuse trimming structure is not limited to trimming the resistance value of the integrated circuit, and may also trim the current, or even replace a defective component or supplement a replacement component by adding the fuse trimming structure in the integrated circuit.
In the existing fuse trimming technology, in order to ensure that the fuse can be effectively blown and reduce the failure rate of fuse cutting, a larger blowing voltage is generally required to be applied to the fuse. However, when the blowing voltage is increased to increase the blowing current introduced into the fuse, the insulating layer under the fuse may be damaged. The insulating layer below the fuse is damaged, so that on one hand, the invasion of substances such as moisture and the like becomes more obvious (the substances such as moisture and the like start to invade from the side wall of the damaged insulating layer and further extend inwards); on the other hand, after the insulating layer under the fuse is damaged, the VCC under the substrate will generate leakage current between the two conductive terminals connected to the fuse pad after passing through the substrate and the insulating layer. The generation of leakage current will act on the semiconductor device in reverse to affect the trimming precision of the fuse, and the accumulation of leakage current will lead to the rapid decrease of the reliability of the IC.
Therefore, the present application particularly proposes a new fuse trimming structure, in which a PN junction conducting in a direction from the first insulating layer 20 to the N-type substrate 10 is formed between the insulating layer (i.e., the first insulating layer 20) below the fuse layer 30 of the fuse trimming structure and the N-type substrate 10, so that even when a large current applied to the fuse layer 30 blows out the fuse layer 30, the first insulating layer 20 below the fuse layer 30 is also damaged, and then, due to the existence of the reverse PN junction, the VCC of the N-type substrate 10 is still prevented from conducting to two conductive terminals (i.e., PAD and GND) connected to PADs of the fuse layer 30, so that the fuse trimming structure provided by the present application can effectively reduce the leakage current of the fuse trimming structure, thereby improving the reliability of the IC.
The details of the fuse trimming structure, the method for manufacturing the fuse trimming structure, and the integrated circuit provided in the present application will be described in detail below.
The first implementation mode comprises the following steps:
referring to fig. 1 and 2, the fuse trimming structure provided in the present application includes an N-type substrate 10, a first insulating layer 20 on the N-type substrate 10, a fuse layer 30 on the first insulating layer 20, and a second insulating layer 40 on the fuse layer 30; the fuse layer 30 is provided with a first bonding pad 51 and a second bonding pad 52 which are arranged at intervals, and the second insulating layer 40 is provided with a first window 41 exposing the first bonding pad 51 and a second window 42 exposing the second bonding pad 52; the fuse trimming structure further comprises a P-type region 60 located between the first insulating layer 20 and the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction that is conducted along the second insulating layer 40 toward the first insulating layer 20. The fuse trimming structure can solve the problem that the first insulating layer 20 is easily damaged when the fuse layer 30 is fused, thereby avoiding the leakage current generated by the fuse trimming structure and further improving the reliability of the IC.
The specific material of the N-type substrate 10 is not limited in this application, and those skilled in the art can select a suitable substrate material as needed as long as the substrate material is N-type. Of course, the N-type property of the N-type substrate 10 may be obtained by doping the substrate.
The first insulating layer 20 is located on the upper surface of the N-type substrate 10, and the arrangement of the first insulating layer 20 is known to those skilled in the art according to the structure level manner provided in the present application, and the first insulating layer 20 is used for electrically isolating the fuse layer 30 from the substrate layer. The thickness and material of the first insulating layer 20 are not particularly limited, and can be selected by those skilled in the art.
The fuse layer 30 is located above the first insulating layer 20, the fuse layer 30 is a core of the fuse trimming structure, and the fuse trimming structure is mainly trimmed by fusing or not fusing the fuse layer 30. Since the working principle of the fuse trimming structure has been described in detail in the foregoing application, it is not described herein again.
Alternatively, in one possible embodiment, the material of the fuse layer 30 is polysilicon. Thus, one of the advantages of the polysilicon fuse layer 30 over the metal fuse in the prior art is that it can be blown at a lower blowing current, and based on the advantage, the fuse trimming structure using the polysilicon fuse can be disposed at an internal position of the integrated circuit. The fuse layer 30 made of the polycrystalline silicon material is adopted, so that fusing current can be properly reduced when the fuse layer 30 is fused, and thus leakage current can be reduced to a certain extent, and the reliability of an IC (integrated circuit) is improved.
In addition, the fuse layer 30 is further provided with a first pad 51 and a second pad 52 which are spaced apart from each other, so that when the fuse trimming structure is connected to an integrated circuit, the fuse trimming structure can be connected to two conductive terminals of an external power source through the first pad 51 and the second pad 52. In short, by providing the first PAD 51 and the second PAD 52, the first PAD 51 and the second PAD 52 and the PAD terminal and the GND terminal can be connected, thereby facilitating the passage of the fusing current to the fuse layer 30.
The second insulating layer 40 is formed on a side of the fuse layer 30 facing away from the first insulating layer 20, i.e., an upper surface of the fuse layer 30. The second insulating layer 40 is disposed to prevent the fuse trimming structure from being invaded by impurities such as moisture.
Two windows, namely a first window 41 and a second window 42, are arranged on the second insulating layer 40, and the first window 41 and the first pad 51 are oppositely arranged and used for exposing the first pad 51; the second window 42 is disposed opposite to the second pad 52 for exposing the second pad 52, as shown in fig. 1. In this way, the connection of the fuse layer 30 and the external power source can be facilitated.
The present application further provides a P-type region 60 between the first insulating layer 20 and the N-type substrate 10 such that a PN junction conducting in a direction of the second insulating layer 40 toward the first insulating layer 20 can be formed between the P-type region 60 and the N-type substrate 10. Thus, even if the fuse trimming structure breaks the first insulating layer 20 due to a large blowing current flowing into the fuse layer 30, the leakage current generated from the VCC of the N-type substrate 10 toward the PAD or GND is prevented due to the PN junction, and thus, the reliability of the IC can be improved.
It should be noted that the material of the P-type region 60 is not limited in the present application, and those skilled in the art can select an appropriate material or perform doping with appropriate ions, as long as a PN junction conducting along the direction from the second insulating layer 40 to the first insulating layer 20 is formed between the P-type region 60 and the N-type substrate 10.
In summary, the fuse trimming structure provided by the present application includes an N-type substrate 10, a first insulating layer 20 located on the N-type substrate 10, a fuse layer 30 located on the first insulating layer 20, and a second insulating layer 40 located on the fuse layer 30; the fuse layer 30 is provided with a first bonding pad 51 and a second bonding pad 52 which are arranged at intervals, and the second insulating layer 40 is provided with a first window 41 exposing the first bonding pad 51 and a second window 42 exposing the second bonding pad 52; the fuse trimming structure further comprises a P-type region 60 located between the first insulating layer 20 and the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction conducting along the second insulating layer 40 towards the first insulating layer 20. The present application forms the P-type region 60 between the first insulating layer 20 of the fuse trimming structure and the N-type substrate 10, so that the N-type substrate 10 and the P-type region 60 together form a PN junction that is conducted along the second insulating layer 40 toward the first insulating layer 20. In this way, even if the fuse layer 30 is broken due to a large blowing current applied to the fuse layer 30 in order to effectively blow the fuse layer 30, the leakage current from the VCC of the N-type substrate 10 toward the PAD or GND is prevented due to the PN junction. By adopting the fuse trimming structure provided by the application, the leakage current can be effectively reduced, and the reliability of an IC (integrated circuit) can be improved.
In one possible embodiment, referring to fig. 2, an orthographic projection width of the p-type region 60 on the N-type substrate 10 is greater than a first width, which is a distance between orthographic projections of the first bonding pad 51 and the second bonding pad 52 on the N-type substrate 10.
That is, the width of the P-type region 60 is greater than the first width, and the width direction corresponds to the horizontal direction of fig. 2 in fig. 2. Since heat is easily accumulated to the first and second pads 51 and 52 of the fuse layer 30 when the fuse layer 30 is blown, the fuse layer 30 at the positions corresponding to the first and second pads 51 and 52 is easily blown and the relative positions of the first insulating layer 20 corresponding to the first and second pads 51 and 52 are also easily damaged when the fuse layer 30 is blown. Therefore, in order to make the PN junction effectively prevent the leakage current from the VCC of the N-type substrate 10 toward the PAD or GND, the width of the P-type region 60 needs to be greater than the first width.
Further, in order to prevent the leakage current from being generated in the direction from the VCC of the N-type substrate 10 toward the PAD or the GND, the orthographic projection width of the P-type region 60 on the N-type substrate 10 may be larger than the orthographic projection width of the fuse layer 30 on the N-type substrate 10.
In another possible embodiment, referring to fig. 3, the orthogonal projection of the p-type region 60 on the N-type substrate 10 coincides with the N-type substrate 10. Thus, the PN junction formed between the P-type region 60 and the N-type substrate 10 can better prevent leakage current from being generated in the direction from the VCC of the N-type substrate 10 toward the PAD or GND.
It should be noted that the forming method of the P-type region 60 is not limited in the present application, and the P-type region 60 may be formed by ion doping, deposition, or sputtering, for example. For example, when the width of the P-type region 60 is greater than the first width and less than the width of the N-type substrate 10, the P-type region 60 may be formed by performing P-type ion implantation on the upper surface of the N-type substrate 10; when the orthographic projection of the P-type region 60 on the N-type substrate 10 is coincident with the N-type substrate 10, the P-type region 60 can be formed by deposition or sputtering on the N-type substrate 10.
In one possible embodiment, the fuse layer 30 includes a first portion and two second portions at opposite ends of the first portion, the two second portions corresponding to the first pad 51 and the second pad 52, respectively; wherein the thickness of the first portion is less than the thickness of the second portion.
The first portion is a middle region of the fuse layer 30, and the two second portions are a left region and a right region of the fuse layer 30, respectively. It should be understood that the orientations shown in the left and right regions are only for convenience of understanding, and are not intended to limit the present application, by way of example only with the orientations shown in fig. 2 and 3.
In the present embodiment, the two second portions correspond to the first pad 51 and the second pad 52, respectively, that is, the two second portions are the area under the first pad 51 and the area under the second pad 52, respectively.
The thickness of the first portion is set to be smaller than that of the second portion because, on the one hand, the thickness of the first portion is small, so that it is possible to facilitate the fuse layer 30 to be fused from the first portion, as shown in fig. 4; on the other hand, the thickness of the second portion is large, so that when the fuse layer 30 is fused, the positions of the fuse layer 30 corresponding to the first pad 51 and the second pad 52 can be effectively prevented from being fused rapidly due to the fact that heat is easily accumulated to the first pad 51 and the second pad 52 of the fuse layer 30, and thus, the position of the first insulating layer 20 which is most easily damaged can be protected to a certain extent (since the positions of the first insulating layer 20 corresponding to the first pad 51 and the second pad 52 are easily damaged, the thickness of the fuse layer 30 at the position is increased, and the risk that the first insulating layer 20 is damaged can be reduced to a certain extent).
To further reduce the risk of damage to the first insulating layer 20, in one possible embodiment, the first insulating layer 20 includes an insulating layer main body and two insulating layer end portions at opposite ends of the insulating layer main body, the two insulating layer end portions corresponding to the first pad 51 and the second pad 52, respectively; wherein, the thickness of the end parts of the two insulating layers is larger than that of the insulating layer main body.
It should be understood that the main body of the insulating layer is the middle region of the first insulating layer 20, and the two insulating layer ends, i.e., the first insulating layer 20 is located at a position below the first pad 51 and the first insulating layer 20 is located at a position below the second pad 52.
The thickness of the end parts of the two insulating layers is larger than that of the insulating layer main body, so that the risk that the first insulating layer 20 is damaged can be effectively reduced in a mode of increasing the thickness of the end parts of the insulating layers.
In the above, the present application forms the P-type region 60 between the first insulating layer 20 of the fuse trimming structure and the N-type substrate 10, so that the N-type substrate 10 and the P-type region 60 together form a PN junction that is conducted toward the first insulating layer 20 along the second insulating layer 40. And choose the polycrystalline silicon for the material of the fuse layer 30, set up the fuse layer 30 as the form that the middle is thin both sides are thick, set up the first insulating layer 20 as the form that both sides are thick, like this, at first, because the fuse layer 30 of the polycrystalline silicon material that chooses for use, like this, can use less fusing current to fuse the fuse layer 30 easily as far as possible, even if still lead to the first insulating layer 20 below the fuse layer 30 to be damaged in the fusing process, then also can be because of the existence of this PN junction, and the VCC that prevents N type substrate 10 is towards PAD or GND's direction and is produced the leakage current. Therefore, by adopting the fuse trimming structure provided by the application, the leakage current can be effectively reduced, and the reliability of the IC can be improved.
The second embodiment:
referring to fig. 5, the present invention further provides a method for manufacturing a fuse trimming structure, which includes the following steps:
s100, providing an N-type substrate 10.
The material and thickness of the N-type substrate 10 are not limited in this application and can be selected by those skilled in the art.
S200, forming a P-type region 60 on the N-type substrate 10, wherein the P-type region 60 and the N-type substrate 10 jointly form a PN junction.
The P-type region 60 may be formed by performing ion implantation on the N-type substrate 10, or may be formed by depositing or sputtering a corresponding material on the N-type substrate 10, which is not particularly limited in this application.
S300, forming a first insulating layer 20 on the P-type region 60, wherein the first insulating layer 20 covers the P-type region 60.
S400, forming a fuse layer 30 on the first insulating layer 20, the fuse layer 30 having spaced first and second pads 51 and 52 thereon, and the fuse layer 30 and the N-type substrate 10 being electrically isolated by the first insulating layer 20.
S500, a second insulating layer 40 covering the fuse layer 30 is formed on the fuse layer 30.
That is, the first insulation layer 20, the fuse layer 30, and the second insulation layer 40 are sequentially formed to be on the P-type region 60.
It should be noted that, for the materials, thicknesses, structural forms, and the like of the N-type substrate 10, the P-type region 60, the first insulating layer 20, the fuse layer 30, and the second insulating layer 40, reference may be made to the related description of the structural portion of the fuse trimming structure in the foregoing, and in order to avoid repeated descriptions, the same portions are not repeated in this embodiment.
S600, opening a first window 41 exposing the first pad 51 and a second window 42 exposing the second pad 52 on the second insulating layer 40 by a photolithography process.
Since the photolithography process is well known to those skilled in the art, the specific steps of forming the first window 41 exposing the first pad 51 and the second window 42 exposing the second pad 52 on the second insulating layer 40 by photolithography process are not described in detail in the present application.
The fuse structure prepared by the preparation method of the fuse trimming structure provided by the embodiment can prevent leakage current from being generated in the direction from the VCC of the N-type substrate 10 to the PAD or GND due to the existence of the PN junction, and thus can improve the reliability of the IC.
In one possible embodiment, the step S200 of forming the P-type region 60 on the N-type substrate 10, the P-type region 60 and the N-type substrate 10 together forming a PN junction, includes:
a P-type region 60 is formed in the N-type substrate 10 by an ion implantation process, an upper surface of the P-type region 60 is flush with an upper surface of the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction, as shown in fig. 2.
The type of the ions to be implanted is not limited in the present application, and any type of ions may be used as long as P-type ions can form a PN junction with the N-type substrate 10, which is electrically connected from the second insulating layer 40 to the first insulating layer 20.
In another possible embodiment, the step S200 of forming the P-type region 60 on the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction, includes:
a P-type region 60 is formed on the N-type substrate 10 by a deposition process or a sputtering process, the P-type region 60 covers the upper surface of the N-type substrate 10, and the P-type region 60 and the N-type substrate 10 together form a PN junction, as shown in fig. 3.
The third embodiment is as follows:
the invention also provides an integrated circuit which comprises the fuse trimming structure. Since the specific hierarchical structure of the fuse trimming structure and the beneficial effects thereof have been described in detail in the foregoing, the present application is not repeated herein. The integrated circuit obtained by the fuse trimming structure provided by the application can prevent the fuse trimming structure from generating leakage current due to the existence of the PN junction in the fuse trimming structure, and further can improve the reliability of an IC.
While the invention has been described with reference to several particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A fuse trimming structure is characterized by comprising an N-type substrate, a first insulating layer positioned on the N-type substrate, a fuse layer positioned on the first insulating layer and a second insulating layer positioned on the fuse layer; the fuse layer is provided with a first bonding pad and a second bonding pad which are arranged at intervals, and the second insulating layer is provided with a first window exposing the first bonding pad and a second window exposing the second bonding pad; the fuse trimming structure further comprises a P-type region located between the first insulating layer and the N-type substrate, and the P-type region and the N-type substrate jointly form a PN junction conducted along the direction of the second insulating layer towards the first insulating layer.
2. The fuse trimming structure according to claim 1, wherein an orthographic projection width of the P-type region on the N-type substrate is greater than a first width, the first width being a distance between orthographic projections of the first and second pads on the N-type substrate.
3. The fuse trimming structure of claim 2, wherein an orthographic projection of the P-type region on the N-type substrate coincides with the N-type substrate.
4. The fuse trimming structure of claim 1, wherein the fuse layer is made of polysilicon.
5. The fuse trimming structure according to claim 1, wherein the fuse layer comprises a first portion and two second portions at opposite ends of the first portion, the two second portions corresponding to the first pad and the second pad, respectively; wherein the thickness of the first portion is less than the thickness of the second portion.
6. The fuse trimming structure according to claim 1 or 5, wherein the first insulating layer comprises an insulating layer main body and two insulating layer end portions located at two opposite ends of the insulating layer main body, and the two insulating layer end portions correspond to the first pad and the second pad, respectively; the thickness of the two end parts of the insulating layer is larger than that of the insulating layer main body.
7. A preparation method of a fuse trimming structure is characterized by comprising the following steps:
providing an N-type substrate;
forming a P-type area on the N-type substrate, wherein the P-type area and the N-type substrate jointly form a PN junction;
forming a first insulating layer on the P-type region, wherein the first insulating layer covers the P-type region;
forming a fuse layer on the first insulating layer, the fuse layer having first and second pads spaced apart thereon, and the fuse layer and the N-type substrate being electrically isolated by the first insulating layer;
forming a second insulating layer on the fuse layer to cover the fuse layer;
and forming a first window exposing the first bonding pad and a second window exposing the second bonding pad on the second insulating layer through a photoetching process.
8. The method of claim 7, wherein forming a P-type region on the N-type substrate, the P-type region and the N-type substrate together forming a PN junction, comprises:
and forming a P-type region in the N-type substrate by an ion implantation process, wherein the upper surface of the P-type region is flush with the upper surface of the N-type substrate, and the P-type region and the N-type substrate together form a PN junction.
9. The method of claim 7, wherein forming a P-type region on the N-type substrate, the P-type region and the N-type substrate together forming a PN junction, comprises:
and forming a P-type area on the N-type substrate through a deposition process or a sputtering process, wherein the P-type area covers the upper surface of the N-type substrate, and the P-type area and the N-type substrate jointly form a PN junction.
10. An integrated circuit comprising the fuse trimming structure of any one of claims 1 to 6.
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| JPH0541481A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor integrated circuit |
| CN1226084A (en) * | 1998-02-12 | 1999-08-18 | 日本电气株式会社 | Semiconductor device and method of manufacturing it |
| CN101170099A (en) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
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2022
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0541481A (en) * | 1991-08-06 | 1993-02-19 | Nec Corp | Semiconductor integrated circuit |
| CN1226084A (en) * | 1998-02-12 | 1999-08-18 | 日本电气株式会社 | Semiconductor device and method of manufacturing it |
| CN101170099A (en) * | 2007-11-30 | 2008-04-30 | 上海宏力半导体制造有限公司 | Multicrystalline silicon compounds electric fuse silk part |
| CN109244061A (en) * | 2018-09-03 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | Electrically programmable fuse structure and forming method thereof |
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