CN115810545A - Super junction device structure and forming method thereof - Google Patents

Abstract

A super junction device structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a first epitaxial layer and an active electric field intervening layer on a substrate, wherein first ions are arranged in the first epitaxial layer, second ions are arranged in the active electric field intervening layer, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is smaller than that of the first ions; forming a plurality of super junction grooves in the first epitaxial layer and the active electric field intervening layer; and forming a second epitaxial layer in the super junction groove, wherein the second epitaxial layer has third ions, and the conductivity type of the third ions is different from that of the first ions. Through forming initiative electric field intervention layer in first epitaxial layer, it is internal to utilize initiative electric field intervention layer to introduce the electric field peak, reduces the electric field peak and causes the influence to the device structure on the first epitaxial layer, effectively promotes device stability, reverse breakdown BV and EAS ability, and then promotes the performance of device structure.

Description

Super junction device structure and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a super junction device structure and a forming method thereof.

Background

The super junction is formed by alternately arranging P-type thin layers, also called P-type columns (Pillar), and N-type thin layers, also called N-type columns, formed in a semiconductor substrate, and one P-type column and one corresponding adjacent N-type column form a super junction unit. The devices employing the super junction are super junction devices such as super junction MOSFETs. The technology of reducing the surface electric field (Resurf) in the body by utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and simultaneously keep smaller on-resistance.

The PN-spaced Pillar structure of the super junction is the biggest characteristic of the super junction. The conventional method for manufacturing the p-n spaced pilar structure mainly comprises two methods, one is obtained by multiple times of epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxy (EPI) filling. The latter method is to fabricate the super junction device by a trench process, in which a trench with a certain depth and width is first etched on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then a P-type doped silicon epitaxy is filled on the etched trench by an epitaxial Filling (EPI Filling) method.

A key technical difficulty in fabricating a super junction device by a trench process is the trench fill process. The groove filling is carried out in a mode of synchronous etching filling. The etching is introduced for eliminating the defect that the top of the trench is closed in advance, so that a hollow hole is generated in the trench. But due to the existence of the etching effect, the filling speed is extremely slow, the epitaxial filling efficiency is very low, and the cost is extremely high. Particularly, in the case that the step (Pitch) is continuously reduced and the trench opening is continuously reduced, a slower filling rate is required to achieve a good filling effect, the occupation of the production energy is more and more significant, and the cost is significantly increased. The super junction is stepped to the sum of the width of the grooves and the space between the grooves, and also to the sum of the width of one N-type column and the width of one P-type column, namely the width of one super junction unit.

However, there are still many problems with the prior art super junction device structures.

Disclosure of Invention

The invention provides a super junction device structure and a forming method thereof, which aims to improve the performance of the device structure.

In order to solve the above problems, the present invention provides a method for forming a super junction device structure, including: providing a substrate; forming a first epitaxial layer and at least one active electric field intervening layer on the substrate, wherein the active electric field intervening layer is positioned in the first epitaxial layer, first ions are arranged in the first epitaxial layer, second ions are arranged in the active electric field intervening layer, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is smaller than that of the first ions; forming a plurality of mutually-separated super junction grooves in the first epitaxial layer and the active electric field intervening layer; and forming a second epitaxial layer in the super junction trench, wherein third ions are arranged in the second epitaxial layer, and the conductivity type of the third ions is different from that of the first ions.

Optionally, at least one active electric field intervening layer is formed during the process of forming the first epitaxial layer.

Optionally, the method for forming the first epitaxial layer and the at least one active electric field intervening layer on the substrate includes: forming the first epitaxial layer by adopting a first epitaxial growth process; and in the process of forming the first epitaxial layer, at least one second epitaxial process is adopted, at least one active electric field intervening layer is formed in the first epitaxial layer, and the process parameters of the second epitaxial process are different from those of the first epitaxial process.

Optionally, at least one active electric field intervening layer is formed after the first epitaxial layer is formed.

Optionally, the method for forming the first epitaxial layer and the at least one active electric field intervening layer on the substrate includes: forming the first epitaxial layer by adopting a first epitaxial growth process; after the first epitaxial layer is formed, at least one layer of active electric field intervening layer is formed in the first epitaxial layer by adopting at least one inversion ion implantation treatment.

Optionally, the thickness of the active electric field intervening layer is: 0.1 micron to 50% of the thickness of the first epitaxial layer.

Optionally, the depth of the active electric field intervening layer is: 1 micron to 80% of the thickness of the first epitaxial layer.

Optionally, the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent.

Optionally, the forming method of the second epitaxial layer includes: forming an initial second epitaxial layer in the super junction trench and on the first epitaxial layer by adopting a third epitaxial growth process, wherein the initial second epitaxial layer has the third ions; and carrying out planarization treatment on the initial second epitaxial layer to form a second epitaxial layer, wherein the second epitaxial layer is filled in the super junction groove.

Optionally, before forming the super junction trench, the method further includes: and forming a plurality of mutually-separated gate structures in the first epitaxial layer.

Optionally, the gate structure includes a gate oxide layer and a polysilicon gate layer stacked in sequence.

Optionally, the gate structure includes: a trench gate structure or a planar gate structure.

Optionally, when the gate structure is a trench gate structure, the method for forming the gate structure includes: forming a grid groove in the first epitaxial layer; forming a gate oxide material layer on the side wall and the bottom surface of the gate trench and the first epitaxial layer; forming a polysilicon gate material layer on the gate oxide material layer; and carrying out planarization treatment on the gate oxide material layer and the polysilicon gate material layer to form the gate structure.

Optionally, when the gate structure is a planar gate structure, the method for forming the gate structure includes: forming a gate oxide material layer on the first epitaxial layer; forming a polysilicon gate material layer on the gate oxide material layer; and carrying out graphical processing on the gate oxide material layer and the polysilicon gate material layer to form the gate structure.

Optionally, after the gate structure is formed, the method further includes: and forming source regions in the first epitaxial layer at two sides of the grid structure.

Optionally, before forming the super junction trench, the method further includes: and forming a body region in the first epitaxial layer.

Optionally, after forming the second epitaxial layer, the method further includes: forming a dielectric layer on the first epitaxial layer; forming a plurality of conductive plugs on the first epitaxial layer; forming a first metal layer on the conductive plugs; and after the first metal layer is formed, carrying out back surface process treatment.

Correspondingly, the technical solution of the present invention further provides a super junction device structure, including: a substrate; a first epitaxial layer on the substrate, the first epitaxial layer having first ions therein; at least one active electric field intervening layer positioned in the first epitaxial layer, wherein second ions are arranged in the active electric field intervening layer, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is smaller than that of the first ions; a plurality of mutually discrete super junction trenches located within the first epitaxial layer and the active electric field intervening layer; and the second epitaxial layer is positioned in the super junction groove, third ions are arranged in the second epitaxial layer, and the conductivity type of the third ions is different from that of the first ions.

Optionally, the thickness of the active electric field intervening layer is: 0.1 micron to 50% of the thickness of the first epitaxial layer.

Optionally, the depth of the active electric field intervening layer is: 1 micron to 80% of the thickness of the first epitaxial layer.

Optionally, the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent.

Optionally, the method further includes: and the plurality of mutually-separated gate structures are positioned in the first epitaxial layer.

Optionally, the gate structure includes a gate oxide layer and a polysilicon gate layer stacked in sequence.

Optionally, the gate structure includes: trench gate structures or planar gate structures.

Optionally, the method further includes: and the source regions are positioned at two sides of the gate structure and in the first epitaxial layer.

Optionally, the method further includes: a body region located within the first epitaxial layer.

Optionally, the method further includes: a dielectric layer located on the first epitaxial layer; a plurality of conductive plugs located on the first epitaxial layer; a first metal layer located on the plurality of conductive plugs.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the method for forming the super junction device structure, at least one active electric field intervention layer is formed in the first epitaxial layer, and an electric field peak is introduced into a body by using the active electric field intervention layer, so that the influence of the electric field peak on the device structure on the first epitaxial layer is reduced, the stability of the device, the reverse breakdown BV (BV) and the EAS (electronic article surveillance) capability are effectively improved, and the performance of the device structure is further improved.

Further, the thickness of the active electric field intervening layer is as follows: 0.1 micron to 50% of the thickness of the first epitaxial layer. When the thickness of the active electric field intervention layer is less than 0.1 micrometer, the introduction effect of the active electric field intervention layer on an electric field peak is poor; when the thickness of the active electric field intervention layer is greater than 50% of the thickness of the first epitaxial layer, the on-resistance introduced by the active electric field intervention layer is large, and the performance of the device structure is further influenced.

Further, the formation depth of the active electric field intervening layer is as follows: 1 micron to 80% of the thickness of the first epitaxial layer. When the active electric field intervening layer is formed to a depth of less than 1 μm, it is difficult for the active electric field intervening layer to introduce an electric field peak into the body; when the formation depth of the active electric field intervening layer is greater than 80% of the thickness of the first epitaxial layer, the influence of the active electric field intervening layer on the surface electric field is too small, and it is also difficult to introduce an electric field peak into the body.

Further, the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent. When the second ion doping concentration is less than 0.01% of the first ion doping concentration, the requirement on the manufacturing process is high, and the realization is difficult; when the second ion doping concentration is greater than 80% of the first ion doping concentration, the active electric field intervening layer has a poor effect of reducing the surface electric field.

The super junction device structure comprises at least one active electric field intervening layer positioned in the first epitaxial layer, and an electric field peak is introduced into the body by utilizing the active electric field intervening layer, so that the influence of the electric field peak on the device structure on the first epitaxial layer is reduced, the stability of the device, the reverse breakdown BV (potential of Hydrogen) and the EAS (Electron emission Signal) capability are effectively improved, and the performance of the device structure is further improved.

Further, the thickness of the active electric field intervening layer is: 0.1 micron to 50% of the thickness of the first epitaxial layer. When the thickness of the active electric field intervention layer is less than 0.1 micrometer, the introduction effect of the active electric field intervention layer on an electric field peak is poor; when the thickness of the active electric field intervention layer is greater than 50% of the thickness of the first epitaxial layer, the on-resistance introduced by the active electric field intervention layer is large, and the performance of the device structure is further influenced.

Further, the formation depth of the active electric field intervening layer is: 1 micron to 80% of the thickness of the first epitaxial layer. When the active electric field intervening layer is formed to a depth of less than 1 μm, it is difficult for the active electric field intervening layer to introduce an electric field peak into the body; when the formation depth of the active electric field intervening layer is greater than 80% of the thickness of the first epitaxial layer, the influence of the active electric field intervening layer on the surface electric field is too small, and it is also difficult to introduce an electric field peak into the body.

Further, the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent. When the second ion doping concentration is less than 0.01% of the first ion doping concentration, the requirement on the manufacturing process is high, and the realization is difficult; when the second ion doping concentration is greater than 80% of the first ion doping concentration, the active electric field intervening layer has a poor effect of reducing the surface electric field.

Drawings

FIG. 1 is a schematic structural diagram of a super junction device structure;

FIG. 2 is a distribution curve of electric field with super junction trench depth under P-type charge under-matching;

FIGS. 3-12 are schematic structural views of the super junction device structure and the steps of the method of forming the same in an embodiment of the present invention;

FIG. 13 is a graph showing the electric field distribution with the depth of the super junction trench under the condition of P-type charge under-matching in the embodiment of the present invention.

Detailed Description

As described in the background, problems still exist with prior art super junction device structures. The following detailed description will be made in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a super junction device structure; fig. 2 is a profile of electric field with super junction trench depth for P-type charge under-matching.

Referring to fig. 1, a super junction device structure includes: a substrate 100; a first epitaxial layer 101 on the substrate 100, the first epitaxial layer 101 having first ions therein; a plurality of mutually discrete super junction trenches (not labeled) located within the first epitaxial layer 101; and a second epitaxial layer 102 located in the super junction trench, wherein the second epitaxial layer 102 has second ions therein, and the conductivity type of the second ions is different from that of the first ions.

In this embodiment, the first ions are N-type ions, the second ions are P-type ions, and the super junction device structure is a MOSFET structure that utilizes a PN charge balance in-vivo SURface electric Field reduction (Reduced SURface Field, resurf) technique to improve reverse breakdown BV of the device and maintain a small on-resistance. PN spaced conductivity type pillars (pilar) are the largest feature of super junction devices. When PN charges in the super junction device are completely matched, the electric field of the super junction device is rectangular, and compared with a triangular electric field of a common MOS, the breakdown voltage is greatly improved.

However, when the P-type charge in the super junction device is under-matched (e.g., the P-type ions are relatively weak), the electric field peak of the super junction device appears near the surface (as shown in fig. 2), which causes the problems of poor device stability, reverse breakdown BV, poor long-term reliability, greatly reduced EAS capability, and the like.

On the basis, the invention provides a super junction device structure and a forming method thereof, wherein at least one active electric field intervention layer is formed in the first epitaxial layer, and an electric field peak is introduced into a body by using the active electric field intervention layer, so that the influence of the electric field peak on the device structure on the first epitaxial layer is reduced, the stability of the device, the reverse breakdown BV (BV) and the EAS (electronic article surveillance) capability are effectively improved, and the performance of the device structure is further improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

FIGS. 3-12 are schematic structural diagrams of the super junction device structure and the steps of the method for forming the same according to the embodiment of the invention; FIG. 13 is a graph showing the electric field distribution with the depth of the super junction trench under the condition of P-type charge under-matching in the embodiment of the present invention.

Referring to fig. 3, a substrate 200 is provided.

In this embodiment, silicon is used as the material of the substrate 200.

In this embodiment, the substrate 200 includes a first side 201 and a second side 202 opposite to each other, where the first side 201 is a top surface of the substrate 200, and the second side 202 is a bottom surface of the substrate 200.

Referring to fig. 4, a first epitaxial layer 203 and at least one active electric field intervening layer 204 are formed on the substrate 200, the active electric field intervening layer 204 is located in the first epitaxial layer 203, the first epitaxial layer 203 has first ions therein, the active electric field intervening layer 204 has second ions therein, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is less than that of the first ions.

In this embodiment, through in form at least once initiative electric field intervenes the layer in the first epitaxial layer, utilize initiative electric field intervenes the layer and introduces the electric field peak in vivo (as shown in fig. 13), it is right to reduce the electric field peak device structure on the first epitaxial layer causes the influence, effectively promotes device stability, reverse breakdown BV and EAS ability, and then promotes the performance of device structure.

In this embodiment, the super junction device is an N-type device, and the first ions are N-type ions; in other embodiments, when the super junction device is a P-type device, the first ions are P-type ions.

In this embodiment, the conductivity type of the second ions is the same as the conductivity type of the first ions, i.e., the second ions are N-type ions; in other embodiments, when the first ions are P-type ions, the second ions are P-type ions.

In this embodiment, at least one active electric field intervening layer 204 is formed after the first epitaxial layer 203 is formed; the corresponding method for forming the first epitaxial layer 203 and the at least one active electric field intervening layer 204 on the substrate 200 comprises the following steps: forming the first epitaxial layer 203 by using a first epitaxial growth process; after the first epitaxial layer 203 is formed, at least one active electric field intervening layer 204 is formed in the first epitaxial layer 203 by using at least one inversion ion implantation process.

In this embodiment, the inversion ion implantation process is to perform inversion ion implantation, that is, the conductivity type of the implanted ions is opposite to the conductivity type of the first ions, that is, the implanted ions are P-type ions, and the inversion ions are used to neutralize part of the ions in the first epitaxial layer, so as to reduce the ion concentration in this region, thereby forming the active electric field intervening layer 204.

In this embodiment, the first ions and the third ions are the same ions.

In other embodiments, at least one active electric field intervening layer may be formed during the formation of the first epitaxial layer; the corresponding method for forming the first epitaxial layer and the at least one active electric field intervening layer on the substrate comprises the following steps: forming the first epitaxial layer by adopting a first epitaxial growth process; and in the process of forming the first epitaxial layer, at least one second epitaxial process is adopted, at least one active electric field intervening layer is formed in the first epitaxial layer, and the process parameters of the second epitaxial process are different from those of the first epitaxial process.

In this embodiment, the number of the active electric field intervening layers 204 is 1, which can effectively reduce the cost of the process.

In other embodiments, the number of active electric field intervening layers may also be multiple.

In this embodiment, the thickness of the active electric field intervening layer 204 is: 0.1 micron to 50% of the thickness of the first epitaxial layer 203, i.e. the distance between the top surface and the bottom surface of the active electric field insertion layer 204 in a direction perpendicular to the top of the first epitaxial layer 203. When the thickness of the active electric field intervening layer 204 is less than 0.1 μm, the effect of the active electric field intervening layer 204 on introducing the electric field peak is not good; when the thickness of the active electric field intervening layer 204 is greater than 50% of the thickness of the first epitaxial layer 203, the on-resistance introduced by the active electric field intervening layer 204 is relatively large, and the performance of the device structure is further influenced

In this embodiment, the depth of the active electric field intervening layer 204 is 1 μm to 80% of the thickness of the first epitaxial layer 203, i.e. the distance between the bottom surface of the active electric field intervening layer 204 and the top surface of the first epitaxial layer 203 along the direction perpendicular to the top surface of the first epitaxial layer 203. When the active electric field intervening layer 204 is formed to a depth of less than 1 μm, it is difficult for the active electric field intervening layer 204 to introduce an electric field peak into the body; when the active electric field intervening layer 204 is formed to a depth greater than 80% of the thickness of the first epitaxial layer 203, the influence of the active electric field intervening layer 204 on the surface electric field is too small to introduce an electric field peak into the body.

In this embodiment, the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent. When the second ion doping concentration is less than 0.01% of the first ion doping concentration, the requirement on the manufacturing process is high, and the realization is difficult; when the second ion doping concentration is greater than 80% of the first ion doping concentration, the active electric field intervening layer 204 has a poor effect of reducing the surface electric field.

After the first epitaxial layer 203 and the active electric field intervening layer 204 are formed, the method further includes: and performing a gate structure forming process, and forming a plurality of gate structures in the first epitaxial layer 203. Please refer to fig. 5 to 7.

Referring to fig. 5, a plurality of gate structures 205 separated from each other are formed in the first epitaxial layer 203.

In this embodiment, the gate structure 205 includes a gate oxide layer and a polysilicon gate layer (not labeled) stacked in sequence.

In this embodiment, the gate structure 205 is a trench gate structure, and the corresponding method for forming the gate structure 205 includes: forming a gate trench (not labeled) within the first epitaxial layer 203; forming a gate oxide layer (not shown) on the sidewalls and bottom surface of the gate trench and on the first epitaxial layer 203; forming a polysilicon gate material layer (not shown) on the gate oxide material layer; and carrying out planarization treatment on the gate oxide material layer and the polysilicon gate material layer to form the gate structure 205.

In other embodiments, the gate structure may also be a planar gate structure, and the corresponding method for forming the gate structure includes: forming a gate oxide material layer on the first epitaxial layer; forming a polysilicon gate material layer on the gate oxide material layer; and carrying out graphical processing on the gate oxide material layer and the polysilicon gate material layer to form the gate structure.

Referring to fig. 6, after the gate structure 205 is formed, a body region 206 is formed in the first epitaxial layer 203.

In this embodiment, the formation region of body region 206 is defined by photolithography, and body region 206 is formed by ion implantation and an annealing drive-in process.

Referring to fig. 7, after the body region 206 is formed, source regions 207 are formed in the first epitaxial layer 203 on both sides of the gate structure 205.

In this embodiment, the formation region of the source region 207 is defined by photolithography, and the source region 207 is formed by ion implantation and an annealing process, and the source region 207 and the corresponding side surface of the gate structure 205 are self-aligned.

After forming the source region 207, further comprising: and performing a super junction forming process to form a plurality of super junction units in the first epitaxial layer 203. Please refer to fig. 7 to fig. 11 for a specific forming process.

Referring to fig. 8, a plurality of super junction trenches 208 are formed in the first epitaxial layer 203 and the active electric field intervening layer 204, which are separated from each other.

In this embodiment, a forming region of the super junction trench 208 is defined by photolithography, and a plurality of super junction trenches 208 are formed in the first epitaxial layer 203 by an etching process, where the super junction trenches 208 have in-plane distribution non-uniformity caused by the photolithography process and the etching process.

In this embodiment, the method for forming the super junction trench 208 includes: a mask structure can be formed on the first epitaxial layer 203; forming a photoresist layer (not shown) on the mask structure, the photoresist layer exposing a portion of a top surface of the mask structure; etching the mask structure by taking the photoresist layer as a mask, and forming a mask opening in the mask structure, wherein the mask opening exposes part of the top surface of the first epitaxial layer 203; and removing the photoresist layer, and etching the first epitaxial layer 203 by taking the mask structure as a mask to form the super junction groove 208.

In this embodiment, the mask structure includes: a bottom oxide layer 209, an intermediate nitride layer 210 on the bottom oxide layer 209, and a top oxide layer 211 on the intermediate nitride layer 210 (ONO structure).

After forming the super junction trench 208, the method further includes: a second epitaxial layer is formed within the super junction trench 208 having third ions therein of a different conductivity type than the first ions. Please refer to fig. 8 to fig. 11 for a specific forming process.

Referring to fig. 9, a third epitaxial growth process is employed to form an initial second epitaxial layer 212 within the super junction trench 208 and on the first epitaxial layer 203, the initial second epitaxial layer 212 having the third ions therein.

In this embodiment, before the forming the initial second epitaxial layer 212 by using an epitaxial growth process, the method further includes: the top oxide layer 211 and the middle nitride layer 210 are removed.

Referring to fig. 10, the initial second epitaxial layer 212 is planarized to form a second epitaxial layer 213, and the second epitaxial layer 213 is filled in the super junction trench 208.

In this embodiment, the planarization process employs a chemical mechanical polishing process; in other embodiments, the planarization process may also employ a wet etching process.

In this embodiment, the bottom oxide layer 209 is removed to a partial thickness after the planarization process.

In other embodiments, the bottom oxide layer may also be completely removed after the planarization process.

Referring to fig. 11, a dielectric layer 214 is formed on the first epitaxial layer 211.

So far, the formation process of the super junction is completed.

After the super junction forming process is completed, the first epitaxial layer 203 between the adjacent super junction trenches 208 is a first conductive type column (pilar), the second epitaxial layer 213 in the super junction trenches 208, or the second epitaxial layer 213 in the super junction trenches 208 and the dielectric layer 214 corresponding to the super junction trenches 208 in an overlapped manner are second conductive type columns, the super junction is formed by alternately arranging the first conductive type columns and the second conductive type columns, and a super junction unit is formed by one first conductive type column and one adjacent second conductive type column.

In this embodiment, the super junction forming process is placed after the gate structure 205 forming process, so that adverse effects on interdiffusion of the first ions and the second ions in each super junction unit caused by a thermal process of the gate oxide layer growing process in the gate structure 205 forming process and a thermal process of the polysilicon gate layer growing process can be eliminated, and adverse effects on the dielectric layer 214 caused by the gate oxide layer etching process can be eliminated, so that process stability of a super junction device can be improved and performance of the device can be further improved.

In this embodiment, the process sequence of the super junction device structure is as follows: and forming the gate structure, the body region, the source region and the super junction.

In other embodiments, the process sequence of the super junction device structure may further include: and forming the body region, the gate structure, the source region and the super junction.

In other embodiments, the process sequence of the super junction device structure may further include: the gate structure is formed first, the body region is formed, the super junction is formed, and the source region is formed.

In other embodiments, the process sequence of the super junction device structure may further include: and forming the body region, the gate structure, the super junction and the source region.

In this embodiment, the dielectric layer 214 is formed by overlapping a part of interlayer films formed by a thermal oxide layer and a USG or TEOS oxide layer, where the thickness of the field oxide is usually 150 angstroms to 8000 angstroms, and the typical value is 1500 angstroms; the USG or TEOS oxide layer has a thickness of 5000-15000 angstroms.

In this embodiment, the dielectric layer 214 is not processed; in other embodiments, the dielectric layer may be planarized by a chemical mechanical polishing process.

Referring to fig. 12, after forming the dielectric layer 214, a plurality of conductive plugs 215 are formed on the first epitaxial layer 203; after forming the conductive plugs 215, forming a first metal layer 216 on a number of the conductive plugs 215; after the first metal layer 216 is formed, a backside process is performed.

In this embodiment, before forming a plurality of the conductive plugs 215, the method further includes: a BPSG film 217 is formed over the dielectric layer 214 to increase thickness and planarize. On the active region, the USG or TEOS oxide layer in the dielectric layer 214 and the BPSG film layer 217 are stacked to form an interlayer film.

In other embodiments, the thickness of the dielectric layer may also be made directly to the total requirements of the interlayer film.

In this embodiment, the method for forming the conductive plugs 215 includes: a conductive opening (not shown) is formed by photolithography definition, and a conductive material (e.g., tungsten) is filled in the conductive opening to form the conductive plug 215.

In this embodiment, the method for forming the first metal layer 216 includes: forming a first metal material layer (not shown); a lithography definition and etching process is performed on the first metal material layer to form the first metal layer 216.

In this embodiment, the first metallic material layer is deposited by a hot aluminum (hot Al) process.

In this embodiment, after forming the first metal layer 216, the method further includes: contact pads (not shown) are formed, the formation areas of which are defined by photolithography.

In this embodiment, the process for forming the contact pad includes: depositing a Passivation layer (Passivation), photoetching, etching the Passivation layer to expose the first metal layer 216 in the contact pad region, removing the photoresist, and carrying out H ₂ Alloying; followed by a pre-grind process (BG).

In this embodiment, the process for completing the back surface of the super junction device includes: the substrate 200 is thinned in a direction from the second surface 202 toward the first surface 202.

In this embodiment, the substrate 200 is also doped with the first ions, so that the thinned substrate 200 can be directly used as a drain region.

In other embodiments, the substrate 1 after thinning may be further subjected to a heavy doping process of the first ions to form the drain region.

Accordingly, an embodiment of the present invention further provides a super junction device structure, please continue to refer to fig. 12, including: a substrate 200; a first epitaxial layer 203 on the substrate 200, the first epitaxial layer 203 having first ions therein; at least one active electric field intervening layer 204 located in the first epitaxial layer 203, wherein second ions are located in the active electric field intervening layer 204, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is less than that of the first ions; a plurality of mutually discrete super junction trenches 208 located within the first epitaxial layer 203 and the active electric field intervening layer 204; and a second epitaxial layer 213 positioned in the super junction trench 208, wherein a third ion having a conductivity type different from that of the first ion is provided in the second epitaxial layer 213.

In this embodiment, the active electric field insertion layer 204 is used to introduce an electric field peak into the body, so as to reduce the influence of the electric field peak on the device structure on the first epitaxial layer 203, effectively improve the device stability, reverse breakdown BV and EAS capabilities, and further improve the performance of the device structure.

In this embodiment, the number of the active electric field intervening layers 204 is 1, which can effectively reduce the cost of the process.

In other embodiments, the number of active electric field intervening layers 204 may also be multiple.

In this embodiment, the thickness of the active electric field intervening layer 204 is: 0.1 micron to 50% of the thickness of the first epitaxial layer 203, i.e. the distance between the top surface and the bottom surface of the active electric field insertion layer 204 in a direction perpendicular to the top of the first epitaxial layer 203. When the thickness of the active electric field intervening layer 204 is less than 0.1 μm, the effect of introducing the electric field peak into the active electric field intervening layer 204 is not good; when the thickness of the active electric field intervening layer 204 is greater than 50% of the thickness of the first epitaxial layer 203, the on-resistance introduced by the active electric field intervening layer 204 is relatively large, and the performance of the device structure is further influenced

In this embodiment, the depth of the active electric field intervening layer 204 is 1 μm to 80% of the thickness of the first epitaxial layer 203, i.e. the distance between the bottom surface of the active electric field intervening layer 204 and the top surface of the first epitaxial layer 203 along the direction perpendicular to the top surface of the first epitaxial layer 203. When the active electric field intervening layer 204 is formed to a depth of less than 1 μm, it is difficult for the active electric field intervening layer 204 to introduce an electric field peak into the body; when the active electric field intervening layer 204 is formed to a depth greater than 80% of the thickness of the first epitaxial layer 203, the influence of the active electric field intervening layer 204 on the surface electric field is too small to introduce an electric field peak into the body.

In this embodiment, the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent. When the second ion doping concentration is less than 0.01% of the first ion doping concentration, the requirement on the manufacturing process is high, and the realization is difficult; when the second ion doping concentration is greater than 80% of the first ion doping concentration, the active electric field intervening layer 204 has a poor effect of reducing the surface electric field.

In this embodiment, the method further includes: a plurality of mutually discrete gate structures 205 located within the first epitaxial layer 203.

In this embodiment, the gate structure 205 includes a gate oxide layer and a polysilicon gate layer stacked in sequence.

In this embodiment, the gate structure 205 is a trench gate structure.

In other embodiments, the gate structure may also be a planar gate structure.

In this embodiment, the method further includes: a source region 207 in the first epitaxial layer 203 on both sides of the gate structure 205.

In this embodiment, the method further includes: a body region 206 located within the first epitaxial layer 203.

In this embodiment, the method further includes: a dielectric layer located on the first epitaxial layer; a plurality of conductive plugs located on the first epitaxial layer; a first metal layer located on the plurality of conductive plugs.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (27)

1. A method for forming a super junction device structure is characterized by comprising the following steps:

providing a substrate;

forming a first epitaxial layer and at least one active electric field intervening layer on the substrate, wherein the active electric field intervening layer is positioned in the first epitaxial layer, first ions are arranged in the first epitaxial layer, second ions are arranged in the active electric field intervening layer, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is smaller than that of the first ions;

forming a plurality of mutually-separated super junction grooves in the first epitaxial layer and the active electric field intervening layer;

and forming a second epitaxial layer in the super junction trench, wherein third ions are arranged in the second epitaxial layer, and the conductivity type of the third ions is different from that of the first ions.

2. The method of claim 1, wherein at least one active electric field intervening layer is formed during the formation of the first epitaxial layer.

3. The method of claim 2, wherein forming the first epitaxial layer and the at least one active electric field intervening layer on the substrate comprises: forming the first epitaxial layer by adopting a first epitaxial growth process; and in the process of forming the first epitaxial layer, at least one second epitaxial process is adopted, at least one active electric field intervening layer is formed in the first epitaxial layer, and the process parameters of the second epitaxial process are different from those of the first epitaxial process.

4. The method of claim 1, wherein at least one of the active electric field intervening layers is formed after the first epitaxial layer is formed.

5. The method of forming a super junction device structure of claim 4, wherein the method of forming a first epitaxial layer and at least one active electric field intervening layer on said substrate comprises: forming the first epitaxial layer by adopting a first epitaxial growth process; after the first epitaxial layer is formed, at least one layer of active electric field intervening layer is formed in the first epitaxial layer by adopting at least one inversion ion implantation treatment.

6. The method of claim 1, wherein the thickness of the active electric field intervening layer is: 0.1 micron to 50% of the thickness of the first epitaxial layer.

7. The method of claim 1, wherein the active electric field intervening layer is formed to a depth of: 1 micron to 80% of the thickness of the first epitaxial layer.

8. The method of claim 1, wherein the second ion doping concentration is the following of the first ion doping concentration: 0.01 to 80 percent.

9. The method of forming the super-junction device structure of claim 1, wherein the method of forming the second epitaxial layer comprises: forming an initial second epitaxial layer in the super junction trench and on the first epitaxial layer by adopting a third epitaxial growth process, wherein the initial second epitaxial layer has the third ions; and carrying out planarization treatment on the initial second epitaxial layer to form a second epitaxial layer, wherein the second epitaxial layer is filled in the super junction groove.

10. The method of forming a super junction device structure of claim 1, further comprising, prior to forming the super junction trench: and forming a plurality of mutually-separated gate structures in the first epitaxial layer.

11. The method of claim 10, wherein the gate structure comprises a gate oxide layer and a polysilicon gate layer stacked in sequence.

12. The method of forming the super junction device structure of claim 11, wherein the gate structure comprises: a trench gate structure or a planar gate structure.

13. The method for forming the super junction device structure of claim 12, wherein when the gate structure is a trench gate structure, the method for forming the gate structure comprises: forming a grid groove in the first epitaxial layer; forming a gate oxide material layer on the side wall and the bottom surface of the gate trench and the first epitaxial layer; forming a polysilicon gate material layer on the gate oxide material layer; and carrying out planarization treatment on the gate oxide material layer and the polysilicon gate material layer to form the gate structure.

14. The method of forming the super junction device structure of claim 12, wherein when the gate structure is a planar gate structure, the method of forming the gate structure comprises: forming a gate oxide material layer on the first epitaxial layer; forming a polysilicon gate material layer on the gate oxide material layer; and carrying out graphical processing on the gate oxide material layer and the polysilicon gate material layer to form the gate structure.

15. The method of forming a super junction device structure of claim 10, further comprising, after forming the gate structure: and forming source regions in the first epitaxial layer at two sides of the gate structure.

16. The method of forming a super junction device structure of claim 1, further comprising, prior to forming the super junction trench: and forming a body region in the first epitaxial layer.

17. The method of forming a super junction device structure of claim 1, further comprising, after forming said second epitaxial layer: forming a dielectric layer on the first epitaxial layer; forming a plurality of conductive plugs on the first epitaxial layer; forming a first metal layer on the conductive plugs; and after the first metal layer is formed, carrying out back surface process treatment.

18. A super junction device structure, comprising:

a substrate;

a first epitaxial layer on the substrate, the first epitaxial layer having first ions therein;

at least one active electric field intervening layer positioned in the first epitaxial layer, wherein second ions are arranged in the active electric field intervening layer, the conductivity type of the first ions is the same as that of the second ions, and the doping concentration of the second ions is smaller than that of the first ions;

a plurality of mutually discrete super junction trenches located within the first epitaxial layer and the active electric field intervening layer;

and the second epitaxial layer is positioned in the super junction groove, third ions are arranged in the second epitaxial layer, and the conductivity type of the third ions is different from that of the first ions.

19. The super-junction device structure of claim 18, wherein the active electric field intervening layer has a thickness of: 0.1 micron to 50% of the thickness of the first epitaxial layer.

20. The super-junction device structure of claim 18, wherein the active electric field intervention layer is formed to a depth of: 1 micron to 80% of the thickness of the first epitaxial layer.

21. The super-junction device structure of claim 18, wherein the second ion doping concentration is at least one of: 0.01 to 80 percent.

22. The super-junction device structure of claim 18, further comprising: and the plurality of mutually-separated gate structures are positioned in the first epitaxial layer.

23. The super-junction device structure of claim 22 wherein said gate structure comprises a gate oxide layer and a polysilicon gate layer stacked in sequence.

24. The super-junction device structure of claim 22, wherein the gate structure comprises: a trench gate structure or a planar gate structure.

25. The super-junction device structure of claim 22, further comprising: and the source regions are positioned at two sides of the gate structure and in the first epitaxial layer.

26. The super-junction device structure of claim 18, further comprising: a body region within the first epitaxial layer.

27. The super-junction device structure of claim 18, further comprising: a dielectric layer located on the first epitaxial layer; a plurality of conductive plugs located on the first epitaxial layer; a first metal layer located on the plurality of conductive plugs.

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