CN115810380A

CN115810380A - PHY low-power consumption control module based on DFI

Info

Publication number: CN115810380A
Application number: CN202211178071.1A
Authority: CN
Inventors: 白祯帅; 李瑞东; 沈力; 郭鹏; 衣瑞刚
Original assignee: Shandong Sinochip Semiconductors Co Ltd
Current assignee: Shandong Sinochip Semiconductors Co Ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2023-03-17

Abstract

The invention provides a DFI-based PHY low-power-consumption control module.A circuit is connected in parallel between an MC (multi-chip) and a PHY (physical layer), and comprises a DFI signal analysis unit, a counter, a programmable control unit and an APB (advanced peripheral bus) interface control unit which are sequentially connected; the APB interface control unit is connected to the MC register through an APB bus; the DFI signal analysis unit is used for monitoring the number of read-write data between the MC and the PHY and transmitting the read-write data to the counter, and both the read data and the write data are transmitted to the counter for counting; the counting period of the counter is controlled by the programmable control unit, and the counter transmits the counting value to the programmable control unit; and the programmable control unit configures the corresponding low-power-consumption parameters in the MC according to the transmitted count values, and the configuration parameters are transmitted to the register of the MC through the APB bus. According to the invention, the PHY low-power-consumption state is dynamically adjusted according to the data transmission quantity in a certain fixed period, and the low-power-consumption mode of the DDR is realized together with the controller, so that the high-efficiency transmission of data is ensured while the energy is saved.

Description

PHY low-power consumption control module based on DFI

Technical Field

The invention relates to a DFI-based PHY low-power-consumption control module, and belongs to the technical field of memories.

Background

In many current circuit designs, reducing unnecessary energy consumption is an important optimization index, and with the increasing requirements of users and the continuous development of computers, the memory capacity and frequency of the DDR are also increasing, and with the increasing memory capacity and frequency of the DDR, the DDR also has increased power consumption, and therefore, a series of configurable interfaces are provided for users to enter different low-power consumption states for the DDR controller. But lack a module that saves power while ensuring efficient data transfer.

Disclosure of Invention

The invention aims to provide a PHY low-power-consumption control module based on a DFI, which can meet the requirement of data reading and writing to the greatest extent on the premise of reducing power consumption.

In order to achieve the purpose, the invention is realized by the following technical scheme:

a PHY low-power consumption control module based on DFI is characterized in that a circuit is connected in parallel between an MC and a PHY, and the circuit comprises a DFI signal analysis unit, a counter, a programmable control unit and an APB interface control unit which are connected in sequence; the APB interface control unit is connected to the MC register through an APB bus;

the DFI signal analysis unit is used for monitoring the quantity of read-write data DFI _ rddata and DFI _ wrdata between the MC and the PHY and transmitting the read-write data and the DFI _ wrdata to the counter, and both the read data and the write data are transmitted to the same counter for counting;

the counting period of the counter is controlled by a programmable control unit, and the counter transmits a counting value to the programmable control unit;

the programmable control unit configures corresponding low-power-consumption parameters in the MC according to the transmitted count values, and the configuration parameters are transmitted to a register of the MC through an APB bus and then transmitted to the PHY through a DFI interface to realize low-power-consumption control of the PHY; the specific control mode is as follows: when the MC enters a low power consumption state, if the data volume in the counting period is more than fifty percent of the data volume in the normal working state, the programmable control unit configures the wake-up time of less than 256 clock periods for the PHY through the APB interface; when the data volume in the counting period is less than fifty percent of the data volume in the normal working state, the programmable control unit configures the awakening time of more than 256 clock periods for the PHY through the APB interface; when the operation of reading and writing data cannot be detected in a plurality of periods, the programmable control unit controls the module except the DFI analysis unit to enter a low power consumption state, at the moment, the DFI module serves as a trigger, and once the read and write data appearing on the DFI interface is detected again, the whole module is awakened to enter a normal working mode.

Preferably, the programmable control unit comprises a clock control unit, an MCU, a user interface, and a UART serial port; the counter transmits information to an MCU in the programmable control unit, and the MCU screens out corresponding low power consumption parameters according to the data volume information transmitted by the counter: when the value transmitted by the counter is higher than fifty percent of the data volume in the normal working state, the MCU generates a wake-up time parameter which is lower than 256 clock cycles; when the value transmitted by the counter is less than fifty percent of the data quantity in the normal working state, the MCU generates a wake-up time parameter more than 256 clock cycles, and completes the mapping of the address and data from the MCU to the APB interface control unit, and transmits various low-power-consumption configuration parameters after mapping to an APB bus through the APB interface control unit and to a register of the MC through the APB bus.

Preferably, signal interaction exists between the MCU and the clock control unit, the count value of the counter in the counting period is transmitted to the clock control unit through a signal wire, and the clock control unit dynamically adjusts the running frequency of the MCU according to the size of the count value; when the value transmitted by the counter is lower than fifty percent of the data volume in the normal working state, the clock control unit can reduce the running frequency of the MCU when the count value is smaller;

preferably, the user interface is used for modifying related parameters inside the MCU; and the UART serial port is used for finishing communication with an upper computer.

The invention has the advantages that: according to the method and the device, the low power consumption state of the PHY is dynamically adjusted according to the data transmission quantity in a certain fixed period, the low power consumption mode of the DDR is jointly realized by matching with the controller (MC), and the high-efficiency transmission of data is ensured while energy is saved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a schematic view of the structure of the present invention.

FIG. 2 is a schematic diagram of a programmable control unit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

A PHY low-power consumption control module based on DFI comprises a DFI signal analysis unit, a counter (counter), a programmable control unit (controller) and an APB interface control unit (APB Block).

The low power consumption control module adds an extra circuit between the MC and the PHY, firstly, the DFI signal analysis unit can monitor the quantity of read-write data DFI _ rddata and DFI _ wrdata between the MC and the PHY and transmit the data to a counter at the rear part, the read data and the write data are transmitted to the same counter for counting, the counting period of the counter is controlled by the programmable control unit, the counter transmits the counting value to the programmable control unit, the programmable control unit configures corresponding low power consumption parameters in the MC according to the transmitted counting value, the configuration parameters are transmitted to a register of the MC through an APB bus, and then the configuration parameters are transmitted to the PHY through a DFI interface to realize the low power consumption control of the PHY: when the MC enters a low power consumption state, if the data volume in the counting period is large, the programmable control unit configures short wake-up time for the PHY through the APB interface; when the data volume in the counting period is small, the programmable control unit configures long wake-up time for the PHY through the APB interface; when the operation of reading and writing data cannot be detected in a plurality of periods, the whole low-power-consumption module except the DFI analysis unit can enter a low-power-consumption state under the operation of the programmable control unit, at the moment, the DFI module serves as a trigger, and once the read and write data appearing on the DFI interface is detected again, the whole module can be awakened to enter a normal working mode. The low power consumption mode is set for the low power consumption control module, so that the energy consumption of the whole system can be reduced to the maximum extent, and the situation that DDR enters the low power consumption mode and the low power consumption module is still active to cause no operation is avoided

The necessary energy consumption.

The programmable control unit is described in detail below: the programmable control unit comprises a clock control unit, an MCU, a user interface and a UART serial port. The counting value is transmitted to the MCU in the programmable control unit from the counter, the MCU screens out the corresponding low-power consumption parameters according to the value, then the mapping of the address and data from the MCU to the APB interface control unit is completed through internal logic processing, and various mapped low-power consumption configuration parameters are transmitted to an APB bus through the APB interface control unit and further transmitted to a register of the MC; in addition, signal interaction exists between the MCU and the clock control unit, the count value of the counter in the counting period is transmitted to the clock control unit through a signal wire, and the clock control unit dynamically adjusts the operating frequency of the MCU according to the size of the count value: when the count value is smaller, the clock control unit can reduce the running frequency of the MCU to meet the reduction of the power consumption of the whole system. In addition, the MCU also has a User interface (User interface), and a User can modify the relevant parameters inside the MCU through the User interface: and modifying specific parameters of low power consumption configuration, specific MCU clock frequencies corresponding to different count values and the like. In order to facilitate the operation, a UART serial port is additionally arranged behind the user interface, the communication with an upper computer can be completed through the serial port, and the input of MCU configuration commands and the display of the running state in the MCU can be directly completed through the serial port.

The invention is expanded according to the framework of DFI standard, and has applicability, and different DDR can adopt the configuration. And DDR low power consumption configuration parameters are dynamically managed according to the number of data read and write in a period, and the power consumption is reduced while high-efficiency transmission is achieved. The low-power-consumption control circuit also has a low-power-consumption state, so that the power consumption is prevented from being increased due to the additional addition of the low-power-consumption control circuit. The invention also adds a user interface and a UART serial port to the programmable control unit, thereby facilitating the communication with an upper computer.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A PHY low-power consumption control module based on DFI is characterized in that a circuit is connected in parallel between an MC and a PHY, and the circuit comprises a DFI signal analysis unit, a counter, a programmable control unit and an APB interface control unit which are connected in sequence; the APB interface control unit is connected to the MC register through an APB bus;

the programmable control unit configures corresponding low-power consumption parameters in the MC according to the transmitted count values, and the configuration parameters are transmitted to a register of the MC through an APB bus and then transmitted to the PHY through a DFI interface to realize low-power consumption control of the PHY; the specific control mode is as follows: when the MC enters a low power consumption state, if the data volume in the counting period is more than fifty percent of the data volume in the normal working state, the programmable control unit configures the wake-up time of less than 256 clock periods for the PHY through the APB interface; when the data volume in the counting period is less than fifty percent of the data volume in the normal working state, the programmable control unit configures the awakening time of more than 256 clock periods for the PHY through the APB interface; when the operation of reading and writing data cannot be detected in a plurality of periods, the programmable control unit controls the module except the DFI analysis unit to enter a low power consumption state, at the moment, the DFI module serves as a trigger, and once the read and write data appearing on the DFI interface is detected again, the whole module is awakened to enter a normal working mode.

2. The DFI-based PHY low-power-consumption control module according to claim 1, wherein the programmable control unit comprises a clock control unit, an MCU, a user interface, and a UART serial port; the counter transmits information to an MCU in the programmable control unit, and the MCU screens out corresponding low power consumption parameters according to the data volume information transmitted by the counter: when the value transmitted by the counter is higher than fifty percent of the data volume in the normal working state, the MCU generates a wake-up time parameter which is lower than 256 clock cycles; when the value transmitted by the counter is less than fifty percent of the data volume in the normal working state, the MCU generates an awakening time parameter more than 256 clock cycles, the mapping of the address and the data from the MCU to the APB interface control unit is completed, and various mapped low-power-consumption configuration parameters are transmitted to an APB bus through the APB interface control unit and transmitted to a register of the MC through the APB bus.

3. The PHY low-power consumption control module according to claim 2, wherein there is signal interaction between the MCU and the clock control unit, a count value of the counter in a count period is transmitted to the clock control unit through a signal line, and the clock control unit dynamically adjusts an operating frequency of the MCU according to the count value; when the value transmitted by the counter is less than fifty percent of the data amount in the normal working state, the clock control unit reduces the running frequency of the MCU.

4. The DFI-based PHY low power consumption control module according to claim 2, wherein the user interface is configured to modify related parameters inside the MCU; and the UART serial port is used for finishing communication with an upper computer.