CN115803811A - 用于存储器处理单元架构的层间通信技术 - Google Patents

用于存储器处理单元架构的层间通信技术 Download PDF

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Publication number
CN115803811A
CN115803811A CN202180042480.6A CN202180042480A CN115803811A CN 115803811 A CN115803811 A CN 115803811A CN 202180042480 A CN202180042480 A CN 202180042480A CN 115803811 A CN115803811 A CN 115803811A
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memory
regions
ilc
cores
compute
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Chinese (zh)
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J·博蒂默尔
M·施丹
C·刘
T·韦斯利
卢伟
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Mamrix
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Mamrix
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Biophysics (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • Neurology (AREA)
  • Computing Systems (AREA)
  • Human Computer Interaction (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Evolutionary Computation (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
  • Logic Circuits (AREA)
CN202180042480.6A 2020-08-31 2021-08-31 用于存储器处理单元架构的层间通信技术 Pending CN115803811A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202063072904P 2020-08-31 2020-08-31
US63/072,904 2020-08-31
PCT/US2021/048548 WO2022047422A1 (fr) 2020-08-31 2021-08-31 Techniques de communication intercouche pour architectures d'unités de traitement de mémoire

Publications (1)

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CN115803811A true CN115803811A (zh) 2023-03-14

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CN202180037882.7A Pending CN115668125A (zh) 2020-08-31 2021-08-31 存储器处理单元架构映射技术
CN202180027918.3A Pending CN115668121A (zh) 2020-08-31 2021-08-31 存储器处理单元架构和配置
CN202180042480.6A Pending CN115803811A (zh) 2020-08-31 2021-08-31 用于存储器处理单元架构的层间通信技术
CN202180037893.5A Pending CN115917515A (zh) 2020-08-31 2021-08-31 存储器处理单元核心架构

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CN202180037882.7A Pending CN115668125A (zh) 2020-08-31 2021-08-31 存储器处理单元架构映射技术
CN202180027918.3A Pending CN115668121A (zh) 2020-08-31 2021-08-31 存储器处理单元架构和配置

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US (4) US20230076473A1 (fr)
CN (4) CN115668125A (fr)
WO (4) WO2022047422A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115526302B (zh) * 2022-08-19 2023-07-25 北京应用物理与计算数学研究所 基于异构多核处理器的多层神经网络计算方法及装置
US12045309B1 (en) 2023-11-29 2024-07-23 Recogni Inc. Systems and methods for performing matrix multiplication with a plurality of processing elements
US12007937B1 (en) * 2023-11-29 2024-06-11 Recogni Inc. Multi-mode architecture for unifying matrix multiplication, 1×1 convolution and 3×3 convolution

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US6836838B1 (en) * 1998-06-29 2004-12-28 Cisco Technology, Inc. Architecture for a processor complex of an arrayed pipelined processing engine
JP4317296B2 (ja) * 1999-09-17 2009-08-19 株式会社ターボデータラボラトリー 並列コンピュータのアーキテクチャおよびこのアーキテクチャを利用した情報処理ユニット
EP1267272B1 (fr) * 2001-06-11 2011-08-17 Zoran Microelectronics Ltd. Un dispositif de mémoire spécialisé
US7743382B2 (en) * 2003-11-03 2010-06-22 Ramal Acquisition Corp. System for deadlock condition detection and correction by allowing a queue limit of a number of data tokens on the queue to increase
US7136987B2 (en) * 2004-03-30 2006-11-14 Intel Corporation Memory configuration apparatus, systems, and methods
US7251185B2 (en) * 2005-02-24 2007-07-31 International Business Machines Corporation Methods and apparatus for using memory
US7941637B2 (en) * 2008-04-15 2011-05-10 Freescale Semiconductor, Inc. Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
KR101867336B1 (ko) * 2011-07-11 2018-06-15 삼성전자주식회사 다중 프로세서를 지원하는 인터럽트 발생을 위한 장치 및 방법
US9424191B2 (en) * 2012-06-29 2016-08-23 Intel Corporation Scalable coherence for multi-core processors
US9798751B2 (en) * 2013-10-16 2017-10-24 University Of Tennessee Research Foundation Method and apparatus for constructing a neuroscience-inspired artificial neural network
US9978014B2 (en) * 2013-12-18 2018-05-22 Intel Corporation Reconfigurable processing unit
US10289604B2 (en) * 2014-08-07 2019-05-14 Wisconsin Alumni Research Foundation Memory processing core architecture
US10083722B2 (en) * 2016-06-08 2018-09-25 Samsung Electronics Co., Ltd. Memory device for performing internal process and operating method thereof
US10430706B2 (en) * 2016-12-01 2019-10-01 Via Alliance Semiconductor Co., Ltd. Processor with memory array operable as either last level cache slice or neural network unit memory
US10943652B2 (en) * 2018-05-22 2021-03-09 The Regents Of The University Of Michigan Memory processing unit
US11138497B2 (en) * 2018-07-17 2021-10-05 Macronix International Co., Ltd In-memory computing devices for neural networks
US10802883B2 (en) * 2018-08-21 2020-10-13 Intel Corporation Method, system, and device for near-memory processing with cores of a plurality of sizes
US10990524B2 (en) * 2018-10-11 2021-04-27 Powerchip Semiconductor Manufacturing Corporation Memory with processing in memory architecture and operating method thereof
CN114072778A (zh) * 2019-05-07 2022-02-18 麦姆瑞克斯公司 存储器处理单元架构

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Publication number Publication date
US20230075069A1 (en) 2023-03-09
WO2022047403A1 (fr) 2022-03-03
CN115917515A (zh) 2023-04-04
US20230061711A1 (en) 2023-03-02
WO2022047422A1 (fr) 2022-03-03
CN115668125A (zh) 2023-01-31
WO2022047423A1 (fr) 2022-03-03
US20230076473A1 (en) 2023-03-09
WO2022047390A1 (fr) 2022-03-03
CN115668121A (zh) 2023-01-31
US20230073012A1 (en) 2023-03-09

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