CN115802746A - Floating gate type split gate flash memory device and process method - Google Patents
Floating gate type split gate flash memory device and process method Download PDFInfo
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Abstract
The invention discloses a process method and a structure of a floating gate type split gate flash memory device. The process method mainly comprises the steps of forming a first polycrystalline silicon layer side wall through anisotropic etching self-alignment on the inner side of a device, forming a third side wall through anisotropic etching self-alignment, then etching part of the third side wall through isotropic etching, depositing to form a selection tube gate dielectric silicon oxide layer, forming a fourth dielectric layer side wall on the outer side of the device through anisotropic and isotropic combined method self-alignment, enabling the selection gate to wrap the upper corner of the outer side of the floating gate, and improving the erasing efficiency of the device.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a floating gate type split gate flash memory device and a process method.
Background
With the rapid popularization of electronic products, flash memory flash is rapidly popularized as the mainstream storage carrier at present, and the technology thereof is rapidly developed. The non-volatile memory (NVM) technology mainly comprises floating gate (floating gate) technology and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology from the storage medium, and mainly comprises single gate (1-Transistor), split gate (split gate), double gate (2-Transistor) and other technologies from the structure. Flash has been widely applied to various embedded electronic products such as financial IC cards, automotive electronics, etc. due to its advantages of long life, non-volatility, low price, and easy programming and erasing. The memory integration density is improved, so that the chip area is saved, and the manufacturing cost is reduced. With the development of mainstream process technology and urgent requirements of people on Flash devices, split-gate Flash based on a split-gate structure is widely concerned by people, compared with the traditional Flash, the split-gate Flash memory is used as one of Flash memories, and has high programming speed and capability of completely avoiding over-erasing, so that the split-gate Flash memory is more concerned by people in both single and embedded products, and at present, the split-gate Flash memory is widely applied to products such as personal computers, digital equipment, mobile terminals, smart cards and the like. The novel split-gate Flash like SST ESF3 is superior in reliability, no over-erasure and the like. But due to the complex device structure and the requirement on the process difficulty, great resistance is generated to the popularization of production and manufacture. Therefore, simplification and optimization of the split gate Flash process flow are always a key point, and reduction of the use of a mask is a very effective research direction on the premise of not influencing devices, so that the process can be greatly simplified and the production cost can be greatly reduced.
A conventional floating gate type split gate flash memory device is shown in fig. 1, which includes: 101-medium-high voltage P-type well formed on substrate, 102-floating gate dielectric layer silicon oxide, 103-floating gate polysilicon layer, 205-first side wall dielectric layer, 106-second side wall dielectric layer, 107-polysilicon layer of leading-out source end 109, 108-protective silicon oxide layer, 109-source end heavy doping ion implantation, 111-selective gate dielectric layer silicon oxide, 112-selective gate polysilicon, 113-Light Doped Drain (LDD) and Halo ion implantation, 114-fourth side wall dielectric layer, 115-drain end heavy doping ion implantation.
In this structure, the overlapping size of the heavily doped region 109 of the Source Line (SL) and the Floating Gate 103 (FG) (FG)L op ) Larger coupling coefficient of SL-FG can be obtained, but the overlarge overlapping area of the source end and the floating gate is not beneficial to the reduction of the flash memory unit,therefore, it is required to be reducedL op However, butL op This in turn results in a reduced coupling coefficient of the SL-FG, which reduces the programming operation speed of the device.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a process method of a floating gate type split gate flash memory device, so that the erasing efficiency is improved while the size of the device is reduced.
In order to solve the above problems, the process method of the floating gate type split gate flash memory device according to the present invention comprises:
providing a semiconductor substrate (101), and sequentially forming a floating gate dielectric layer (102), a first polycrystalline silicon layer (103) and a first silicon nitride layer (502) on the semiconductor substrate; and etching by taking the first silicon nitride layer (502) as a hard mask to form a shallow trench isolation structure, and defining a memory cell area and a peripheral logic device area of the flash memory device by using the shallow trench isolation structure.
Step two, performing ion implantation on the semiconductor substrate to form a high-voltage well region, removing a first silicon nitride layer (502) on the surface, and then sequentially depositing a first silicon oxide layer (104-1), a second silicon nitride layer (104-2) and a sacrificial silicon oxide layer (503); depositing a third silicon nitride layer (504) over the sacrificial silicon oxide layer (503); and photoetching and etching to open a memory cell area of the flash memory device, removing the third silicon nitride layer (504) in the opened window area by taking the sacrificial silicon oxide layer (503) as an etching stop layer, and then etching to remove the sacrificial silicon oxide layer (503) in the window area.
Step three, forming a second silicon oxide layer (104-3), wherein the second silicon oxide layer (104-3) covers the top surface and the side surface of the third silicon nitride layer (504) and the surface of the second silicon nitride layer (104-2) in the window area; then depositing a second polysilicon layer (105); and etching the second polysilicon layer to form a first side wall (105).
Etching to remove the ONO laminated layers (104-1, 104-2, 104-3) between the first side walls in the window area, and simultaneously etching to remove the second silicon dioxide layer (104-3) on the surface of the third silicon nitride (504); then, etching and removing the first polysilicon layer (103) in the opening, wherein because the first side wall (105) is also a polysilicon layer, part of the polysilicon layer of the first side wall (105) can be etched while the first polysilicon layer (103) is etched; and depositing and etching to form a second side wall dielectric layer and form a second side wall (106).
Fifthly, heavily doped ion implantation is carried out to form a source region (109) of the flash memory device; etching and removing the floating gate dielectric layer (102) in the window to expose the surface of the substrate and expose the top of the first side wall (105); depositing a third polysilicon layer (107) in the window region and doping; a protective silicon oxide layer (108) is formed on top of the third polysilicon layer (107).
Sixthly, removing the third silicon nitride layer (504) by wet etching, and etching the ONO lamination again in a self-alignment way by taking the second side wall (106), the second silicon dioxide layer (104-3) and the protective silicon oxide layer (108) as masks; and depositing a third silicon oxide layer, etching to form a third side wall (110), etching part of the third side wall (110) by an isotropic wet method, and depositing to form a selection tube gate dielectric layer (111), so that the selection tube gate dielectric layer (111) forms a package on the upper corner of the outer side of the floating gate (103).
And seventhly, depositing polysilicon and etching to form a selection gate (112), performing ion implantation to form LDD and Halo (113), then forming a fourth side wall dielectric layer (114), and performing source-drain heavily-doped ion implantation to form a drain region (115).
In a further improvement, in the first step, the floating gate dielectric layer (102) is an oxide layer, and the floating gate dielectric layer (102) is formed by a thermal oxidation method; the first polysilicon layer is subsequently etched to form a floating gate (103) of the flash memory device.
In a further improvement, in the third step, the second silicon dioxide layer (104-3) is formed by deposition or thermal oxidation; the second silicon oxide layer is used as a top silicon oxide layer of the ONO layer between the control gate and the floating gate.
A further improvement is that, in the fourth step, the second sidewall is self-aligned etched, and after the etching is completed, the second sidewall is attached to the sidewall of the first sidewall and the sidewall of the second silicon dioxide layer on the top of the first sidewall.
In a further improvement, in the fifth step, a CMP process is performed on the top of the third polysilicon layer (107) and oxidized to form a protective silicon oxide layer (108); the source region (109), the first side wall (105) and the third polysilicon layer (107) are directly connected in short.
In the sixth step, the third silicon oxide layer is subjected to self-aligned anisotropic dry etching to form a third side wall (110), and then a part of the third side wall (110) is subjected to isotropic wet etching.
The invention provides a floating gate type split gate flash memory device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a source region (109), an LDD region (113) and a drain region (115); the source region (109), the LDD region (113) and the drain region (115) are all positioned in the well region (101); the source region (109) is located at the center of the well region (101).
On the surface of the semiconductor substrate, a grid electrode of a storage unit and a grid electrode of a selection unit of the flash memory device are arranged right above a source region (109); the section above the source region (109) is in a left-right symmetrical structure; a third polysilicon (107) is arranged right above the source region (109), and the third polysilicon (107) is directly contacted with the source region (109); the surface of the semiconductor substrate at two sides of the third polysilicon (107) covers the floating gate dielectric layer (102); a floating gate (103) is arranged above the floating gate dielectric layer (102), and an ONO lamination layer and a first side wall (105) are sequentially arranged above the floating gate (103); the floating gate (103), the ONO laminated layer, the first side wall (105) and the third polysilicon (107) are isolated by the second side wall (106), but the top of the first side wall (105) is directly contacted with the third polysilicon (107) to form electrical connection; the first side walls (105) are made of polycrystalline silicon.
A third side wall (110) is further arranged on the floating gate (103), and the third side wall (110) is isolated from the first side wall (105) by a second silicon dioxide layer (104-3); .
The selection gate (112) of the flash memory device is positioned on the outer side of the floating gate (103) and is isolated from the semiconductor substrate by a selection gate dielectric layer (111); and the selection gate dielectric layer (111) extends upwards to realize half wrapping of the selection gate (112) so as to isolate the selection gate from the third side wall (110); the outer side of the selection gate (112) is covered by a fourth sidewall dielectric layer (114-1, 114-2).
The further improvement is that the first side wall (105), the third polysilicon (107) and the source region (109) are all in direct contact to form electrical connection; so that the source region (109) is coupled to the floating gate (103) at two sides above and below the floating gate (103); the floating gate (103) is coupled up and down to reduce the overlapping size Lop of the floating gate (103) and the source region (109), which is beneficial to reducing the device; meanwhile, the selection gate (112) wraps the upper outer corner of the floating gate (103), so that the erasing efficiency of the device is improved.
According to the process method of the floating gate type split gate flash memory device, the polycrystalline silicon layer and the medium ONO lamination layer are introduced above the floating gate of the source region, and the polycrystalline silicon layer and the source region are in short circuit connection, so that the source region is coupled to the floating gate at the upper part and the lower part of the floating gate, the Lop size can be reduced, and the device is favorably reduced. The process method mainly comprises the steps of forming a first polycrystalline silicon layer side wall through anisotropic etching self-alignment on the inner side of a device, forming a third side wall through anisotropic etching self-alignment, then etching part of the third side wall through isotropic etching, depositing to form a selection tube gate dielectric silicon oxide layer, forming a fourth dielectric layer side wall on the outer side of the device through anisotropic and isotropic combined method self-alignment, enabling the selection gate to wrap the upper corner of the outer side of the floating gate, and improving the erasing efficiency of the device.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional floating gate type split gate flash memory device.
FIGS. 2-8 are schematic diagrams of the steps of the process of the present invention.
Fig. 9 is a flowchart of a method of fabricating a floating gate type split gate flash memory device according to the present invention.
Description of the reference numerals
101-semiconductor substrate (containing formed middle-high voltage P-type well), 102-floating gate dielectric layer, 103-floating gate (polysilicon layer), 104 (104-1, 104-2, 104-3) -ONO (Oxide-Nitride-Oxide) dielectric lamination between polysilicon, 105-first side wall (second polysilicon layer), 106-second side wall dielectric layer, 107-third polysilicon layer, 108-protective silicon Oxide layer, 109-source region heavy doping ion implantation, 110-third side wall dielectric layer, 111-selective gate dielectric layer silicon Oxide, 112-selective gate (fourth polysilicon layer), 113-Light Doped Drain (LDD) and Halo ion implantation, 114 (114-1, 114-2) -fourth side wall dielectric layer, 115-drain region heavy doping ion implantation.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to further reduce the size of the floating gate type split gate flash memory device, reduce Lop without reducing the coupling coefficient between the source end SL and the floating gate FG, the invention provides that a polysilicon layer 105 and a dielectric ONO lamination layer 104 are introduced above the FG at the SL end, and the 105 and the SL are short-circuited at the same time, so that the SL is coupled to the FG at the upper surface and the lower surface of the FG. And forming the fourth dielectric layer side wall 110 on the outer side of the device in a self-alignment manner by adopting a combination method of anisotropy and isotropy, and simultaneously enabling the selection gate 112 to wrap the upper corner of the outer side of the floating gate 103, so that the erasing efficiency of the device is improved. The whole cross section presents an axial symmetry structure, and particularly referring to fig. 8, the semiconductor substrate comprises a source region (109), an LDD region (113) and a drain region (115); the source region (109), the LDD region (113) and the drain region (115) are all positioned in the well region (101); the source region (109) is located at the center of the well region (101).
On the surface of the semiconductor substrate, a grid electrode of a storage unit and a grid electrode of a selection unit of the flash memory device are arranged right above a source region (109); a third polysilicon (107) is arranged right above the source region (109), and the third polysilicon (107) is directly contacted with the source region (109); the surface of the semiconductor substrate at two sides of the third polysilicon (107) covers the floating gate dielectric layer (102); a floating gate (103) is arranged above the floating gate dielectric layer (102), and an ONO lamination layer and a first side wall (105) are sequentially arranged above the floating gate (103); the floating gate (103), the ONO laminated layer, the first side wall (105) and the third polysilicon (107) are isolated by the second side wall (106), but the first side wall (105) is made of polysilicon, and the top of the first side wall is directly contacted with the third polysilicon (107) to form electrical connection. And a third side wall (110) is also arranged on the floating gate (103), and the third side wall (110) is isolated from the first side wall (105) by a second silicon dioxide layer (104-3).
The selection gate (112) of the flash memory device is positioned on the outer side of the floating gate (103) and is isolated from the semiconductor substrate by a selection gate dielectric layer (111); and the selection gate dielectric layer (111) extends upwards to realize half wrapping of the selection gate (112) so as to isolate the selection gate from the third side wall (110); the outer side of the selection gate (112) is covered by a fourth sidewall dielectric layer (114-1, 114-2).
The process method of the floating gate type split gate flash memory device comprises the following process steps in combination with the corresponding attached figures 2-8 of each step:
step one, providing a P-type semiconductor substrate (101), and sequentially forming a floating gate dielectric layer (102), a first polysilicon layer (103) and a first silicon nitride layer (502) on the semiconductor substrate; the floating gate dielectric layer can be made of silicon oxide, and can be formed by deposition or thermal oxidation. And etching by taking the first silicon nitride layer (502) as a hard mask to form a shallow trench isolation structure (501), and defining a memory cell area and a peripheral logic device area of the flash memory device by using the shallow trench isolation structure.
And secondly, performing ion implantation on the semiconductor substrate to form a high-voltage P-type well region (also denoted by reference numeral 101), removing the first silicon nitride layer (502) on the surface, and sequentially depositing a first silicon oxide layer (104-1), a second silicon nitride layer (104-2) and a sacrificial silicon oxide layer (503) to form a structure similar to ONO. Depositing a third silicon nitride layer (504) over the sacrificial silicon oxide layer (503); and photoetching and etching the memory cell region of the flash memory device, removing the third silicon nitride layer (504) in the opened window region by taking the sacrificial silicon oxide layer (503) as an etching stop layer, and then etching and removing the sacrificial silicon oxide layer (503) in the window region.
Step three, forming a second silicon oxide layer (104-3), wherein the second silicon oxide layer (104-3) covers the top surface and the side surface of the third silicon nitride layer (504) and the surface of the second silicon nitride layer (104-2) in the window area; then depositing a second polysilicon layer; and etching the second polysilicon layer to form a first side wall (105). The second silicon oxide layer (104-3) serves as the top silicon oxide layer of the ONO stack between the control gate and the floating gate.
Etching and removing the ONO laminated layers (104-1, 104-2 and 104-3) between the first side walls (105) in the window area to expose the floating gate dielectric layer (102) in the window, and simultaneously etching the second silicon oxide layer (104-3) on the surface of the third silicon nitride (504); then, etching and removing the first polysilicon layer (103) in the opening, wherein because the first side wall (105) is also a polysilicon layer, part of the polysilicon layer of the first side wall (105) can be etched while the first polysilicon layer (103) is etched; depositing a dielectric layer and performing self-aligned etching to form a second side wall dielectric layer and a second side wall (106); the second side wall (106) is attached to the side wall of the first side wall (105) and the side wall of the second silicon dioxide layer (104-3) on the top of the first side wall.
Fifthly, heavily doped N-type ion implantation is carried out to form a source region (109) of the flash memory device; etching and removing the floating gate dielectric layer (102) in the window to expose the surface of the substrate and expose the top of the first side wall (105); depositing a third polysilicon layer (107) in the window region and doping; performing a CMP process on the top of the third polysilicon layer (107) and thermally oxidizing to form a protective silicon oxide layer (108); and after the completion, the source region (109), the first side wall (105) and the third polysilicon layer (107) are directly shorted together to form electrical connection.
Sixthly, removing the third silicon nitride layer (504) by wet etching, and etching the ONO lamination again in a self-alignment way by taking the second side wall (106), the second silicon dioxide layer (104-3) and the protective silicon oxide layer (108) as masks; and depositing a third silicon oxide layer, forming a third side wall (110) through self-aligned anisotropic dry etching, then etching part of the third side wall (110) through isotropic wet etching, and depositing a selection tube gate dielectric layer (111) so that the selection tube gate dielectric layer (111) forms a package on the upper corner of the outer side of the floating gate (103).
And step seven, depositing polysilicon and etching to form a selection gate (112), performing ion implantation to form LDD and Halo (113), then forming a fourth side wall dielectric layer (114), and performing source-drain heavily doped N-type ion implantation to form a drain region (115). The resulting device structure is shown in fig. 8.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A process method of a floating gate type split gate flash memory device is characterized in that: the process method comprises the following steps:
providing a semiconductor substrate (101), and sequentially forming a floating gate dielectric layer (102), a first polycrystalline silicon layer (103) and a first silicon nitride layer (502) on the semiconductor substrate; etching by taking the first silicon nitride layer (502) as a hard mask to form a shallow trench isolation structure, and defining a memory cell area and a peripheral logic device area of the flash memory device by utilizing the shallow trench isolation structure;
step two, performing ion implantation on the semiconductor substrate to form a high-voltage well region, removing a first silicon nitride layer (502) on the surface, and then sequentially depositing a first silicon oxide layer (104-1), a second silicon nitride layer (104-2) and a sacrificial silicon oxide layer (503); depositing a third silicon nitride layer (504) over the sacrificial silicon oxide layer (503); photoetching and etching to open a memory cell area of the flash memory device, removing a third silicon nitride layer (504) in an opened window area by taking a sacrificial silicon oxide layer (503) as an etching stop layer, and then etching to remove the sacrificial silicon oxide layer (503) in the window area;
step three, forming a second silicon oxide layer (104-3), wherein the second silicon oxide layer (104-3) covers the top surface and the side surfaces of the third silicon nitride layer (504) and the surface of the second silicon nitride layer (104-2) in the window area; then depositing a second polysilicon layer (105); etching the second polysilicon layer to form a first side wall (105);
etching to remove the ONO laminated layers (104-1, 104-2, 104-3) between the first side walls in the window area, and simultaneously etching to remove the second silicon dioxide layer (104-3) on the surface of the third silicon nitride (504); then, etching and removing the first polysilicon layer (103) in the opening, wherein because the first side wall (105) is also a polysilicon layer, part of the polysilicon layer of the first side wall (105) can be etched while the first polysilicon layer (103) is etched; depositing and etching to form a second side wall dielectric layer and a second side wall (106);
fifthly, heavily doped ion implantation is carried out to form a source region (109) of the flash memory device; etching and removing the floating gate dielectric layer (102) in the window to expose the surface of the substrate and expose the top of the first side wall (105); depositing a third polysilicon layer (107) in the window region and doping; forming a protective silicon oxide layer (108) on top of the third polysilicon layer (107);
sixthly, removing the third silicon nitride layer (504) by wet etching, and etching the ONO lamination again in a self-alignment way by taking the second side wall (106), the second silicon dioxide layer (104-3) and the protective silicon oxide layer (108) as masks; depositing a third silicon oxide layer, etching to form a third side wall (110), etching part of the third side wall (110), and depositing to form a selection tube gate dielectric layer (111), so that the selection tube gate dielectric layer (111) forms a package on the outer upper corner of the floating gate (103);
and step seven, depositing polysilicon and etching to form a selection gate (112), performing ion implantation to form LDD and Halo (113), then forming a fourth side wall dielectric layer (114), and performing source-drain heavily doped ion implantation to form a drain region (115).
2. The process of claim 1, wherein the floating gate flash memory device comprises: in the first step, the floating gate dielectric layer (102) is an oxide layer, and the floating gate dielectric layer (102) is formed by a thermal oxidation method; the first polysilicon layer is subsequently etched to form a floating gate (103) of the flash memory device.
3. The process of claim 1, wherein the floating gate type split gate flash memory device comprises: in the third step, the second silicon dioxide layer (104-3) is formed by deposition or thermal oxidation; the second silicon oxide layer is used as a top silicon oxide layer of the ONO layer between the control gate and the floating gate.
4. The process of claim 1, wherein the floating gate flash memory device comprises: in the fourth step, the second side wall is self-aligned etched, and after etching is completed, the second side wall is attached to the side wall of the first side wall and the side wall of the second silicon dioxide layer on the top of the first side wall.
5. The process of claim 1, wherein the floating gate flash memory device comprises: in the fifth step, the top of the third polysilicon layer (107) is subjected to a CMP process and oxidized to form a protective silicon oxide layer (108); and the source region (109), the first side wall (105) and the third polycrystalline silicon layer (107) are directly connected in short.
6. The process of claim 1, wherein the floating gate flash memory device comprises: and in the sixth step, the third silicon oxide layer is subjected to self-aligned anisotropic dry etching to form a third side wall (110), and then part of the third side wall (110) is etched.
7. A floating gate type split gate flash memory device is characterized in that: the flash memory device includes:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a source region (109), an LDD region (113) and a drain region (115); the source region (109), the LDD region (113) and the drain region (115) are all positioned in the well region (101); the source region (109) is positioned at the central position of the well region (101);
on the surface of the semiconductor substrate, a grid electrode of a storage unit and a grid electrode of a selection unit of the flash memory device are arranged right above a source region (109); the section above the source region (109) is in a left-right symmetrical structure; a third polysilicon (107) is arranged right above the source region (109), and the third polysilicon (107) is directly contacted with the source region (109); the surface of the semiconductor substrate at two sides of the third polysilicon (107) covers the floating gate dielectric layer (102); a floating gate (103) is arranged above the floating gate dielectric layer (102), and an ONO lamination layer and a first side wall (105) are sequentially arranged above the floating gate (103); the floating gate (103), the ONO laminated layer, the first side wall (105) and the third polysilicon (107) are isolated by the second side wall (106), but the top of the first side wall (105) is directly contacted with the third polysilicon (107) to form electrical connection; the first side wall (105) is made of polycrystalline silicon;
a third side wall (110) is further arranged on the floating gate (103), and the third side wall (110) is isolated from the first side wall (105) through a second silicon dioxide layer (104-3);
the selection gate (112) of the flash memory device is positioned on the outer side of the floating gate (103) and is isolated from the semiconductor substrate by a selection gate dielectric layer (111); and the selection gate dielectric layer (111) extends upwards to realize half-wrapping of the selection gate (112) to isolate the selection gate from the third side wall (110); the outer side of the selection gate (112) is covered by a fourth sidewall dielectric layer (114-1, 114-2).
8. The floating gate type split gate flash memory device according to claim 7, wherein: the first side wall (105), the third polycrystalline silicon (107) and the source region (109) are in direct contact to form electrical connection; so that the source region (109) is coupled to the floating gate (103) at the upper and lower sides of the floating gate (103); the floating gate (103) is coupled up and down to reduce the overlapping size Lop of the floating gate (103) and the source region (109), which is beneficial to reducing the device; meanwhile, the selection gate (112) wraps the upper outer corner of the floating gate (103), so that the erasing efficiency of the device is improved.
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