CN115801511B - Decision feedback equalization circuit - Google Patents
Decision feedback equalization circuit Download PDFInfo
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Abstract
The invention discloses a decision feedback equalization circuit. The circuit comprises a reference voltage generating module, a voltage buffering module, an adjusting network and a decision device; the reference voltage generation module is used for generating a first reference voltage Vref1; the voltage buffer module is used for isolating the reference voltage generation module and outputting a first reference voltage Vref1 to the adjustment network; the adjusting network is used for generating a second reference voltage Vref2 based on the first reference voltage Vref1 and a judgment result D-1 of the input voltage Vin before the judgment device and outputting the second reference voltage Vref2 to the judgment device; the decider is used for deciding the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result. The invention can reduce the response time of the reference voltage generated in the key time sequence path for compensating intersymbol interference, thereby solving the problem of time sequence convergence of the key time sequence path.
Description
Technical Field
The invention belongs to the technical field of feedback equalization, and particularly relates to a decision feedback equalization circuit.
Background
With the progress of high-speed interface technology, signal bandwidth is larger and larger, and the opening width of a signal eye pattern transmitted on a channel is smaller and smaller. On the other hand, the factors such as intersymbol interference introduced by attenuation of channels, signal reflection, and the like, and crosstalk between different channels are also continuously compressing the height and width of a signal eye. In a worse case, the eye diagram of the channel receiving end is not even opened. To this end, various equalization techniques (e.g., FFE/CTLE/DFE, etc.) have been proposed to improve the eye pattern. Among them, decision feedback equalizer (Decision Feedback Equalizer, DFE) is a common equalization technique for reducing intersymbol interference, and this technique is used in high-speed interface protocols such as PCIE3.0 and DDR 5. However, as the signal bandwidth increases, timing convergence of critical timing paths in a decision feedback equalizer becomes more and more difficult.
Disclosure of Invention
In order to meet the above-mentioned drawbacks or improvement needs of the prior art, the present invention provides a decision feedback equalization circuit, which can reduce the response time of the reference voltage generated in the critical timing path for compensating the intersymbol interference, so as to solve the timing convergence problem of the critical timing path.
In order to achieve the above object, according to one aspect of the present invention, there is provided a decision feedback equalization circuit, including a reference voltage generating module, a voltage buffering module, an adjusting network, and a decision device; the reference voltage generation module is used for generating a first reference voltage Vref1; the voltage buffer module is used for isolating the reference voltage generation module and outputting a first reference voltage Vref1 to the adjustment network; the adjusting network is used for generating a second reference voltage Vref2 based on the first reference voltage Vref1 and a judgment result D-1 of the input voltage Vin before the judgment device and outputting the second reference voltage Vref2 to the judgment device; the decider is used for deciding the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result.
In some embodiments, the output end of the reference voltage generating module is connected with the input end of the voltage buffering module, the output end of the voltage buffering module is connected with the first input end of the adjusting network, the output end of the adjusting network is connected with the first input end of the judging device, and the output end of the judging device is connected with the second input end of the adjusting network; the second input of the decision device is used for obtaining the input voltage Vin.
In some embodiments, the decision device comprises a comparator and a sampling module, wherein the forward input end of the comparator is used for acquiring the input voltage Vin, the reverse input end of the comparator is connected with the output end of the adjustment network, the output end of the comparator is connected with the input end of the sampling module, and the output end of the sampling module is connected with the second input end of the adjustment network; the sampling module is used for sampling and outputting the output signal of the comparator to the adjusting network under the triggering of the current clock signal.
In some embodiments, the regulation network has a first regulation factor T1, and a second reference voltage Vref2 = Vref1+ T1 (D-1).
In some embodiments, D-1 is a decision result of the sampling module on the input voltage Vin under the trigger of the clock signal before the current clock signal.
In some embodiments, the tuning network includes a resistor and a controllable current source; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the controllable current source is connected between the second end of the resistor and the ground; the current I1 of the controllable current source is regulated by D-1.
In some embodiments, the second reference voltage Vref2 = Vref1+ I1R, where R is the resistance of the resistor.
In some embodiments, the regulation network includes a voltage superposition module and a controllable voltage source; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the controllable voltage sources are respectively connected between the second input end of the voltage superposition module and the ground; the voltage V1 of the controllable voltage source is regulated by D-1.
In some embodiments, the second reference voltage Vref2 = Vref1+ V1.
In some embodiments, the decision feedback equalization circuit further comprises N sampling delay modules, wherein N is greater than or equal to 1; the N sampling delay modules are sequentially connected to the output end of the sampling module, and the N sampling delay modules are sequentially marked as a first sampling delay module to an Nth sampling delay module according to the direction from the near to the far of the sampling module; each sampling delay module is used for delaying a signal input to the sampling delay module by one clock period and outputting the signal to the adjustment network.
In some embodiments, the first to nth sampling delay modules are respectively configured to output N decision results D-2 to D- (n+1) to the adjustment network; wherein D-2 to D- (n+1) are respectively the decision results of the sampling module on the input voltage Vin under the triggering of the first two clock signals to the first n+1 clock signals of the current clock signal.
In some embodiments, the tuning network has n+1 tuning coefficients, labeled as first tuning coefficient T1, second tuning coefficient T2, through n+1th tuning coefficient T (n+1), respectively; the second reference voltage Vref 2=vref 1+t1 (D-1) +t2 (D-2) + … +t (n+1) (D- (n+1)) where D-1 is a decision result of the sampling module on the input voltage Vin under the trigger of the previous clock signal of the current clock signal.
In some embodiments, the regulation network comprises a resistor and n+1 controllable current sources; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the n+1 controllable current sources are respectively connected between the second end of the resistor and the ground; currents I1 to I (n+1) of the n+1 controllable current sources are regulated by D-1 to D- (n+1), respectively.
In some embodiments, the second reference voltage Vref2 = Vref1+ I1R + … + I (n+1) R, wherein R is the resistance of the resistor.
In some embodiments, the regulation network includes a voltage superposition module and n+1 controllable voltage sources; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the N+1 controllable voltage sources are respectively connected between the other input ends of the voltage superposition module and the ground; the voltages V1 to V (n+1) of the n+1 controllable voltage sources are regulated by D-1 to D- (n+1), respectively.
In some embodiments, the second reference voltage Vref2 = Vref1+ V1+ … + V (N + 1).
In some embodiments, the voltage buffer module includes an operational amplifier; the output end of the reference voltage generating module is connected with the forward input end of the operational amplifier, the reverse input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is connected with the first input end of the adjusting network.
In some embodiments, the reference voltage generation module is implemented with a resistive voltage divider network.
In some embodiments, the resistive divider network is an R-2R resistive network or a resistor ladder.
In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art: the voltage buffer module and the adjusting network are introduced to process the existing reference voltage and the previous judgment result to obtain a new reference voltage, the new reference voltage has shorter establishing time, can be rapidly changed along with the change of the judgment result, can solve the problem of timing convergence of a key timing path, and can be further applied to (but not limited to) a high-speed interface technology.
Drawings
Fig. 1 is a schematic diagram of a decision feedback equalizer circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a decision feedback equalizer circuit according to another embodiment of the present invention;
fig. 3 is a schematic diagram of a decision feedback equalizer circuit according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of the architecture of an adjustment network according to one embodiment of the invention;
fig. 5 is a schematic diagram of an adjusting network according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
As shown in fig. 1, the decision feedback equalization circuit of the embodiment of the invention comprises a reference voltage generating module, a voltage buffering module, an adjusting network and a decision device. The output end of the reference voltage generating module is connected with the input end of the voltage buffering module, the output end of the voltage buffering module is connected with the first input end of the adjusting network, the output end of the adjusting network is connected with the first input end of the judging device, and the output end of the judging device is connected with the second input end of the adjusting network.
The reference voltage generating module is used for generating a first reference voltage Vref1, and the voltage buffering module is used for isolating the reference voltage generating module and outputting the first reference voltage Vref1 to the adjusting network, namely, the output voltage vb=Vref 1 of the voltage buffering module. The adjusting network generates a second reference voltage Vref2 based on the first reference voltage Vref1 and a decision result D-1 of the input voltage Vin before the decision device, and the second reference voltage Vref2 is used as a decision level of the decision device on the input voltage Vin currently. The second input end of the decision device is used for acquiring the input voltage Vin, and the decision device decides the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result and outputs the decision result.
In some embodiments, the reference voltage generation module is implemented with a resistive voltage divider network. In some embodiments, the resistor divider network is an R-2R resistor network or resistor ladder (resistor ladder). The voltage buffer module is used for avoiding mutual interference between the reference voltage generating module and the adjusting network by isolating the reference voltage generating module.
In some embodiments, the regulation network has a first regulation factor T1, and a second reference voltage Vref2 = Vref1+ T1 (D-1).
In some embodiments, the regulation network generates the second reference voltage Vref2 based on the first reference voltage Vref1 and a decision result D-1 of the decision device on the input voltage Vin triggered by a clock signal (clock signal is not shown in the figure) preceding the current clock signal. And the decision device decides the input voltage Vin according to the generated second reference voltage Vref2 under the triggering of the current clock signal to obtain a decision result and outputs the decision result.
In some embodiments, it is assumed that the decision feedback equalizer circuit is in operation and the decision device outputs a high level under normal conditions. If the input voltage Vin is reduced in amplitude due to reflection, intersymbol interference and other factors, the second reference voltage Vref2 regulated and output by the regulating network is also reduced, so that the decision device can decide the reduced input voltage Vin based on the regulated second reference voltage Vref2, so that the decision device still outputs high level, the decision result is kept unchanged, and the accuracy of decision is improved.
As shown in fig. 2, the voltage buffer module includes an operational amplifier 201, and the arbiter includes a comparator 203 and a sampling module. The output end of the reference voltage generating module is connected with the positive input end of the operational amplifier 201, the negative input end of the operational amplifier 201 is connected with the output end of the operational amplifier 201, and the output end of the operational amplifier 201 is connected with the first input end of the adjusting network. The output end of the adjusting network is connected with the reverse input end of the comparator 203, the forward input end of the comparator 203 is used for obtaining the input voltage Vin, the output end of the comparator 203 is connected with the input end of the sampling module, and the output end of the sampling module is connected with the second input end of the adjusting network.
The comparator 203 outputs a high level when the input voltage Vin is greater than the second reference voltage Vref2, and outputs a low level when the input voltage Vin is less than the second reference voltage Vref2. The sampling module samples and outputs the output signal of the comparator 203 to the second input terminal of the adjusting network under the triggering of the clock signal.
As shown in fig. 3, the decision feedback equalization circuit according to the embodiment of the present invention further includes a first sampling delay module, a second sampling delay module, and a third sampling delay module. The output end of the sampling module is connected with the input end of the first sampling delay module, the output end of the first sampling delay module is connected with the third input end of the adjusting network and the input end of the second sampling delay module, the output end of the second sampling delay module is connected with the fourth input end of the adjusting network and the input end of the third sampling delay module, and the output end of the third sampling delay module is connected with the fifth input end of the adjusting network.
The first sampling delay module is used for delaying the judgment result D-1 output by the sampling module by one clock period under the triggering of the clock signal, and outputting the judgment result D-1 to the adjustment network and the second sampling delay module, wherein the signal output by the first sampling delay module is marked as D-2. The second sampling delay module is used for delaying the signal D-2 output by the first sampling delay module by one clock period under the triggering of the clock signal and outputting the delayed signal to the adjusting network and the third sampling delay module, and the signal output by the second sampling delay module is marked as D-3. The third sampling delay module is used for delaying the signal D-3 output by the second sampling delay module by one clock period under the triggering of the clock signal and outputting the delayed signal to the adjustment network, and the signal output by the third sampling delay module is marked as D-4.
In some embodiments, the adjustment network generates the second reference voltage Vref2 based on the first reference voltage Vref1, the decision result D-1 of the input voltage Vin triggered by the arbiter under the previous clock signal of the current clock signal, the decision result D-2 of the input voltage Vin triggered by the arbiter under the previous two clock signals of the current clock signal, the decision result D-3 of the input voltage Vin triggered by the arbiter under the previous three clock signals of the current clock signal, and the decision result D-4 of the input voltage Vin triggered by the arbiter under the previous four clock signals of the current clock signal.
In some embodiments, the adjusting network further has a second adjusting coefficient T2, a third adjusting coefficient T3 and a fourth adjusting coefficient T4, and the second reference voltage Vref2 = Vref1+ T1 (D-1) +t2 (D-2) +t3 (D-3) +t4 (D-4). And the decision device decides the input voltage Vin according to the generated second reference voltage Vref2 under the triggering of the current clock signal to obtain a decision result and outputs the decision result.
It should be understood that three sampling delay modules (i.e., the first sampling delay module, the second sampling delay module, and the third sampling delay module) are provided herein as examples, and the present invention may also provide only one or two sampling delay modules, which, of course, may also provide more sampling delay modules according to the actual implementation, which is not limited in this respect.
Generally, the decision feedback equalization circuit comprises N sampling delay modules, wherein N is more than or equal to 1; the N sampling delay modules are sequentially connected to the output end of the sampling module, and the N sampling delay modules are sequentially marked as a first sampling delay module to an Nth sampling delay module according to the direction from the near to the far of the sampling module; each sampling delay module is used for delaying a signal input to the sampling delay module by one clock period and outputting the signal to the adjustment network. The first sampling delay module to the Nth sampling delay module are respectively used for outputting N judgment results D-2 to D- (N+1) to the adjustment network; wherein, D-2 to D- (n+1) are respectively the decision results of the sampling module on the input voltage Vin under the triggering of the first two clock signals to the first n+1 clock signals of the current clock signal. Correspondingly, the adjusting network has n+1 adjusting coefficients, which are respectively marked as a first adjusting coefficient T1, a second adjusting coefficient T2 and an n+1th adjusting coefficient T (n+1); the second reference voltage Vref2 = Vref1+ T1 (D-1) +t2 (D-2) + … +t (n+1) (D- (n+1)).
It can be understood that the more sampling delay modules are set, the more accurate the decision result is, and the circuit cost is correspondingly increased, so that whether to set the sampling delay modules and how many sampling delay modules can be selected according to actual use needs.
Fig. 4 is a schematic diagram of the structure of an adjusting network according to an embodiment of the present invention. As shown in fig. 4, the regulation network comprises a resistor 401, a first controllable current source 403, a second controllable current source 405, a third controllable current source 407, and a fourth controllable current source 409. A first end of the resistor 401 is connected to the output end of the voltage buffer module, a second end of the resistor 401 is connected to the inverting input end of the comparator 203, and the first controllable current source 403, the second controllable current source 405, the third controllable current source 407 and the fourth controllable current source 409 are respectively connected between the second end of the resistor 401 and ground.
The current I1 of the first controllable current source 403 is adjusted by the decision device under the triggering of the previous clock signal of the current clock signal to the decision result D-1 of the input voltage Vin, the current I2 of the second controllable current source 405 is adjusted by the decision device under the triggering of the previous two clock signals of the current clock signal to the decision result D-2 of the input voltage Vin, the current I3 of the third controllable current source 407 is adjusted by the decision device under the triggering of the previous three clock signals of the current clock signal to the decision result D-3 of the input voltage Vin, and the current I4 of the fourth controllable current source 409 is adjusted by the decision device under the triggering of the previous four clock signals of the current clock signal to the decision result D-4 of the input voltage Vin.
In some embodiments, the second reference voltage Vref 2=vb+i1+r+i2+r+i3+rj4+rj, where vb=vref 1, R is the resistance of the resistor 401, the current of the first controllable current source 403 is I1, the current of the second controllable current source 405 is I2, the current of the third controllable current source 407 is I3, and the current of the fourth controllable current source 409 is I4.
In some embodiments, the number of controllable current sources corresponds to the number of decision results fed back to the adjustment network, and the current of each controllable current source is adjusted by the decision results fed back to the adjustment network.
For example, for the configuration shown in fig. 2, the regulation network may comprise only one controllable current source, the current I1 of which is regulated by D-1, the second reference voltage Vref2 = Vref1+ I1R.
Generally, for the case that the aforementioned decision feedback equalization circuit includes N sampling delay modules, the adjustment network includes n+1 controllable current sources, and the n+1 controllable current sources are respectively connected between the second end of the resistor and ground, and the currents I1 to I (n+1) of the n+1 controllable current sources are respectively adjusted by D-1 to D- (n+1). Accordingly, the second reference voltage Vref2 = Vref1+ I1R + … + I (n+1) R.
Fig. 5 is a schematic diagram of an adjusting network according to another embodiment of the present invention. As shown in fig. 5, the tuning network includes a voltage superposition module 501, a first controllable voltage source 503, a second controllable voltage source 505, a third controllable voltage source 507, and a fourth controllable voltage source 509. The first input end of the voltage superposition module 501 is connected with the output end of the voltage buffer module, the output end of the voltage superposition module 501 is connected with the reverse input end of the comparator 203, the first controllable voltage source 503 is connected between the second input end of the voltage superposition module 501 and the ground, the second controllable voltage source 505 is connected between the third input end of the voltage superposition module 501 and the ground, the third controllable voltage source 507 is connected between the fourth input end of the voltage superposition module 501 and the ground, and the fourth controllable voltage source 509 is connected between the fifth input end of the voltage superposition module 501 and the ground.
The voltage V1 of the first controllable voltage source 503 is adjusted by the decision device under the triggering of the previous clock signal of the current clock signal to the decision result D-1 of the input voltage Vin, the voltage V2 of the second controllable voltage source 505 is adjusted by the decision device under the triggering of the previous two clock signals of the current clock signal to the decision result D-2 of the input voltage Vin, the voltage V3 of the third controllable voltage source 507 is adjusted by the decision device under the triggering of the previous three clock signals of the current clock signal to the decision result D-3 of the input voltage Vin, and the voltage V4 of the fourth controllable voltage source 509 is adjusted by the decision device under the triggering of the previous four clock signals of the current clock signal to the decision result D-4 of the input voltage Vin.
In some embodiments, the second reference voltage Vref2 = Vb + V1+ V2+ V3 + V4, where Vb = Vref1, the voltage V1 = T1 of the first controllable voltage source 503 (D-1), the voltage V2 = T2 of the second controllable voltage source 505 (D-2), the voltage V3 = T3 of the third controllable voltage source 507 (D-3), and the voltage V4 = T4 of the fourth controllable voltage source 509 (D-4).
In some embodiments, the number of controllable voltage sources corresponds to the number of decision results fed back to the adjustment network, and the voltages of the controllable voltage sources are respectively adjusted by the decision results fed back to the adjustment network.
For example, for the configuration shown in fig. 2, the regulation network may comprise only one controllable voltage source, the voltage V1 of which is regulated by D-1, the second reference voltage Vref2 = Vref1+ V1.
Generally, for the case that the aforementioned decision feedback equalization circuit includes N sampling delay modules, the adjustment network includes n+1 controllable voltage sources, the n+1 controllable voltage sources are respectively connected between the other input terminals of the voltage superposition module and ground, and voltages V1 to V (n+1) of the n+1 controllable voltage sources are respectively adjusted through D-1 to D- (n+1). Accordingly, the second reference voltage Vref 2=vref 1+v1+ … +v (n+1).
Since the circuit generating the reference voltage is in the critical timing path of the decision feedback equalizer circuit, the setup time of the reference voltage becomes one of the critical design criteria of the circuit generating the reference voltage. The resistor voltage dividing network is directly utilized to generate corresponding reference voltage according to a plurality of previous judgment results, so that the balance between power consumption and voltage adjustment response time is difficult. In particular, if a fast response is required to establish a reference voltage in a short time, a small unit resistance needs to be selected, which results in a large power consumption of the circuit; if a larger unit resistor is selected to reduce the power consumption, the RC time constant of the resistor network is larger, which in turn reduces the voltage regulation response speed of the circuit. Therefore, the manner of generating the reference voltage using the resistive divider network is difficult to be directly applied to such a scenario.
The invention processes the existing reference voltage and the previous judgment result by introducing the voltage buffer module and the adjustment network to obtain the new reference voltage, wherein the new reference voltage has shorter establishment time, can be rapidly changed along with the change of the judgment result, can solve the problem of timing sequence convergence of a key timing sequence path, and can be further applied to (but not limited to) a high-speed interface technology.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Any process or method description in a flowchart or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a substantially simultaneous manner or in an opposite order from that shown or discussed, including in accordance with the functions that are involved.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods of the embodiments described above may be performed by a program that, when executed, comprises one or a combination of the steps of the method embodiments, instructs the associated hardware to perform the method.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules described above, if implemented in the form of software functional modules and sold or used as a stand-alone product, may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present application, and these should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (18)
1. The decision feedback equalization circuit is characterized by comprising a reference voltage generation module, a voltage buffer module, an adjustment network and a decision device; the reference voltage generation module is used for generating a first reference voltage Vref1; the voltage buffer module is used for isolating the reference voltage generation module and outputting a first reference voltage Vref1 to the adjustment network; the adjusting network is used for generating a second reference voltage Vref2 based on the first reference voltage Vref1 and a judgment result D-1 of the input voltage Vin before the judgment device and outputting the second reference voltage Vref2 to the judgment device; the decider is used for deciding the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result;
the decision device comprises a comparator and a sampling module, wherein the forward input end of the comparator is used for acquiring an input voltage Vin, the reverse input end of the comparator is connected with the output end of the adjusting network, the output end of the comparator is connected with the input end of the sampling module, and the output end of the sampling module is connected with the second input end of the adjusting network; the sampling module is used for sampling and outputting the output signal of the comparator to the adjustment network under the triggering of the current clock signal.
2. The decision feedback equalizer circuit of claim 1, wherein the output of the reference voltage generating module is coupled to the input of the voltage buffering module, and wherein the output of the voltage buffering module is coupled to the first input of the adjustment network.
3. The decision feedback equalizer circuit of claim 1, wherein the adjustment network has a first adjustment coefficient T1 and a second reference voltage Vref2 = Vref1+ T1 x (D-1).
4. A decision feedback equalizer circuit as claimed in claim 3, wherein D-1 represents the result of the decision of the input voltage Vin by the sampling module triggered by the clock signal preceding the current clock signal.
5. The decision feedback equalization circuit of claim 3, wherein said adjustment network comprises a resistor and a controllable current source; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the controllable current source is connected between the second end of the resistor and the ground; the current I1 of the controllable current source is regulated by D-1.
6. The decision feedback equalizer circuit of claim 5, wherein the second reference voltage Vref2 = Vref1+ I1R, wherein R represents the resistance of the resistor.
7. The decision feedback equalization circuit of claim 3, wherein said adjustment network comprises a voltage superposition module and a controllable voltage source; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the controllable voltage sources are respectively connected between the second input end of the voltage superposition module and the ground; the voltage V1 of the controllable voltage source is regulated by D-1.
8. The decision feedback equalizer circuit of claim 7, wherein the second reference voltage Vref2 = Vref1+ V1.
9. The decision feedback equalization circuit of claim 1, further comprising N sample delay modules, wherein N is greater than or equal to 1; the N sampling delay modules are sequentially connected to the output end of the sampling module, and the N sampling delay modules are sequentially marked as a first sampling delay module to an Nth sampling delay module according to the direction from the near to the far of the sampling module; each sampling delay module is used for delaying a signal input to the sampling delay module by one clock period and outputting the signal to the adjustment network.
10. The decision feedback equalization circuit of claim 9, wherein the first through nth sample delay modules are each configured to output N decision results D-2 through D- (n+1) to the adjustment network; wherein D-2 to D- (n+1) respectively represent the decision result of the sampling module on the input voltage Vin under the triggering of the first two clock signals to the first n+1 clock signals of the current clock signal.
11. The decision feedback equalizer circuit of claim 10, wherein the adjustment network has n+1 adjustment coefficients, labeled as first adjustment coefficient T1, second adjustment coefficient T2 through n+1th adjustment coefficient T (n+1), respectively; the second reference voltage Vref 2=vref 1+t1 (D-1) +t2 (D-2) + … +t (n+1) (D- (n+1)), where D-1 represents a result of the sampling module determining the input voltage Vin under the trigger of the previous clock signal of the current clock signal.
12. The decision feedback equalization circuit of claim 11, wherein the adjustment network comprises a resistor and n+1 controllable current sources; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the N+1 controllable current sources are respectively connected between the second end of the resistor and the ground; currents I1 to I (n+1) of the n+1 controllable current sources are regulated by D-1 to D- (n+1), respectively.
13. The decision feedback equalizer circuit of claim 12, wherein the second reference voltage Vref2 = Vref1+ I1 x R + … + I (n+1) x R, wherein R represents the resistance of the resistor.
14. The decision feedback equalization circuit of claim 11, wherein the adjustment network comprises a voltage superposition module and n+1 controllable voltage sources; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the N+1 controllable voltage sources are respectively connected between the other input ends of the voltage superposition module and the ground; the voltages V1 to V (n+1) of the n+1 controllable voltage sources are regulated by D-1 to D- (n+1), respectively.
15. The decision feedback equalizer circuit of claim 14, wherein the second reference voltage Vref2 = Vref1+ V1+ … + V (N + 1).
16. A decision feedback equalizer circuit as claimed in any one of claims 1 to 15, wherein the voltage buffer module comprises an operational amplifier; the output end of the reference voltage generating module is connected with the forward input end of the operational amplifier, the reverse input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is connected with the first input end of the adjusting network.
17. The decision feedback equalization circuit of claim 16, wherein the reference voltage generation module is implemented with a resistive divider network.
18. The decision feedback equalization circuit of claim 17, wherein the resistive divider network is an R-2R resistive network or a resistor ladder.
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