CN115801511A - Decision feedback equalization circuit - Google Patents
Decision feedback equalization circuit Download PDFInfo
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Abstract
The invention discloses a decision feedback equalization circuit. The circuit comprises a reference voltage generating module, a voltage buffering module, an adjusting network and a decision device; the reference voltage generating module is used for generating a first reference voltage Vref1; the voltage buffer module is used for isolating the reference voltage generation module and outputting a first reference voltage Vref1 to the adjustment network; the adjusting network is used for generating a second reference voltage Vref2 and outputting the second reference voltage Vref2 to the decision device based on the first reference voltage Vref1 and a decision result D-1 of the input voltage Vin before the decision device; the decision device is used for deciding the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result. The invention can reduce the response time of the reference voltage for compensating the intersymbol interference generated in the key time sequence path, thereby solving the time sequence convergence problem of the key time sequence path.
Description
Technical Field
The invention belongs to the technical field of feedback equalization, and particularly relates to a decision feedback equalization circuit.
Background
With the advance of high-speed interface technology, the signal bandwidth is larger and smaller, and the opening width of the signal eye pattern transmitted on the channel is smaller and smaller. On the other hand, factors such as intersymbol interference introduced by channel attenuation and signal reflection, and crosstalk between different channels are also compressing the height and width of the signal eye pattern. In worse cases, the eye pattern at the receiving end of the channel is not even open. For this reason, various equalization techniques (e.g., FFE/CTLE/DFE, etc.) have been proposed to improve the eye diagram. Among them, the DFE (Decision Feedback Equalizer) is a commonly used equalization technique for reducing inter-symbol interference, and is used in high-speed interface protocols such as PCIE3.0 and DDR 5. However, as signal bandwidth continues to increase, timing convergence of critical timing paths in decision feedback equalizers becomes increasingly difficult.
Disclosure of Invention
In view of the above-mentioned drawbacks and needs of the prior art, the present invention provides a decision feedback equalizer circuit capable of reducing the response time of a critical timing path for generating a reference voltage for compensating for inter-symbol interference, thereby solving the timing convergence problem of the critical timing path.
To achieve the above object, according to one aspect of the present invention, there is provided a decision feedback equalization circuit, including a reference voltage generation module, a voltage buffer module, an adjustment network, and a decision device; the reference voltage generating module is used for generating a first reference voltage Vref1; the voltage buffer module is used for isolating the reference voltage generation module and outputting a first reference voltage Vref1 to the adjustment network; the adjusting network is used for generating a second reference voltage Vref2 and outputting the second reference voltage Vref2 to the decision device based on the first reference voltage Vref1 and a decision result D-1 of the input voltage Vin before the decision device; the decision device is used for deciding the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result.
In some embodiments, the output terminal of the reference voltage generating module is connected to the input terminal of the voltage buffering module, the output terminal of the voltage buffering module is connected to the first input terminal of the adjusting network, the output terminal of the adjusting network is connected to the first input terminal of the decision device, and the output terminal of the decision device is connected to the second input terminal of the adjusting network; the second input terminal of the decision device is used for obtaining the input voltage Vin.
In some embodiments, the decision device includes a comparator and a sampling module, a positive input end of the comparator is used for obtaining the input voltage Vin, a negative input end of the comparator is connected to an output end of the adjusting network, an output end of the comparator is connected to an input end of the sampling module, and an output end of the sampling module is connected to a second input end of the adjusting network; the sampling module is used for sampling and outputting the output signal of the comparator to the adjusting network under the triggering of the current clock signal.
In some embodiments, the trim network has a first trim factor T1, and the second reference voltage Vref2= Vref1+ T1 × D-1.
In some embodiments, D-1 is the result of the decision of the input voltage Vin by the sampling module triggered by the previous clock signal of the current clock signal.
In some embodiments, the adjustment network comprises a resistor and a controllable current source; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the controllable current source is connected between the second end of the resistor and the ground; the current I1 of the controllable current source is regulated by D-1.
In some embodiments, the second reference voltage Vref2= Vref1+ I1 × R, where R is a resistance value of a resistor.
In some embodiments, the regulation network comprises a voltage superposition module and a controllable voltage source; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the controllable voltage source is respectively connected between the second input end of the voltage superposition module and the ground; the voltage V1 of the controllable voltage source is regulated by D-1.
In some embodiments, the second reference voltage Vref2= Vref1+ V1.
In some embodiments, the decision feedback equalizer circuit further comprises N sampling delay modules, wherein N ≧ 1; the N sampling delay modules are sequentially connected to the output end of the sampling module, and are sequentially marked as a first sampling delay module to an Nth sampling delay module according to the direction from the near to the far from the sampling module; each sampling delay module is used for delaying the signal input into the sampling delay module by one clock period and then outputting the signal to the adjusting network.
In some embodiments, the first to nth sampling delay modules are respectively configured to output N decision results D-2 to D- (N + 1) to the adjustment network; and D-2 to D- (N + 1) are judgment results of the sampling module on the input voltage Vin under the triggering of the first two clock signals to the first N +1 clock signals of the current clock signal respectively.
In some embodiments, the adjustment network has N +1 adjustment coefficients, respectively labeled as a first adjustment coefficient T1, a second adjustment coefficient T2, through an N +1 th adjustment coefficient T (N + 1); the second reference voltage Vref2= Vref1+ T1 + D-1+ T2 + D-2+ \ 8230, + T (N + 1) × D- (N + 1), where D-1 is a decision result of the sampling module on the input voltage Vin triggered by the previous clock signal of the current clock signal.
In some embodiments, the adjustment network comprises a resistor and N +1 controllable current sources; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the N +1 controllable current sources are respectively connected between the second end of the resistor and the ground; the currents I1 to I (N + 1) of the N +1 controllable current sources are regulated by D-1 to D- (N + 1), respectively.
In some embodiments, the second reference voltage Vref2= Vref1+ I1 × R + \8230, + I (N + 1) × R, where R is a resistance value of the resistor.
In some embodiments, the regulation network comprises a voltage superposition module and N +1 controllable voltage sources; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the N +1 controllable voltage sources are respectively connected between the other input ends of the voltage superposition module and the ground; the voltages V1 to V (N + 1) of the N +1 controllable voltage sources are regulated by D-1 to D- (N + 1), respectively.
In some embodiments, the second reference voltage Vref2= Vref1+ V1+ \8230, + V (N + 1).
In some embodiments, the voltage buffer module comprises an operational amplifier; the output end of the reference voltage generation module is connected with the positive input end of the operational amplifier, the reverse input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is connected with the first input end of the adjusting network.
In some embodiments, the reference voltage generation module is implemented using a resistive voltage divider network.
In some embodiments, the resistive divider network is an R-2R resistive network or a resistor ladder.
Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects: by introducing a voltage buffer module and an adjusting network, the existing reference voltage and the previous judgment result are processed to obtain a new reference voltage, the new reference voltage has shorter establishing time, can change rapidly along with the change of the judgment result, can solve the time sequence convergence problem of a key time sequence path, and can be further applied to (but not limited to) a high-speed interface technology.
Drawings
Fig. 1 is a schematic diagram of a decision feedback equalization circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a decision feedback equalization circuit according to another embodiment of the present invention;
fig. 3 is a schematic diagram of a decision feedback equalization circuit according to yet another embodiment of the present invention;
FIG. 4 is a schematic diagram of a regulating network according to one embodiment of the present invention;
fig. 5 is a schematic diagram of a structure of a tuning network according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
As shown in fig. 1, the decision feedback equalizer circuit according to the embodiment of the present invention includes a reference voltage generating module, a voltage buffering module, an adjusting network, and a decision device. The output end of the reference voltage generation module is connected with the input end of the voltage buffer module, the output end of the voltage buffer module is connected with the first input end of the adjusting network, the output end of the adjusting network is connected with the first input end of the decision device, and the output end of the decision device is connected with the second input end of the adjusting network.
The reference voltage generating module is used for generating a first reference voltage Vref1, and the voltage buffer module is used for isolating the reference voltage generating module and outputting the first reference voltage Vref1 to the adjusting network, namely, the output voltage Vb = Vref1 of the voltage buffer module. The regulation network generates a second reference voltage Vref2 based on the first reference voltage Vref1 and the previous decision result D-1 of the input voltage Vin by the decision device, and the second reference voltage Vref2 is used as the current decision level of the decision device for the input voltage Vin. And a second input end of the decision device is used for acquiring the input voltage Vin, and the decision device decides the input voltage Vin according to a second reference voltage Vref2 to obtain a decision result and output the decision result.
In some embodiments, the reference voltage generation module is implemented using a resistive voltage divider network. In some embodiments, the resistive voltage divider network is an R-2R resistive network or a resistor ladder. The voltage buffer module avoids the mutual interference of the reference voltage generation module and the adjusting network by isolating the reference voltage generation module.
In some embodiments, the trim network has a first trim factor T1, and the second reference voltage Vref2= Vref1+ T1 × D-1.
In some embodiments, the regulation network generates the second reference voltage Vref2 based on the first reference voltage Vref1 and a decision result D-1 of the input voltage Vin by the decision device triggered by a clock signal (the clock signal is not shown in the figure) previous to the current clock signal. And under the triggering of the current clock signal, the decision device decides the input voltage Vin according to the generated second reference voltage Vref2 to obtain a decision result and outputs the decision result.
In some embodiments, it is assumed that the decision feedback equalization circuit is in operation, and the decision device outputs a high level under normal conditions. If the amplitude of the input voltage Vin is reduced due to factors such as reflection and intersymbol interference, the second reference voltage Vref2 output by the adjustment network is reduced accordingly, so that the determiner can determine the reduced input voltage Vin based on the adjusted second reference voltage Vref2, the determiner can still output a high level, the determination result is kept unchanged, and the accuracy of determination is improved.
As shown in fig. 2, the voltage buffer module includes an operational amplifier 201, and the decision device includes a comparator 203 and a sampling module. The output terminal of the reference voltage generating module is connected to the positive input terminal of the operational amplifier 201, the negative input terminal of the operational amplifier 201 is connected to the output terminal of the operational amplifier 201, and the output terminal of the operational amplifier 201 is connected to the first input terminal of the adjusting network. The output end of the adjusting network is connected with the reverse input end of the comparator 203, the forward input end of the comparator 203 is used for obtaining the input voltage Vin, the output end of the comparator 203 is connected with the input end of the sampling module, and the output end of the sampling module is connected with the second input end of the adjusting network.
The comparator 203 outputs a high level when the input voltage Vin is greater than the second reference voltage Vref2, and outputs a low level when the input voltage Vin is less than the second reference voltage Vref2. The sampling module samples and outputs the output signal of the comparator 203 to the second input terminal of the adjusting network under the trigger of the clock signal.
As shown in fig. 3, the decision feedback equalizer circuit according to the embodiment of the present invention further includes a first sampling delay module, a second sampling delay module, and a third sampling delay module. The output end of the sampling module is connected with the input end of the first sampling delay module, the output end of the first sampling delay module is connected with the third input end of the adjusting network and the input end of the second sampling delay module, the output end of the second sampling delay module is connected with the fourth input end of the adjusting network and the input end of the third sampling delay module, and the output end of the third sampling delay module is connected with the fifth input end of the adjusting network.
The first sampling delay module is used for delaying the judgment result D-1 output by the sampling module for one clock period under the triggering of the clock signal and outputting the result to the adjusting network and the second sampling delay module, and the signal output by the first sampling delay module is marked as D-2. The second sampling delay module is used for delaying the signal D-2 output by the first sampling delay module for one clock period under the triggering of the clock signal and outputting the signal D-2 to the adjusting network and the third sampling delay module, and the signal output by the second sampling delay module is marked as D-3. The third sampling delay module is used for delaying the signal D-3 output by the second sampling delay module for one clock period under the trigger of the clock signal and outputting the signal to the adjusting network, and the signal output by the third sampling delay module is marked as D-4.
In some embodiments, the regulation network generates the second reference voltage Vref2 based on the first reference voltage Vref1, the decision result D-1 of the input voltage Vin by the decision device under the trigger of the previous clock signal of the current clock signal, the decision result D-2 of the input voltage Vin by the decision device under the trigger of the first two clock signals of the current clock signal, the decision result D-3 of the input voltage Vin by the decision device under the trigger of the first three clock signals of the current clock signal, and the decision result D-4 of the input voltage Vin by the decision device under the trigger of the first four clock signals of the current clock signal.
In some embodiments, the adjustment network further has a second adjustment coefficient T2, a third adjustment coefficient T3, and a fourth adjustment coefficient T4, and the second reference voltage Vref2= Vref1+ T1 + D-1+ T2 + D-2+ T3 + D-3+ T4. And under the triggering of the current clock signal, the decision device decides the input voltage Vin according to the generated second reference voltage Vref2 to obtain a decision result and outputs the decision result.
It should be understood that three sampling delay modules (i.e., the first sampling delay module, the second sampling delay module, and the third sampling delay module) are provided herein as an example, and only one or two sampling delay modules may be provided in the present invention.
Generally, a decision feedback equalization circuit comprises N sampling delay modules, wherein N is more than or equal to 1; the N sampling delay modules are sequentially connected to the output end of the sampling module, and are sequentially marked as a first sampling delay module to an Nth sampling delay module according to the direction from the near to the far from the sampling module; each sampling delay module is used for delaying the signal input into the sampling delay module by one clock period and then outputting the signal to the adjusting network. The first sampling delay module to the Nth sampling delay module are respectively used for outputting N judgment results D-2 to D- (N + 1) to an adjusting network; d-2 to D- (N + 1) are respectively judgment results of the sampling module on the input voltage Vin under the triggering of the first two clock signals to the first N +1 clock signals of the current clock signal. Correspondingly, the adjusting network has N +1 adjusting coefficients, which are respectively marked as a first adjusting coefficient T1, a second adjusting coefficient T2 to an N +1 adjusting coefficient T (N + 1); then the second reference voltage Vref2= Vref1+ T1 + D-1+ T2 + D-2+ \ 8230 + T (N + 1) _ D- (N + 1).
It can be understood that the more sampling delay modules are set, the more accurate the decision result is, and the circuit cost is correspondingly increased, so that whether to set the sampling delay modules and how many sampling delay modules are set can be selected according to actual use requirements, which is not limited by the present invention.
Fig. 4 is a schematic diagram of the structure of the adjustment network according to an embodiment of the present invention. As shown in fig. 4, the adjustment network comprises a resistor 401, a first controllable current source 403, a second controllable current source 405, a third controllable current source 407 and a fourth controllable current source 409. A first terminal of the resistor 401 is connected to the output terminal of the voltage buffer module, a second terminal of the resistor 401 is connected to the inverting input terminal of the comparator 203, and the first controllable current source 403, the second controllable current source 405, the third controllable current source 407 and the fourth controllable current source 409 are respectively connected between the second terminal of the resistor 401 and ground.
The current I1 of the first controllable current source 403 is adjusted by the decision device for the decision result D-1 of the input voltage Vin under the trigger of the previous clock signal of the current clock signal, the current I2 of the second controllable current source 405 is adjusted by the decision device for the decision result D-2 of the input voltage Vin under the trigger of the previous two clock signals of the current clock signal, the current I3 of the third controllable current source 407 is adjusted by the decision device for the decision result D-3 of the input voltage Vin under the trigger of the previous three clock signals of the current clock signal, and the current I4 of the fourth controllable current source 409 is adjusted by the decision device for the decision result D-4 of the input voltage Vin under the trigger of the previous four clock signals of the current clock signal.
In some embodiments, the second reference voltage Vref2= Vb + I1 × R + I2 × R + I3 × R + I4 × R, where Vb = Vref1, R is a resistance value of the resistor 401, the current of the first controllable current source 403 is I1, the current of the second controllable current source 405 is I2, the current of the third controllable current source 407 is I3, and the current of the fourth controllable current source 409 is I4.
In some embodiments, the number of the controllable current sources is correspondingly consistent with the number of the decision results fed back to the adjusting network, and the currents of the controllable current sources are respectively adjusted through the decision results fed back to the adjusting network.
For example, for the configuration shown in fig. 2, the adjustment network may comprise only one controllable current source, the current I1 of which is adjusted by D-1, and the second reference voltage Vref2= Vref1+ I1 × R.
Generally, in the case that the aforementioned decision feedback equalization circuit includes N sampling delay modules, the adjustment network includes N +1 controllable current sources, the N +1 controllable current sources are respectively connected between the second end of the resistor and the ground, and the currents I1 to I (N + 1) of the N +1 controllable current sources are respectively adjusted through D-1 to D- (N + 1). Accordingly, the second reference voltage Vref2= Vref1+ I1 × R + \8230, + I (N + 1) × R.
Fig. 5 is a schematic structural diagram of a tuning network according to another embodiment of the present invention. As shown in fig. 5, the adjustment network comprises a voltage superposition module 501, a first controllable voltage source 503, a second controllable voltage source 505, a third controllable voltage source 507 and a fourth controllable voltage source 509. A first input terminal of the voltage superposition module 501 is connected to an output terminal of the voltage buffer module, an output terminal of the voltage superposition module 501 is connected to an inverting input terminal of the comparator 203, the first controllable voltage source 503 is connected between a second input terminal of the voltage superposition module 501 and ground, the second controllable voltage source 505 is connected between a third input terminal of the voltage superposition module 501 and ground, the third controllable voltage source 507 is connected between a fourth input terminal of the voltage superposition module 501 and ground, and the fourth controllable voltage source 509 is connected between a fifth input terminal of the voltage superposition module 501 and ground.
The voltage V1 of the first controllable voltage source 503 is adjusted by the decision device according to the decision result D-1 of the input voltage Vin triggered by the previous clock signal of the current clock signal, the voltage V2 of the second controllable voltage source 505 is adjusted by the decision device according to the decision result D-2 of the input voltage Vin triggered by the previous two clock signals of the current clock signal, the voltage V3 of the third controllable voltage source 507 is adjusted by the decision device according to the decision result D-3 of the input voltage Vin triggered by the previous three clock signals of the current clock signal, and the voltage V4 of the fourth controllable voltage source 509 is adjusted by the decision device according to the decision result D-4 of the input voltage Vin triggered by the previous four clock signals of the current clock signal.
In some embodiments, the second reference voltage Vref2= Vb + V1+ V2+ V3 + V4, where Vb = Vref1, the voltage V1= T1 × D-1 of the first controllable voltage source 503, the voltage V2= T2 × D-2 of the second controllable voltage source 505, the voltage V3= T3 × D-3 of the third controllable voltage source 507, and the voltage V4= T4 × D-4 of the fourth controllable voltage source 509.
In some embodiments, the number of the controllable voltage sources is correspondingly consistent with the number of the decision results fed back to the adjusting network, and the voltage of each controllable voltage source is adjusted respectively through the decision results fed back to the adjusting network.
For example, for the configuration shown in fig. 2, the regulation network may comprise only one controllable voltage source, the voltage V1 of which is regulated by D-1, the second reference voltage Vref2= Vref1+ V1.
Generally, in the case that the aforementioned decision feedback equalization circuit includes N sampling delay modules, the adjustment network includes N +1 controllable voltage sources, the N +1 controllable voltage sources are respectively connected between other input terminals of the voltage superposition module and ground, and the voltages V1 to V (N + 1) of the N +1 controllable voltage sources are respectively adjusted through D-1 to D- (N + 1). Accordingly, the second reference voltage Vref2= Vref1+ V1+ \8230, + V (N + 1).
Since the circuit generating the reference voltage is in the critical timing path of the decision feedback equalization circuit, the setup time of the reference voltage becomes one of the critical design indicators of the circuit generating the reference voltage. The corresponding reference voltage is generated according to a plurality of previous judgment results by directly utilizing the resistance voltage division network, so that the balance between the power consumption and the voltage regulation response time is difficult to carry out. Specifically, if the circuit is to respond quickly to establish the reference voltage in a short time, a small unit resistance needs to be selected, which results in large power consumption of the circuit; if a larger unit resistor is selected to reduce power consumption, the RC time constant of the resistor network is larger, which in turn reduces the voltage regulation response speed of the circuit. Therefore, the method of generating the reference voltage by using the resistor voltage-dividing network is difficult to be directly applied to such a scenario.
The invention processes the existing reference voltage and the previous judgment result by introducing the voltage buffer module and the adjusting network to obtain the new reference voltage, the new reference voltage has shorter establishing time, can rapidly change along with the change of the judgment result, can solve the time sequence convergence problem of the key time sequence path, and can be further applied to (but not limited to) the high-speed interface technology.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps in the process. And the scope of the preferred embodiments of the present application includes other implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved.
The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the method of the above embodiments may be implemented by hardware that is configured to be instructed to perform the relevant steps by a program, which may be stored in a computer-readable storage medium, and which, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module may also be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (19)
1. A decision feedback equalization circuit is characterized by comprising a reference voltage generation module, a voltage buffer module, an adjustment network and a decision device; the reference voltage generation module is used for generating a first reference voltage Vref1; the voltage buffer module is used for isolating the reference voltage generation module and outputting a first reference voltage Vref1 to the regulation network; the adjusting network is used for generating a second reference voltage Vref2 and outputting the second reference voltage Vref2 to the decision device based on a first reference voltage Vref1 and a decision result D-1 of the input voltage Vin before the decision device; the decision device is used for deciding the input voltage Vin according to the second reference voltage Vref2 to obtain a decision result.
2. The decision feedback equalizer circuit according to claim 1, wherein an output terminal of the reference voltage generating module is connected to an input terminal of the voltage buffering module, an output terminal of the voltage buffering module is connected to a first input terminal of the adjusting network, an output terminal of the adjusting network is connected to a first input terminal of the decision device, and an output terminal of the decision device is connected to a second input terminal of the adjusting network; the second input end of the decision device is used for obtaining the input voltage Vin.
3. The decision feedback equalizer circuit as claimed in claim 1, wherein the decision device comprises a comparator and a sampling module, a positive input terminal of the comparator is used for obtaining the input voltage Vin, a negative input terminal of the comparator is connected to the output terminal of the adjusting network, an output terminal of the comparator is connected to the input terminal of the sampling module, and an output terminal of the sampling module is connected to the second input terminal of the adjusting network; and the sampling module is used for sampling and outputting the output signal of the comparator to the adjusting network under the triggering of the current clock signal.
4. The decision feedback equalization circuit of claim 3 wherein the scaling network has a first scaling factor T1 and a second reference voltage Vref2= Vref1+ T1 x D-1.
5. The decision feedback equalization circuit of claim 4 wherein D-1 represents the decision result of the sampling module on the input voltage Vin triggered by a clock signal previous to the current clock signal.
6. The decision feedback equalization circuit of claim 4 wherein said adjustment network comprises a resistor and a controllable current source; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the controllable current source is connected between the second end of the resistor and the ground; the current I1 of the controllable current source is regulated by D-1.
7. The decision feedback equalization circuit of claim 6 wherein a second reference voltage Vref2= Vref1+ I1 × R, wherein R represents a resistance value of the resistor.
8. The decision feedback equalization circuit of claim 4 wherein said adjustment network comprises a voltage superposition module and a controllable voltage source; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the controllable voltage source is respectively connected between the second input end of the voltage superposition module and the ground; the voltage V1 of the controllable voltage source is regulated by D-1.
9. The decision feedback equalization circuit of claim 8 wherein the second reference voltage Vref2= Vref1+ V1.
10. The decision feedback equalization circuit of claim 3 further comprising N sample delay modules, wherein N ≧ 1; the N sampling delay modules are sequentially connected to the output end of the sampling module, and the N sampling delay modules are sequentially marked as a first sampling delay module to an Nth sampling delay module from near to far; each sampling delay module is used for delaying the signal input to the sampling delay module by one clock period and then outputting the signal to the adjusting network.
11. The decision feedback equalization circuit of claim 10 wherein the first through nth sample delay modules are configured to output N decision results D-2 through D- (N + 1) respectively to the adjustment network; and D-2 to D- (N + 1) respectively represent the judgment results of the sampling module on the input voltage Vin under the triggering of the first two clock signals to the first N +1 clock signals of the current clock signal.
12. The decision feedback equalization circuit of claim 11 wherein the scaling network has N +1 scaling factors, respectively labeled as a first scaling factor T1, a second scaling factor T2 through an N +1 th scaling factor T (N + 1); and the second reference voltage Vref2= Vref1+ T1 + D-1+ T2 + D-2+ \ 8230 + T (N + 1) D- (N + 1), wherein D-1 represents the judgment result of the sampling module on the input voltage Vin triggered by the previous clock signal of the current clock signal.
13. The decision feedback equalization circuit of claim 12 wherein said adjustment network comprises a resistor and N +1 controllable current sources; the first end of the resistor is connected with the output end of the voltage buffer module, the second end of the resistor is connected with the reverse input end of the comparator, and the N +1 controllable current sources are respectively connected between the second end of the resistor and the ground; the currents I1 to I (N + 1) of the N +1 controllable current sources are regulated by D-1 to D- (N + 1), respectively.
14. The decision feedback equalizer circuit according to claim 13, wherein the second reference voltage Vref2= Vref1+ I1 + R + \8230, + I (N + 1) × R, wherein R represents a resistance value of the resistor.
15. The decision feedback equalization circuit of claim 12 wherein said adjustment network comprises a voltage superposition module and N +1 controllable voltage sources; the first input end of the voltage superposition module is connected with the output end of the voltage buffer module, the output end of the voltage superposition module is connected with the reverse input end of the comparator, and the N +1 controllable voltage sources are respectively connected between the other input ends of the voltage superposition module and the ground; the voltages V1 to V (N + 1) of the N +1 controllable voltage sources are regulated by D-1 to D- (N + 1), respectively.
16. The decision feedback equalization circuit of claim 15 wherein the second reference voltage Vref2= Vref1+ V1+ \8230, + V (N + 1).
17. The decision feedback equalization circuit according to any of claims 1-16 wherein said voltage buffer module comprises an operational amplifier; the output end of the reference voltage generation module is connected with the positive input end of the operational amplifier, the reverse input end of the operational amplifier is connected with the output end of the operational amplifier, and the output end of the operational amplifier is connected with the first input end of the adjusting network.
18. The decision feedback equalization circuit of claim 17 wherein said reference voltage generation module is implemented using a resistive divider network.
19. The decision feedback equalization circuit of claim 18 wherein said resistor divider network is an R-2R resistor network or a ladder resistor.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9231793B1 (en) * | 2014-05-19 | 2016-01-05 | Albert Vareljian | Full bridge decision feedback equalizer |
| CN114765463A (en) * | 2020-12-30 | 2022-07-19 | 晶晨半导体(上海)股份有限公司 | Receiver and data transmission system |
| WO2023284092A1 (en) * | 2021-07-12 | 2023-01-19 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9231793B1 (en) * | 2014-05-19 | 2016-01-05 | Albert Vareljian | Full bridge decision feedback equalizer |
| CN114765463A (en) * | 2020-12-30 | 2022-07-19 | 晶晨半导体(上海)股份有限公司 | Receiver and data transmission system |
| WO2023284092A1 (en) * | 2021-07-12 | 2023-01-19 | 长鑫存储技术有限公司 | Comparator and decision feedback equalization circuit |
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