CN115801002B - Decimal frequency-dividing frequency synthesizer and chip - Google Patents
Decimal frequency-dividing frequency synthesizer and chip Download PDFInfo
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- CN115801002B CN115801002B CN202310047083.9A CN202310047083A CN115801002B CN 115801002 B CN115801002 B CN 115801002B CN 202310047083 A CN202310047083 A CN 202310047083A CN 115801002 B CN115801002 B CN 115801002B
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Abstract
The invention discloses a decimal frequency synthesizer and a chip, comprising: the phase frequency detector, the charge pump, the loop filter, the oscillator, the loop frequency divider and the modulator are sequentially connected to form a phase-locked loop; the phase frequency detector comprises a first D trigger, a second D trigger and a delay driving unit; the modulator includes a first modulation unit and a second modulation unit. According to the decimal frequency synthesizer of the embodiment of the invention, the first digital signal is output by the first modulation unit based on the decimal frequency dividing signal, the delay coefficient is output by the second modulation unit based on the first digital signal and the decimal frequency dividing signal, the first reset signal which has a phase difference and is used for resetting the first D trigger and the second reset signal which is used for resetting the second D trigger are generated by the delay driving unit based on the charging signal, the discharging signal and the delay coefficient, and therefore spurious (spurs) in phase noise output by the frequency synthesizer caused by dynamic frequency dividing controlled by the first modulation unit are eliminated.
Description
Technical Field
The invention relates to the technical field of high-speed simulation and radio frequency chip design, in particular to a decimal frequency division frequency synthesizer and a chip.
Background
The output frequency precision of the integer frequency divider is consistent with the frequency of the reference clock, and the output frequency of any resolution (resolution) can be realized by adopting the fractional frequency divider. Therefore, the latter has been widely used in the design of various wired and wireless communication chips, and very large-scale digital chips. Fig. 1 is the most advanced and most commonly used fractional division frequency synthesizer that uses a digital modulator (SDM) to dynamically control the loop division ratio of the frequency synthesizer, again an integer for each transient, with the average value equal to the desired fractional division ratio.
The significant cause of spurious (spurs) in the digital output spectrum of the digital modulator SDM in the structure of a conventional fractional frequency synthesizer is due to the fact that the input to the digital modulator SDM that controls the dynamic frequency division number is a static (or direct current) fraction. In particular, when the input value of the digital modulator SDM is very close to 0 or 1, or equal to a fractional value of 0.25, 0.5, 0.75, etc., the periodicity of the digital output is too strong and the randomness is insufficient.
While the design technique of sigma-delta frac-N FS (sigma-delta fractional frequency synthesizer) has been relatively mature, complex digital modulator SDM designs are required in order to reduce spurs in the output phase noise caused by the digital modulator SDM. Such as increasing the length of the digital bits, using higher order structures (typically 3 or 4 orders), employing low distortion structures that reduce output delay, using complex scrambling techniques, etc. These complex digital modulator SDM design techniques significantly increase the area and power consumption of the chip, reduce the maximum operational frequency of the digital modulator SDM, and generally do not guarantee that the spurs of the frequency synthesizer output are low enough at each fractional division ratio to meet certain high performance requirements.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a fractional frequency synthesizer and a chip, which can eliminate spurious in output phase noise and have a simple structure.
To achieve the above object, an embodiment of the present invention provides a fractional division frequency synthesizer including: the phase frequency detector, the charge pump, the loop filter, the oscillator, the loop frequency divider and the modulator are sequentially connected to form a phase-locked loop;
the phase frequency detector comprises a first D trigger, a second D trigger and a delay driving unit, wherein the first D trigger and the second D trigger generate a charging signal and a discharging signal with phase difference based on a reference clock signal and a frequency division signal output by a loop frequency divider;
the modulator comprises a first modulation unit and a second modulation unit, wherein the first modulation unit outputs a first digital signal based on a fractional frequency division signal of a fractional frequency division ratio signal, and the second modulation unit outputs a delay coefficient based on the first digital signal and the fractional frequency division signal of the fractional frequency division ratio signal;
the delay driving unit is used for generating a first reset signal with a phase difference for resetting the first D trigger and a second reset signal for resetting the second D trigger based on the charging signal, the discharging signal and the delay coefficient.
In one or more embodiments of the invention, the output of the oscillator is connected to a delay drive unit.
In one or more embodiments of the present invention, the first modulation unit includes a first noise shaping modulator having an input for receiving a fractional frequency division signal of the fractional frequency division ratio signal, an output for outputting a first digital signal, a first input for receiving the first digital signal, and a second input for receiving an integer frequency division signal of the fractional frequency division ratio signal, and a first adder having an output for outputting a dynamic frequency division number based on a sum of the first digital signal and the integer frequency division signal of the fractional frequency division ratio signal.
In one or more embodiments of the invention, the first noise shaping modulator includes a first accumulation quantizer, a second accumulation quantizer, a first D flip-flop, a second D flip-flop, a third D flip-flop, and a second adder;
the first input end of the first accumulation quantizer is used for receiving a decimal frequency division signal of a decimal frequency division ratio signal, the output end of the first accumulation quantizer is connected with the input end of the first D trigger, the output end of the first D trigger is connected with the second input end of the first accumulation quantizer and the first input end of the second accumulation quantizer, the output end of the second accumulation quantizer is connected with the input end of the second D trigger, the output end of the second D trigger is connected with the second input end of the second accumulation quantizer, the carry output end of the first accumulation quantizer is connected with the first input end of the second adder, the carry output end of the second accumulation quantizer is connected with the input end of the third D trigger and the second input end of the second adder, the output end of the third D trigger is connected with the third input end of the second adder, and the output end of the second adder is used for outputting a first digital signal.
In one or more embodiments of the present invention, the second modulation unit includes a third adder, an accumulator, and a second noise shaping modulator, where a first input terminal of the third adder is configured to receive the first digital signal, a second input terminal of the third adder is configured to receive a fractional frequency signal of the fractional frequency signal, an input terminal of the accumulator is connected to an output terminal of the third adder, an input terminal of the second noise shaping modulator is connected to an output terminal of the accumulator, and an output terminal of the second noise shaping modulator is configured to output a delay coefficient.
In one or more embodiments of the invention, the second noise shaping modulator includes a third accumulation quantizer, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, and a fourth adder;
the first input end of the third accumulation quantizer is connected with the output end of the accumulator, the output end of the third accumulation quantizer is connected with the input end of the fourth D trigger and the first input end of the fourth accumulation quantizer, the output end of the fourth D trigger is connected with the second input end of the third accumulation quantizer, the output end of the fourth accumulation quantizer is connected with the input end of the fifth D trigger, the output end of the fifth D trigger is connected with the second input end of the fourth accumulation quantizer, the carry output end of the third accumulation quantizer is connected with the first input end of the fourth adder, the carry output end of the fourth accumulation quantizer is connected with the second input end of the fourth adder and the input end of the sixth D trigger, the output end of the sixth D trigger is connected with the third input end of the fourth adder, and the output end of the fourth adder is used for outputting a delay coefficient.
In one or more embodiments of the present invention, the phase frequency detector further includes a logic gate, a first input terminal of the logic gate is connected to the Q output terminal of the first D flip-flop, a second input terminal of the logic gate is connected to the Q output terminal of the second D flip-flop, and an output terminal of the logic gate is connected to the delay driving unit.
In one or more embodiments of the present invention, the loop divider includes a programmable divider and a prescaler, an input of the prescaler is connected to an output of the oscillator, an input of the programmable divider is connected to an output of the prescaler, an output of the programmable divider is connected to a phase frequency detector, and the programmable divider and the prescaler simultaneously form a feedback connection.
In one or more embodiments of the invention, the delay drive unit is a programmable delay drive unit.
The invention also discloses a chip comprising the decimal frequency dividing frequency synthesizer.
Compared with the prior art, according to the fractional frequency synthesizer and the chip of the embodiment of the invention, the first digital signal is output by the first modulation unit based on the fractional frequency signal of the fractional frequency ratio signal, the delay coefficient is output by the second modulation unit based on the fractional frequency signal of the first digital signal and the fractional frequency ratio signal, the first reset signal with phase difference for resetting the first D trigger and the second reset signal for resetting the second D trigger are generated by the delay driving unit based on the charging signal, the discharging signal and the delay coefficient, and therefore spurious (spurs) in phase noise output by the frequency synthesizer caused by dynamic frequency division controlled by the first modulation unit is eliminated.
The fractional frequency signal of the input of the first modulation unit without spurious generation in the present invention covers all the fractional numbers between 0 and 1, including the fractional numbers very close to 0 or 1, and the fractional numbers equal to the special values of 0.25, 0.5, 0.75, etc. The invention can reduce the order of the first modulation unit from the traditional 3 or 4 order to 2 order. The invention can simplify the structure of the first modulation unit, such as the simplest MASH1-1 structure. The invention can reduce the digital bit length of the first modulation unit, and the length of the first modulation unit generally meets the frequency resolution (resolution) required by the frequency synthesizer, and the length of the first modulation unit does not need 18 bits or even 24 bits. The invention can eliminate the need of a feedforward modulation unit without delay, improves the maximum speed of working, and enables the chip design to be compatible with the chip processing technology with low speed and low cost. The invention can simplify the scrambling design scheme of the first modulation unit. The invention can avoid the need to use a higher order loop filter because the order of the first modulation unit is too high.
Meanwhile, the second modulation unit added in the invention only needs to adopt the simplest 2-order MASH1-1 structure, so compared with the traditional single and complex modulator, the invention does not remarkably increase, and even saves the area and the power consumption of a digital circuit related to the modulator.
Drawings
Fig. 1 is a schematic circuit diagram of a fractional frequency synthesizer according to the present invention.
Fig. 2 is a schematic circuit diagram of a prior art phase frequency detector.
Fig. 3 is a diagram of signal waveforms of a prior art phase frequency detector.
Fig. 4 is a schematic circuit diagram of a phase frequency detector according to the present invention.
Fig. 5 is a timing diagram of the input and output signals of the phase frequency detector according to the present invention.
Fig. 6 is a circuit schematic of a modulator according to the present invention.
Fig. 7 is a circuit schematic of a first noise shaping modulator according to the invention.
Fig. 8 is a circuit schematic of a second noise shaping modulator according to the invention.
Fig. 9 is a phase difference distribution diagram of a phase frequency detector output according to a conventional fractional frequency synthesizer.
Fig. 10 is a spectrum of spurious contained phase differences from the phase frequency detector output of a conventional fractional frequency synthesizer.
Fig. 11 is a phase difference distribution diagram of the phase frequency detector output of the fractional frequency synthesizer according to the present invention.
Fig. 12 is a spectrum of the phase difference spur free of the phase difference output of the phase frequency detector of the fractional frequency synthesizer according to the present invention.
Description of the embodiments
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
As shown in fig. 1, a fractional frequency synthesizer includes: the phase frequency detector PFD, the charge pump CP, the loop filter LF, the oscillator VCO and the loop divider LD, and the modulator SDM (SDM) are connected in this order to form a phase locked loop.
The phase frequency detector PFD is configured to generate a charge signal UP and a discharge signal DN having a phase difference based on the reference clock signal Fref and the frequency-divided signal Fdiv output from the loop divider LD. The charge pump CP is used to generate a bias current based on control of the charge signal UP and the discharge signal DN. The loop filter LF is configured to generate a voltage signal based on the bias current, the oscillator VCO is configured to generate a clock signal Fvco based on the voltage signal, and the loop divider LD is configured to divide the clock signal Fvco based on the dynamic division number to generate a divided signal Fdiv. Modulator SDM is used to generate, dynamically control, dynamic frequency division numbers.
The loop divider LD includes a programmable divider Prd (Programmable divider) and a prescaler Pre (Prescaler), among other things. The input end of the prescaler Pre is connected with the output end of the oscillator VCO to receive the clock signal Fvco, the input end of the programmable divider Prd is connected with the output end of the prescaler Pre, the output end of the programmable divider Prd is connected with the second input end of the phase frequency detector PFD, the first input end of the phase frequency detector PFD is used for receiving the reference clock signal Fref, and the programmable divider Prd and the prescaler Pre form feedback connection at the same time.
As shown in fig. 4, the phase frequency detector PFD includes a first D flip-flop DFF1, a second D flip-flop DFF2, a delay drive unit RST, and a logic gate. In this embodiment, the delay driving unit RST is a programmable delay driving unit. The first D flip-flop DFF1 and the second D flip-flop DFF2 generate the charge signal UP and the discharge signal DN having a phase difference based on the reference clock signal Fref and the frequency-divided signal Fdiv output from the loop divider LD. The delay driving unit RST is used for generating a first reset signal RST1 with a phase difference for resetting the first D flip-flop DFF1 and a second reset signal RST2 for resetting the second D flip-flop DFF2 based on the charge signal UP and the discharge signal DN.
The clock input terminal CK of the first D flip-flop DFF1 is configured to receive the reference clock signal Fref, the D input terminal of the first D flip-flop DFF1 is connected to the power supply voltage, the reset terminal rst of the first D flip-flop DFF1 is configured to receive the first reset signal rst1, and the Q output terminal of the first D flip-flop DFF1 is configured to output the charging signal UP. The clock input terminal CK of the second D flip-flop DFF2 is configured to receive the frequency division signal Fdiv, the D input terminal of the second D flip-flop DFF2 is connected to the power supply voltage, the reset terminal rest of the second D flip-flop DFF2 is configured to receive the second reset signal rst2, and the Q output terminal of the second D flip-flop DFF2 is configured to output the discharge signal DN.
The first input end RST0 of the delay driving unit RST is connected with the output end of the logic gate, the second input end of the delay driving unit RST is connected with the output end of the oscillator VCO, the third input end of the delay driving unit RST is used for receiving the delay coefficient data, the first output end RST10 of the delay driving unit RST is used for outputting a first reset signal RST1, the second output end RST20 of the delay driving unit RST is used for outputting a second reset signal RST2, the first reset signal RST1 is used for controlling the delay reset of the first D trigger DFF1, and the second reset signal RST2 is used for controlling the delay reset of the second D trigger DFF 2.
As shown in fig. 5, there is a certain phase difference between the first reset signal rst1 and the second reset signal rst2, that is, the first reset signal rst1 is turned to high level and the second reset signal rst2 is turned to high level in an asynchronous state (forming a time difference), the phase difference is equal to the delay coefficient data for the oscillation period of the oscillator VCO, the oscillation period of the oscillator VCO is tvco=1/Fvco, and the phase difference is data. As can be seen from fig. 5, when data=2 (positive number), the first reset signal rst1 leads the second reset signal rst2, the phase difference between the first reset signal rst1 and the second reset signal rst2 is 2×tvco, and at this time, the pulse width of the discharge signal DN is extended by 2×tvco. When data= -1 (negative number), the second reset signal rst2 leads the first reset signal rst1, the phase difference between the second reset signal rst2 and the first reset signal rst1 is 1×tvco, and at this time, the pulse width of the charging signal UP is extended by 1×tvco.
As shown in fig. 4, the logic gate is a NAND gate, a first input terminal of the NAND gate is connected to the Q output terminal of the first D flip-flop DFF1, and a second input terminal of the NAND gate is connected to the Q output terminal of the second D flip-flop DFF 2.
The NAND gate NAND generates a base signal based on the charge signal UP and the discharge signal DN, and the delay driving unit RST generates a first reset signal RST1 and a second reset signal RST2 with the base signal as an input signal, and a phase difference (delay) between the first reset signal RST1 and the second reset signal RST2 is mainly determined by the delay coefficient data when the oscillation period Tvco of the oscillator VCO is fixed.
In the present embodiment, the modulator SDM is configured to output a dynamic frequency division number to the loop divider LD based on the fractional frequency division ratio signal. In addition, the modulator SDM is also configured to output the delay coefficient data to the delay driving unit RST based on the fractional frequency division ratio signal. The fractional frequency division ratio signal is composed of a fractional frequency division signal f and an integer frequency division signal N. The modulator SDM outputs a dynamic frequency division number to the loop divider LD based on the fractional frequency division signal f and the integer frequency division signal N. The modulator SDM outputs the delay coefficient data to the delay drive unit RST based on the fractional frequency signal f. The fractional frequency signal f covers all fractional numbers between 0 and 1, including fractional numbers very close to 0 or 1, and equal to special values of 0.25, 0.5, 0.75, etc.
In this embodiment, the modulator SDM is configured to generate and dynamically control the dynamic frequency division number of the programmable divider Prd and/or the prescaler Pre, and preferably the programmable divider Prd is controlled by the modulator SDM generating the controllable dynamic frequency division number.
As shown in fig. 6, the modulator SDM includes a first modulation unit 21 and a second modulation unit 22. The first modulation unit 21 outputs the first digital signal y1 based on the fractional frequency signal f of the fractional frequency signal, and the second modulation unit 22 outputs the delay coefficient data based on the first digital signal and the fractional frequency signal f of the fractional frequency signal.
Wherein the first modulation unit 21 comprises a first noise shaping modulator 211 and a first adder 212. In the present embodiment, the first noise shaping modulator 211 adopts a MASH1-1d structure with a delay function; in other embodiments, the first noise shaping modulator 211 may be a noise shaping modulator of other configurations. An input of the first noise shaping modulator 211 is arranged to receive the fractional frequency signal f of the fractional frequency signal and an output of the first noise shaping modulator 211 is arranged to output the first digital signal y1. A first input of the first adder 212 is configured to receive the first digital signal y1, a second input of the first adder 212 is configured to receive the integer divide signal N of the fractional divide ratio signal, and an output of the first adder 212 outputs a dynamic divide number based on summing the first digital signal y1 with the integer divide signal N of the fractional divide ratio signal.
In this embodiment, the average value of the first digital signal y1 is equal to the fractional frequency division signal f, the value of the first digital signal y1 output by the first noise shaping modulator 211 is-1, 0, 1 or 2, and the addition of the first digital signal y1 and the integer frequency division signal N is the transient loop integer frequency division number.
As shown in fig. 7, the first noise shaping modulator 211 includes a first accumulation quantizer 2111, a second accumulation quantizer 2112, a first D flip-flop 2113, a second D flip-flop 2114, a third D flip-flop 2115, and a second adder 2116. The transfer function of the first D flip-flop 2113, the second D flip-flop 2114, and the third D flip-flop 2115 in the z-domain is z-1.
The first input terminal of the first accumulation quantizer 2111 is configured to receive the fractional frequency signal f of the fractional frequency signal, the output terminal S1 of the first accumulation quantizer 2111 is connected with the input terminal of the first D flip-flop 2113, and the output terminal of the first D flip-flop 2113 is connected with the second input terminal of the first accumulation quantizer 2111 and the first input terminal of the second accumulation quantizer 2112. The output S2 of the second accumulation quantizer 2112 is connected with an input of a second D flip-flop 2114, and the output of the second D flip-flop 2114 is connected with a second input of the second accumulation quantizer 2112.
The carry output C1 of the first accumulation quantizer 2111 is connected to a first input of the second adder 2116, the carry output C2 of the second accumulation quantizer 2112 is connected to an input of the third D flip-flop 2115 and to a second input of the second adder 2116, an output of the third D flip-flop 2115 is connected to a third input of the second adder 2116, and an output of the second adder 2116 is adapted to output the first digital signal y1.
In this embodiment, the value of the fractional frequency division signal f is between 0 and 1, and the value output by the carry output terminal C1 of the first accumulation quantizer 2111 and the carry output terminal C2 of the second accumulation quantizer 2112 is 0 or 1.
As shown in fig. 6, the second modulation unit 22 includes a third adder 221, an accumulator 222, and a second noise shaping modulator 223. In the present embodiment, the second noise shaping modulator 223 adopts a MASH1-1 structure; in other embodiments, the second noise shaping modulator 223 may be a noise shaping modulator of other configurations. A first input of the third adder 221 is configured to receive the first digital signal y1, a second input of the third adder 221 is configured to receive the fractional frequency signal f of the fractional frequency ratio signal, an input of the accumulator 222 is connected to an output of the third adder 221, an input of the second noise shaping modulator 223 is connected to an output x of the accumulator 222, and an output of the second noise shaping modulator 223 is configured to output the delay coefficient data.
In this embodiment, the third adder 221 subtracts the first digital signal y1 from the fractional frequency-dividing signal f, and sends the transient difference signal (frequency-dividing error) generated by the subtraction to the accumulator 222, and the accumulator 222 adds the transient difference signal (frequency-dividing error) to obtain the transient phase difference at the output end of the phase frequency detector PFD, which is numerically normalized to the oscillation period Tvco of the oscillator VCO. The phase difference output from the accumulator 222 is high-pass noise-shaped by the second noise-shaping modulator 223 to quantize the integer output delay coefficient data. In this embodiment, the delay coefficient data has a value of-2, -1, 0, 1, or 2.
In the present embodiment, the reset delays of the charge signal UP and the discharge signal DN are dynamically changed by the delay coefficient data, thereby increasing the randomness of the phase difference of the charge signal UP and the discharge signal DN, which is seen from the output terminal of the phase frequency detector PFD, caused by the first modulation unit 21, and having a more desirable high-pass noise shaping characteristic. The difference signal of the first digital signal y1 subtracted from the fractional frequency signal f corresponds to the transient analog phase difference seen from the input of the phase frequency detector PFD caused by the first modulation unit 21. Since the difference signal of the first digital signal y1 subtracted from the fractional frequency signal f is no longer a static value, spurious emissions (spurs) in the phase difference spectrum of the output of the phase frequency detector PFD are easily eliminated.
As shown in fig. 8, the second noise shaping modulator 223 includes a third accumulation quantizer 2231, a fourth accumulation quantizer 2232, a fourth D flip-flop 2233, a fifth D flip-flop 2234, a sixth D flip-flop 2235, and a fourth adder 2236. The transfer functions of the fourth D flip-flop 2233, the fifth D flip-flop 2234, and the sixth D flip-flop 2235 in the discrete-time z domain are time delayed in units, i.e., the z-1 blocks in FIGS. 7 and 8.
The first input of the third accumulation quantizer 2231 is coupled to the output x of the accumulator 222, the output W1 of the third accumulation quantizer 2231 is coupled to the input of the fourth D flip-flop 2233 and to the first input of the fourth accumulation quantizer 2232, and the output of the fourth D flip-flop 2233 is coupled to the second input of the third accumulation quantizer 2231.
The output terminal of the fourth accumulation quantizer 2232 is connected with the input terminal of the fifth D flip-flop 2234, the output terminal of the fifth D flip-flop 2234 is connected with the second input terminal of the fourth accumulation quantizer 2232, the carry output terminal Q1 of the third accumulation quantizer 2231 is connected with the first input terminal of the fourth adder 2236, the carry output terminal Q2 of the fourth accumulation quantizer 2232 is connected with the second input terminal of the fourth adder 2236 and the input terminal of the sixth D flip-flop 2235, the output terminal of the sixth D flip-flop 2235 is connected with the third input terminal of the fourth adder 2236, and the output terminal of the fourth adder 2236 is used for outputting the delay coefficient data.
In the present embodiment, the value output by the output terminal x of the accumulator 222 is between-1 and-1, the third accumulation quantizer 2231 and the fourth accumulation quantizer 2232 are used as rounding quantizers at the same time, and the value output by the carry output terminal Q1 of the third accumulation quantizer 2231 and the value output by the carry output terminal Q2 of the fourth accumulation quantizer 2232 are all-1, 0 or 1.
The invention also discloses a chip comprising the decimal frequency dividing frequency synthesizer.
Fig. 2 shows a conventional phase frequency detector PFD structure; fig. 3 is a timing chart of the input reference clock signal Fref, the frequency-divided signal Fdiv and the reset signal rst' and the output charge signal UP and discharge signal DN of the conventional phase frequency detector PFD.
When the rising edge of the input reference clock signal Fref leads the rising edge of the frequency division signal Fdiv output by the loop frequency divider LD, the charging signal UP of the output control charge pump CP jumps to a high level along with the rising edge of the reference clock signal Fref; then, when the rising edge of the frequency division signal Fdiv comes, the discharge signal DN for controlling the charge pump CP is outputted to become high; after a certain delay (for example, about 1 nanosecond), the reset signals rst of the first D flip-flop DFF1 and the second D flip-flop DFF2 become high, so that the charging signal UP and the discharging signal DN output by the phase frequency detector PFD become low at the same time.
Fig. 9 shows a probability distribution diagram of the transient phase difference caused by the modulator SDM, seen from the output of the phase frequency detector PFD, in a conventional fractional frequency synthesizer. In this simulation, the structure of the noise shaping modulator employed in the modulator is a third order MASH1-1-1, without using a complex scrambling scheme. The simulation result shows that the modulator SDM causes phase differences between (-2 to +2) Tvco, and probability distribution is disordered without obvious rules.
Fig. 10 shows the phase difference spectrum seen from the output of the phase frequency detector PFD in the conventional fractional frequency synthesizer. As can be seen from fig. 10, the phase difference spectrum approximately corresponds to the second order high pass noise shaping, i.e. the 40dB per 10 frequency doubling characteristic. But the spurious emissions (spurs) that are evident in the spectrum are very large and spread over all frequency ranges and thus do not meet the requirements of most practical applications.
Fig. 11 shows the probability distribution of the transient phase difference caused by the modulator SDM seen from the output of the phase frequency detector PFD in the fractional frequency synthesizer of the invention. In this simulation, the noise shaping modulator of the modulation unit controlling the dynamic frequency division number adopts the structure of MASH1-1d. The noise shaping modulator of the modulating unit controlling the reset signal reset by the charge signal UP and the discharge signal DN output by the phase frequency detector PFD adopts a structure of MASH1-1. Neither modulation unit uses a complex scrambling (difying) scheme. The simulation results show that the phase difference caused by fractional frequency division of the modulator SDM is between (-2 to +2) Tvco, and the probability of the phase difference is very close to the ideal normal distribution.
Fig. 12 shows the phase difference spectrum seen from the output of the phase frequency detector PFD in the fractional frequency synthesizer of the invention. As can be seen from fig. 12, the phase difference spectrum is more consistent with ideal second order high-pass noise shaping, the most important difference being that the spectrum is very clean and almost no spurs (spurs) are visible.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A fractional frequency synthesizer, comprising: the phase frequency detector, the charge pump, the loop filter, the oscillator, the loop frequency divider and the modulator are sequentially connected to form a phase-locked loop;
the phase frequency detector comprises a first D trigger, a second D trigger and a delay driving unit, wherein the first D trigger and the second D trigger generate a charging signal and a discharging signal with phase difference based on a reference clock signal and a frequency division signal output by a loop frequency divider;
the modulator comprises a first modulation unit and a second modulation unit, wherein the first modulation unit outputs a first digital signal based on a fractional frequency division signal of a fractional frequency division ratio signal, and the second modulation unit outputs a delay coefficient based on the first digital signal and the fractional frequency division signal of the fractional frequency division ratio signal;
the delay driving unit is used for generating a first reset signal with a phase difference for resetting the first D trigger and a second reset signal for resetting the second D trigger based on the charging signal, the discharging signal and the delay coefficient.
2. The fractional frequency synthesizer of claim 1 wherein the output of the oscillator is connected to a delay drive unit.
3. The fractional frequency synthesizer of claim 1, wherein the first modulation unit comprises a first noise shaping modulator and a first adder, an input of the first noise shaping modulator is configured to receive the fractional frequency signal of the fractional frequency signal, an output of the first noise shaping modulator is configured to output a first digital signal, a first input of the first adder is configured to receive the first digital signal, a second input of the first adder is configured to receive the integer frequency signal of the fractional frequency signal, and an output of the first adder is configured to output a dynamic frequency division number based on a sum of the first digital signal and the integer frequency signal of the fractional frequency signal.
4. The fractional frequency synthesizer of claim 3, wherein the first noise shaping modulator comprises a first accumulation quantizer, a second accumulation quantizer, a first D flip-flop, a second D flip-flop, a third D flip-flop, and a second adder;
the first input end of the first accumulation quantizer is used for receiving a decimal frequency division signal of a decimal frequency division ratio signal, the output end of the first accumulation quantizer is connected with the input end of the first D trigger, the output end of the first D trigger is connected with the second input end of the first accumulation quantizer and the first input end of the second accumulation quantizer, the output end of the second accumulation quantizer is connected with the input end of the second D trigger, the output end of the second D trigger is connected with the second input end of the second accumulation quantizer, the carry output end of the first accumulation quantizer is connected with the first input end of the second adder, the carry output end of the second accumulation quantizer is connected with the input end of the third D trigger and the second input end of the second adder, the output end of the third D trigger is connected with the third input end of the second adder, and the output end of the second adder is used for outputting a first digital signal.
5. The fractional frequency synthesizer of claim 1, wherein the second modulation unit comprises a third adder, an accumulator and a second noise shaping modulator, a first input of the third adder for receiving the first digital signal, a second input of the third adder for receiving the fractional frequency signal of the fractional frequency signal, an input of the accumulator connected to an output of the third adder, an input of the second noise shaping modulator connected to an output of the accumulator, and an output of the second noise shaping modulator for outputting the delay factor.
6. The fractional frequency synthesizer of claim 5, wherein the second noise shaping modulator comprises a third accumulation quantizer, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, and a fourth adder;
the first input end of the third accumulation quantizer is connected with the output end of the accumulator, the output end of the third accumulation quantizer is connected with the input end of the fourth D trigger and the first input end of the fourth accumulation quantizer, the output end of the fourth D trigger is connected with the second input end of the third accumulation quantizer, the output end of the fourth accumulation quantizer is connected with the input end of the fifth D trigger, the output end of the fifth D trigger is connected with the second input end of the fourth accumulation quantizer, the carry output end of the third accumulation quantizer is connected with the first input end of the fourth adder, the carry output end of the fourth accumulation quantizer is connected with the second input end of the fourth adder and the input end of the sixth D trigger, the output end of the sixth D trigger is connected with the third input end of the fourth adder, and the output end of the fourth adder is used for outputting a delay coefficient.
7. The fractional frequency synthesizer of claim 1, wherein the phase frequency detector further comprises a logic gate, a first input of the logic gate is connected to the Q output of the first D flip-flop, a second input of the logic gate is connected to the Q output of the second D flip-flop, and an output of the logic gate is connected to the delay drive unit.
8. The fractional-n frequency synthesizer of claim 1, wherein the loop divider comprises a programmable divider and a prescaler, an input of the prescaler being coupled to an output of the oscillator, an input of the programmable divider being coupled to an output of the prescaler, an output of the programmable divider being coupled to a phase frequency detector, the programmable divider and prescaler simultaneously forming a feedback connection.
9. The fractional frequency synthesizer of claim 1 wherein the delay drive unit is a programmable delay drive unit.
10. A chip comprising the fractional frequency synthesizer of any one of claims 1 to 9.
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