CN115799330A

CN115799330A - High-voltage-resistant HEMT device and preparation method thereof

Info

Publication number: CN115799330A
Application number: CN202211410574.7A
Authority: CN
Inventors: 吴龙江
Original assignee: Shenzhen Sirius Semiconductor Co ltd
Current assignee: Shenzhen Sirius Semiconductor Co ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2023-03-14

Abstract

The application relates to a high-voltage-resistant HEMT device and a preparation method thereof. The high-voltage resistant HEMT device comprises: the semiconductor device comprises a semiconductor substrate, and a drift layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked on the front surface of the semiconductor substrate. The gate is disposed on the barrier layer. The Schottky metal layer is arranged on the drift layer and is in contact with the first side of the buffer layer. The source electrode is arranged on the Schottky metal layer and is in contact with the channel layer and the barrier layer. The intermediate metal layer is arranged on the drift layer and is in contact with the second side of the buffer layer and the channel layer and the barrier layer. The drain electrode is arranged on the back surface of the semiconductor substrate. This application can construct an anode and be connected with the source electrode and the cathode passes through the schottky diode that semiconductor substrate and drain electrode are connected through schottky metal layer and drift layer, semiconductor substrate, when high voltage applys on drain electrode and source electrode, then this schottky diode can be punctured to the voltage between restriction drain electrode and the source electrode has promoted high-pressure resistant ability.

Description

High-voltage-resistant HEMT device and preparation method thereof

Technical Field

The application belongs to the technical field of high electron mobility transistors, and particularly relates to a high-voltage-resistant HEMT device and a preparation method thereof.

Background

At present, gallium nitride is a novel third-generation semiconductor material, has many excellent characteristics, is the mainstream for developing power semiconductors in the future, and can be used for constructing a High Electron Mobility Transistor (HEMT) device by constructing two-Dimensional Electron Gas (2deg. The substrates commonly used at present with gan have advantages and disadvantages, wherein although the cost of sic is high, the lattice dislocation of gan can be greatly reduced, and the yield and device performance can be improved.

However, the conventional power switching tube made of gallium nitride and silicon carbide has a problem of poor high voltage resistance, and is likely to break down when a high voltage is applied.

Disclosure of Invention

The application aims to provide a high-voltage-resistant HEMT device and a preparation method thereof, and aims to solve the problem that a traditional power switching tube constructed by gallium nitride and silicon carbide is poor in high-voltage-resistant capability.

A first aspect of an embodiment of the present application provides a high voltage HEMT device, including: a semiconductor substrate; the drift layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked on the front surface of the semiconductor substrate; a gate disposed on the barrier layer; the Schottky metal layer is arranged on the drift layer and is in contact with the first side of the buffer layer, and Schottky contact is formed between the Schottky metal layer and the drift layer; the source electrode is arranged on the Schottky metal layer, is in contact with the channel layer and the barrier layer and forms ohmic contact with the channel layer and the barrier layer; an intermediate metal layer disposed on the drift layer and contacting the buffer layer and the second sides of the channel layer and the barrier layer; wherein the second side is opposite the first side; and the drain electrode is arranged on the back surface of the semiconductor substrate.

In one embodiment, the thickness of the schottky metal layer is smaller than or equal to the sum of the thicknesses of the buffer layer and the channel layer.

In one embodiment, the semiconductor device further comprises a P-type cap layer; the P-type cap layer is arranged between the barrier layer and the grid electrode.

In one embodiment, the source electrode comprises a filling metal layer and a connecting metal layer; the filling metal layer extends from the upper surface of the barrier layer to the buffer layer; the connecting metal layer is disposed above the barrier layer and connected with the filling metal layer.

In one embodiment, the gate is made of schottky metal, and the source and the drain are made of ohmic metal.

In one embodiment, the semiconductor substrate and the drift layer are both N-type silicon carbide.

In one embodiment, the concentration of N-type dopant ions in the drift layer is less than the concentration of N-type dopant ions in the semiconductor substrate.

In one embodiment, the channel layer is made of gan, and the barrier layer is made of algan.

In an embodiment, the P-type cap layer is made of P-type gallium nitride.

A second aspect of the embodiments of the present application provides a method for manufacturing a high voltage HEMT device, including: sequentially forming a drift layer, a buffer layer, a channel layer, a barrier layer and a P-type cap layer on the front surface of the semiconductor substrate; etching the edge of the P-type cap layer; etching the buffer layer and the first sides of the channel layer and the barrier layer until the drift layer is exposed to form a first trench; etching the buffer layer and second sides of the channel layer and the barrier layer until the drift layer is exposed to form a second trench; sequentially forming a Schottky metal layer and a source electrode on the first groove filled with the metal material from bottom to top, and forming an intermediate metal layer on the second groove filled with the metal material; forming a Schottky contact between the Schottky metal layer and the drift layer, and forming an ohmic contact between the source electrode and the channel layer and the barrier layer; and forming a grid electrode on the P-type cap layer, and constructing a drain electrode on the back of the semiconductor substrate.

Compared with the prior art, the embodiment of the application has the advantages that: when the channel layer is contacted with the barrier layer, two-dimensional electron gas can be formed, the drain electrode is arranged on the back face of the semiconductor substrate, the two-dimensional electron gas and the drift layer are connected through the intermediate metal layer, the source electrode is connected with the drain electrode through the two-dimensional electron gas, the intermediate metal layer, the drift layer and the semiconductor substrate in sequence, power transmission is achieved, and therefore the capacity of resisting high voltage of the device can be improved through the drift layer and the semiconductor substrate on the premise that the high-speed on-off characteristic of the HEMT device is still achieved.

Meanwhile, the Schottky diode with the anode connected with the source electrode and the cathode connected with the drain electrode through the semiconductor substrate can be constructed through the Schottky metal layer, the drift layer and the semiconductor substrate, when high voltage is applied to the drain electrode and the source electrode (the drain electrode is high in potential and the source electrode is low in potential), if the voltage is larger than avalanche voltage of the Schottky diode constructed by the Schottky metal layer, the Schottky diode can be broken down, so that voltage between the drain electrode and the source electrode is limited, the whole high-voltage-resistant HEMT device is prevented from being burnt out by the high voltage, and the high-voltage-resistant capability is further improved.

Drawings

Fig. 1 is a schematic structural diagram of a high-voltage resistant HEMT device according to a first embodiment of the present application;

fig. 2 is a schematic structural diagram of a high voltage HEMT device according to another embodiment of the present application;

fig. 3 is a schematic structural diagram of an insulating layer according to another embodiment of the present application;

fig. 4 is a flowchart of a method for manufacturing a high voltage HEMT device according to the second embodiment of the present application;

fig. 5 is a schematic structural diagram of the high voltage resistant HEMT device after step S100 is performed according to the second embodiment of the present application;

fig. 6 is a schematic structural diagram of the high voltage resistant HEMT device according to the second embodiment of the present application after step S200 is performed;

fig. 7 is a schematic structural diagram of the high voltage resistant HEMT device after step S400 is performed according to the second embodiment of the present application;

fig. 8 is a flowchart of a specific manufacturing method of a high voltage resistant HEMT device provided in the second embodiment of the present application;

fig. 9 is a schematic structural diagram of the high voltage HEMT device after step S500 is performed according to the second embodiment of the present application;

fig. 10 is a schematic structural diagram of a trapezoidal intermediate metal layer after step S500 is performed according to a second embodiment of the present application;

fig. 11 is a schematic structural diagram of a metal structure after step S500 is performed according to a second embodiment of the present application.

The drawings described above illustrate: 100. a semiconductor substrate; 200. a drift layer; 300. a buffer layer; 400. a channel layer; 500. a barrier layer; 510. a first trench; 520. a second trench; 600. a gate electrode; 610. a P-type cap layer; 700. a source electrode; 710. filling the metal layer; 720. connecting the metal layers; 730. a Schottky metal layer; 740. an insulating layer; 800. an intermediate metal layer; 810. a first metal structure; 820. a second metal structure; 830. a third metal structure; 900. and a drain electrode.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 1 shows a schematic structural diagram of a high-voltage-resistant HEMT device provided in the first embodiment of the present application, and for convenience of description, only the parts related to this embodiment are shown, which are detailed as follows:

a high-voltage-resistant HEMT device includes a semiconductor substrate 100, a drift layer 200, a buffer layer 300, a channel layer 400, and a barrier layer 500; the drift layer 200, the buffer layer 300, the channel layer 400, and the barrier layer 500 are sequentially stacked on the front surface of the semiconductor substrate 100, and the channel layer 400 and the barrier layer 500 are used to form a two-dimensional electron gas. The buffer layer 300 serves to reduce lattice dislocation between the channel layer 400 and the drift layer 200.

The high voltage resistant HEMT device further includes a gate 600, a schottky metal layer 730, a source 700, an intermediate metal layer 800, and a drain 900.

A gate 600 is disposed on the barrier layer 500. The schottky metal layer 730 is disposed on the drift layer 200 and contacts the first side of the buffer layer 300, and a schottky contact is formed between the schottky metal layer 730 and the drift layer 200. The source electrode 700 is disposed on the schottky metal layer 730, contacts the channel layer 400 and the barrier layer 500, and forms ohmic contact with the channel layer 400 and the barrier layer 500. The intermediate metal layer 800 is disposed on the drift layer 200 and contacts the second side of the buffer layer 300 and the channel layer 400 and the barrier layer 500. Wherein the second side is opposite to the first side, and the intermediate metal layer 800 is used for connecting the drift layer 200 and the two-dimensional electron gas. The drain 900 is provided on the back surface of the semiconductor substrate 100. The schottky metal layer 730 is made of schottky metal.

In the present embodiment, the drain electrode 900 is disposed on the back surface of the semiconductor substrate 100, and the two-dimensional electron gas and the drift layer 200 are connected through the intermediate metal layer 800, so that the source electrode 700 is connected to the drain electrode 900 through the two-dimensional electron gas, the intermediate metal layer 800, the drift layer 200, and the semiconductor substrate 100 in this order. Due to the fact that the drift layer 200 and the semiconductor substrate 100 have high-voltage resistance, on the premise that the HEMT device still has high-speed on-off characteristics, excessive voltage is prevented from being applied to the two-dimensional electron gas, and the high-voltage resistance of the device is improved through the drift layer 200 and the semiconductor substrate 100.

It should be noted that, in the present embodiment, by disposing the schottky metal layer 730 between the source 700 and the drift layer 200, the schottky metal layer 730 can form a schottky contact (metal-semiconductor junction) with the drift layer 200 to construct a schottky diode, i.e., a schottky diode having an anode connected to the source 700 and a cathode connected to the drain 900 is constructed between the source 700 and the drain 900. When a high voltage is applied to the drain 900 and the source 700 (wherein, the drain 900 is at a high potential, and the source 700 is at a low potential), if the voltage is greater than the avalanche voltage of the schottky diode constructed by the schottky metal layer 730, the schottky diode will be broken down, so as to limit the voltage between the drain 900 and the source 700, prevent the entire high voltage HEMT device from being burned out by the high voltage or prevent the high voltage HEMT device from being turned on by mistake, and further improve the high voltage resistance.

Particularly, when the power device is turned from an on state to an off state, if the external circuit is a circuit having a high inductance, the power device is easily subjected to a large voltage, which causes the power device to break down. In the high-voltage-resistant HEMT device of the embodiment, the schottky diode is broken down to realize the effect of the zener diode by arranging the schottky diode, when the voltage between the source 700 and the drain 900 exceeds the avalanche voltage of the schottky diode, so that the voltage between the source 700 and the drain 900 is limited, and the high-voltage-resistant HEMT device of the embodiment is prevented from being broken down or misconducted.

In the present embodiment, the thickness of the schottky metal layer 730 is less than or equal to the sum of the thicknesses of the buffer layer 300 and the channel layer 400. In one example, as shown in fig. 1, the thickness of the schottky metal layer 730 is equal to the sum of three-quarters of the thickness of the channel layer 400 plus the thickness of the buffer layer 300, such that the source 700 can be in direct intimate contact with the two-dimensional electron gas between the channel layer 400 and the barrier layer 500.

The high voltage resistant HEMT device of this embodiment is a depletion mode (D-mode) power device, and when the voltage applied to the gate 600 is 0, the two-dimensional electron gas between the source 700 and the drain 900 is on, i.e., the depletion mode power device is in an on state. When the value of the negative voltage applied to the gate 600 is greater than the turn-on voltage of the depletion mode power device, the two-dimensional electron gas corresponding to the lower side of the gate 600 is cut off, and the depletion mode power device is turned off.

As shown in fig. 1, the metal filler layer 710 extends downward from the upper surface of the barrier layer 500, and the thickness of the metal filler layer 710 is greater than that of the barrier layer 500, so that the metal filler layer 710 is directly connected to the formed two-dimensional electron gas. In one example, the difference between the thicknesses of the fill metal layer 710 and the barrier layer 500 is equal to one-quarter of the thickness of the channel layer 400.

In this embodiment, the gate 600 is made of schottky metal, and the source 700 and the drain 900 are made of ohmic metal. The material of the gate 600 may be nickel nitride (Ni) ₃ N), aluminum (Al), platinum (Pt), and the material of the source and drain

electrodes

700 and 900 may be titanium (Ti). In one example, the drain 900 covers the entire back surface of the semiconductor substrate 100.

In this embodiment, the semiconductor substrate 100 and the drift layer 200 are both made of N-type silicon carbide.

Wherein the concentration of the N-type dopant ions in the drift layer 200 is less than the concentration of the N-type dopant ions in the semiconductor substrate 100.

The thickness of the drift layer 200 is positively correlated with the high voltage capability of the high voltage HEMT device. In one example, the thickness of the drift layer 200 is five times the thickness of the semiconductor substrate 100.

In this embodiment, the material of the channel layer 400 is gallium nitride (GaN). The material of barrier layer 500 is aluminum gallium nitride (AlGaN). The material of the buffer layer 300 is aluminum nitride (AlN).

The material of the barrier layer 500 may also be any one of indium aluminum gallium nitride (InAlGaN) and indium gallium nitride (InGaN), and the corresponding material may be selected according to actual situations.

In another embodiment, the high voltage HEMT device further comprises a P-type cap layer 610.

As shown in fig. 2, in particular, a P-type cap layer 610 is disposed between the barrier layer 500 and the gate 600.

It should be noted that the power device with the P-type cap layer 610 is an enhancement mode (E-mode) power device, when a positive voltage with a value greater than a turn-on voltage is applied to the gate 600, the two-dimensional electron gas from the source 700 to the intermediate metal layer 800 may be kept on, and a current received by the drain 900 may be transmitted to the source 700 through the semiconductor substrate 100, the drift layer 200, the intermediate metal layer 800, and the two-dimensional electron gas in sequence.

When the voltage applied to the gate electrode 600 is less than the turn-on voltage or is a negative voltage, the two-dimensional electron gas under the gate electrode 600 is blocked, and the current received by the drain electrode 900 is transmitted to the intermediate metal layer 800 through the semiconductor substrate 100 and the drift layer 200 in sequence, and then cannot be transmitted to the source electrode 700 through the two-dimensional electron gas.

In this embodiment, the P-type cap layer 610 is made of P-type gallium nitride (P-GaN).

In one embodiment, the semiconductor substrate 100 has a thickness of 10nm to 30nm, the drift layer 200 has a thickness of 50nm to 100nm, the buffer layer 300 has a thickness of 3nm to 30nm, the channel layer 400 has a thickness of 3nm to 30nm, and the barrier layer 500 has a thickness of 3nm to 30nm.

In one example, the semiconductor substrate 100 has a thickness of 20nm, the drift layer 200 has a thickness of 60nm, the buffer layer 300 has a thickness of 20nm, the channel layer 400 has a thickness of 20nm, and the barrier layer 500 has a thickness of 20nm. The thickness of the fill metal layer 710 is 25nm, and correspondingly, the thickness of the schottky metal 730 under the fill metal layer 710 is 35nm.

In one embodiment, the thickness of the P-type cap layer 610 is 2nm to 5nm.

In another embodiment, as shown in fig. 3, an insulating layer 740 is further disposed between the schottky metal layer 730 and the buffer layer 300 and the channel layer 400, and the insulating layer 740 is used for reducing leakage current generated from the schottky metal layer 730.

Fig. 4 is a flowchart illustrating a method for manufacturing a high-voltage HEMT device according to a third embodiment of the present application, and for convenience of description, only the portions related to this embodiment are shown, which are detailed as follows:

a method for manufacturing a high-voltage-resistant HEMT device can be used for manufacturing the high-voltage-resistant HEMT device of any one of the embodiments. The preparation method comprises steps S100-S600.

In step S100, a drift layer 200, a buffer layer 300, a channel layer 400, a barrier layer 500, and a P-type cap layer 610 are sequentially formed on the front surface of a semiconductor substrate 100.

A schematic structural view of the semiconductor substrate 100, the drift layer 200, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 is shown in fig. 5.

In an example, the thickness of the semiconductor substrate 100 and the thickness of the drift layer 200 are 2 to 5 times that of the semiconductor substrate 100, wherein the thickness of the semiconductor substrate 100 and the thickness of the drift layer 200 determine the high voltage resistance of the high voltage resistant HEMT device, and the thicker the semiconductor substrate 100 and the drift layer 200, the stronger the corresponding high voltage resistance is.

In step S200, the edge of the P-type cap layer 610 is etched.

The etched P-type cap layer 610 is shown in fig. 6, and the P-type cap layer 610 is located in the central area of the surface of the barrier layer 500 by etching the edge portion of the P-type cap layer 610. The P-type cap layer 610 can be used for constructing the gate 600.

In an example, the shape of the P-type cap layer 610 may be a polygon, a circle or an arc, which is not limited by the embodiment.

In step S300, the buffer layer 300 and the first sides of the channel layer 400 and the barrier layer 500 are etched until the drift layer 200 is exposed to form a first trench 510.

In step S400, the buffer layer 300 and the second sides of the channel layer 400 and the barrier layer 500 are etched until the drift layer 200 is exposed to form a second trench 520.

As shown in fig. 7, the first trench 510 and the second trench 520 each reach deep into the drift layer 200, and the second side is opposite to the first side, so that the first trench 510 and the second trench 520 are respectively located on opposite sides of the barrier layer 500 (buffer layer 300/channel layer 400), and the P-type capping layer 610 is located on the barrier layer 500 between the first trench 510 and the second trench 520.

In a specific application embodiment, the depths of the first trench 510 and the second trench 520 are the sum of the thicknesses of the buffer layer 300, the channel layer 400, and the barrier layer 500.

In step S500, a schottky metal layer 730 and a source 700 are sequentially formed by filling a metal material into the first trench 510, and an intermediate metal layer 800 is formed by filling a metal material into the second trench 520. Schottky contact is formed between the schottky metal layer 730 and the drift layer 200, and ohmic contact is formed between the source 700 and the channel layer 400 and the barrier layer 500.

In step S600, a gate electrode 600 is formed on the P-type cap layer 610, and a drain electrode 900 is constructed on the backside of the semiconductor substrate 100.

As shown in fig. 8, the steps S500 and S600 specifically include:

in step S500, a schottky metal layer 730 and a metal filling layer 710 are sequentially formed in the first trench 510 and the second trench 520 from bottom to top by filling metal materials to form an intermediate metal layer 800.

Fig. 9 shows a schematic structure of the schottky metal layer 730, the filling metal layer 710 and the intermediate metal layer 800.

The filler metal layer 710 and the intermediate metal layer 800 are respectively located at two opposite sides of the barrier layer 500, such that the gate 600 is disposed above the barrier layer 500 between the filler metal layer 710 and the intermediate metal layer 800 for controlling conduction and interruption of the two-dimensional electron gas between the filler metal layer 710 and the intermediate metal layer 800.

Meanwhile, in the step S500 of the present embodiment, a schottky metal layer 730 is formed in the first trench 510, and then a source 700 (a filling metal layer 710) is formed on the schottky metal layer 730, wherein the schottky metal layer 730 and the filling metal layer 710 are made of different materials, the schottky metal layer 730 is made of schottky metal, and the filling metal layer 710 is made of ohmic metal.

It should be noted that the schottky metal layer 730 may form a schottky contact (metal-semiconductor junction) with the drift layer 200, so as to form a schottky diode, an anode of the schottky diode is connected to the source 700, and a cathode of the schottky diode is connected to the drain 900, when a high voltage is applied to the drain 900 and the source 700, if the voltage is greater than an avalanche voltage of the schottky diode formed by the schottky metal layer 730, the schottky diode may be broken down, so as to limit a voltage between the drain 900 and the source 700, prevent the entire high voltage HEMT device from being burned out by the high voltage, and further improve the high voltage resistance.

In one embodiment, the shape of the second trench 520 may be adjusted such that the cross-sectional shape of the intermediate metal layer 800 is arc-shaped or trapezoid. At this time, the width of the intermediate metal layer 800 gradually increases from the bottom to the top thereof. As shown in fig. 10, the intermediate metal layer 800 has a trapezoidal cross-sectional shape.

As shown in fig. 11, in one embodiment, the intermediate metal layer 800 may be composed of a plurality of metal structures, for example, the intermediate metal layer 800 may be composed of a first metal structure 810, a second metal structure 820 and a third metal structure 830, and the first metal structure 810, the second metal structure 820 and the third metal structure 830 correspond to the buffer layer 300, the channel layer 400 and the barrier layer 500 one to one.

In one embodiment, the widths of the first metal structure 810, the second metal structure 820 and the third metal structure 830 gradually increase.

In one embodiment, the widths of the first metal structure 810, the second metal structure 820 and the third metal structure 830 are set according to an equal difference ratio.

In a specific application embodiment, the shape of the interface between the first metal structure 810 and the buffer layer 300, the shape of the interface between the second metal structure 820 and the channel layer 400, and the shape of the interface between the third metal structure 830 and the barrier layer 500 may be different from each other.

In a specific embodiment, the metal materials used for the first metal structure 810, the second metal structure 820 and the third metal structure 830 may be different from each other. For example, the first metal structure 810 may be gold and the second metal structure 820 may be copper.

In step S600, a gate electrode 600 is formed on the P-type cap layer 610, and a drain electrode 900 is formed on the backside of the semiconductor substrate 100, and a connection metal layer 720 connected to the fill metal layer 710 is formed above the barrier layer 500.

The gate 600, the drain 900 and the connection metal layer 720 are structured as shown in fig. 2, the filling metal layer 710 and the connection metal layer 720 together constitute the source 700, and the overall cross section of the source 700 is L-shaped. The filler metal layer 710 is used to connect the two-dimensional electron gas, and the connection metal layer 720 is used to connect with an external circuit. In an example, the shapes of the gate electrode 600 and the connection metal layer 720 may be a polygon, a circle, or an arc, which is not limited by the embodiment. The thickness of the gate electrode 600, the connection metal layer 720 and the drain electrode 900 is 10nm-100um.

In the present embodiment, the drain electrode 900 is disposed on the back surface of the semiconductor substrate 100, and the two-dimensional electron gas and the drift layer 200 are connected through the intermediate metal layer 800, so that the source electrode 700 is connected to the drain electrode 900 through the two-dimensional electron gas, the intermediate metal layer 800, the drift layer 200, and the semiconductor substrate 100 in this order. Because the drift layer 200 and the semiconductor substrate 100 have high voltage resistance, the drift layer 200 and the semiconductor substrate 100 improve the high voltage resistance of the device on the premise that the device still has the high-speed on-off characteristic of the HEMT device.

In this embodiment, the gate electrode 600 is made of schottky metal, and the source electrode 700 and the drain electrode 900 are made of ohmic metal.

Specifically, the concentration of N-type dopant ions in the drift layer 200 is smaller than the concentration of N-type dopant ions in the semiconductor substrate 100.

In this embodiment, the material of the channel layer 400 is gallium nitride (GaN). The material of barrier layer 500 is aluminum gallium nitride (AlGaN).

In one embodiment, in step S100, the drift layer 200, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 may be deposited by a known method such as Chemical Vapor Deposition (CVD), and the Deposition method of the drift layer 200, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 is not limited in this embodiment.

In an embodiment, in step S200, step 300, and step S400, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 may be etched by using a known method such as dry etching or wet etching, and the etching method of the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 is not limited in this embodiment. In one example, the buffer layer 300, the channel layer 400, the barrier layer 500, and the P-type cap layer 610 may be etched using an inductively Coupled Plasma etching (ICP).

In one embodiment, in steps S500 and S600, the schottky metal layer 730, the gate 600, the source 700, the intermediate metal layer 800 and the drain 900 may be structured by a known method such as a vacuum evaporation method or a sputtering method, and a specific structure method of the schottky metal layer 730, the gate 600, the source 700, the intermediate metal layer 800 and the drain 900 is not limited in this embodiment.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A high voltage tolerant HEMT device, comprising:

a semiconductor substrate;

the drift layer, the buffer layer, the channel layer and the barrier layer are sequentially stacked on the front surface of the semiconductor substrate;

a gate disposed on the barrier layer;

the Schottky metal layer is arranged on the drift layer and is in contact with the first side of the buffer layer, and Schottky contact is formed between the Schottky metal layer and the drift layer;

the source electrode is arranged on the Schottky metal layer, is in contact with the channel layer and the barrier layer and forms ohmic contact with the channel layer and the barrier layer;

an intermediate metal layer disposed on the drift layer and contacting the buffer layer and the second sides of the channel layer and the barrier layer; wherein the second side is opposite the first side;

and the drain electrode is arranged on the back surface of the semiconductor substrate.

2. The high voltage HEMT device of claim 1, wherein said schottky metal layer has a thickness less than or equal to the sum of the thicknesses of said buffer layer and said channel layer.

3. The high voltage tolerant HEMT device of claim 1 or 2, further comprising a P-type cap layer;

the P-type cap layer is arranged between the barrier layer and the grid electrode.

4. The high voltage tolerant HEMT device of claim 1 or 2, wherein said source electrode comprises a fill metal layer and a link metal layer;

the filling metal layer extends from the upper surface of the barrier layer to the buffer layer;

the connecting metal layer is disposed above the barrier layer and connected to the fill metal layer.

5. The high voltage resistant HEMT device of claim 1 or 2, wherein the material of said gate is a schottky metal and the material of said source and said drain is an ohmic metal.

6. The high-voltage resistant HEMT device of claim 1 or 2, wherein said semiconductor substrate and said drift layer are both N-type silicon carbide.

7. The high-voltage resistant HEMT device of claim 1 or 2, wherein a concentration of N-type dopant ions in said drift layer is less than a concentration of N-type dopant ions in said semiconductor substrate.

8. The high voltage HEMT device of claim 1 or 2, wherein said channel layer is comprised of gallium nitride and said barrier layer is comprised of aluminum gallium nitride.

9. The high voltage HEMT device of claim 3, wherein said P-type cap layer is of P-type gallium nitride.

10. A preparation method of a high-voltage-resistant HEMT device is characterized by comprising the following steps:

sequentially forming a drift layer, a buffer layer, a channel layer, a barrier layer and a P-type cap layer on the front surface of a semiconductor substrate;

etching the edge of the P-type cap layer;

etching the buffer layer and the first sides of the channel layer and the barrier layer until the drift layer is exposed to form a first trench;

etching the buffer layer and second sides of the channel layer and the barrier layer until the drift layer is exposed to form a second trench;

sequentially forming a Schottky metal layer and a source electrode on the first groove filled with the metal material from bottom to top, and forming an intermediate metal layer on the second groove filled with the metal material; forming Schottky contact between the Schottky metal layer and the drift layer, and forming ohmic contact between the source electrode and the channel layer and the barrier layer;

and forming a grid electrode on the P-type cap layer, and constructing a drain electrode on the back of the semiconductor substrate.