CN115799236A - Semiconductor package and method of forming the same - Google Patents

Abstract

An embodiment of the present invention provides a semiconductor package structure, including: the photonic chip is positioned on the substrate, a first part of a first side of the photonic chip is positioned in the accommodating space and electrically connected to the accommodating space, and a photosensitive area of the photonic chip is positioned outside the accommodating space; and the optical fiber is positioned on the substrate, and light emitted by the optical fiber is directly coupled to the photosensitive area of the photonic chip. The present invention is directed to a semiconductor package and a method for forming the same to reduce the coupling loss of the package.

Description

Semiconductor package and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor packages and methods of forming the same.

Background

In a silicon photonic (Si-Ph) structure, if a Fiber Array Unit (FAU) and a photonic chip (PIC) are to be coupled by a Grating coupling (Grating coupling) method. Referring to fig. 1A, in the prior art, a Mirror (Mirror) 11 is needed to guide light emitted from a grating 15 into a waveguide (Wave guide, WG) of a PIC13, such a structure itself lengthens a path of the light (the path needs to be turned), and if a bevel angle is not accurately controlled, an incorrect bevel angle causes reflected light to not be accurately irradiated to the PIC13 and light refraction (shown by a dotted arrow) may occur, further increasing coupling loss (for example, loss of light refraction or an incorrect angle of reflected light), and thus a package structure capable of reducing the coupling loss is needed.

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide a semiconductor package structure and a method for forming the same, so as to reduce the coupling loss of the package structure.

To achieve the above object, an embodiment of the present invention provides a semiconductor package structure, including: the photonic chip is positioned on the substrate, a first part of a first side of the photonic chip is positioned in the accommodating space and electrically connected to the accommodating space, and a photosensitive area of the photonic chip is positioned outside the accommodating space; and the optical fiber is positioned on the substrate, and light emitted by the optical fiber is directly coupled to the photosensitive area of the photonic chip.

In some embodiments, the optical fiber and the photo-sensing region of the photonic chip are located at the same height.

In some embodiments, further comprising: and the underfill material is positioned between the photonic chip and the substrate, and does not cover the photosensitive region.

In some embodiments, further comprising: and the light-transmitting glue is positioned on the bottom filling material, covers the photosensitive area and is positioned on a path from the optical coupling of the optical fiber to the photosensitive area.

In some embodiments, further comprising: and the light-transmitting glue encapsulates the whole photonic chip and is positioned between the substrate and the photonic chip.

In some embodiments, further comprising: and the electronic element is positioned on the substrate and outside the accommodating space, and the electronic element is positioned outside a path through which the light of the optical fiber is coupled to the light sensing area.

In some embodiments, the first side of the photonic chip is the active side.

In some embodiments, the photosensitive region of the photonic chip includes a waveguide.

In some embodiments, the photonic chip is in contact with the optical fiber.

In some embodiments, the substrate comprises: a substrate core; a first circuit layer on the substrate core; the accommodating space is positioned in the first dielectric layer and the first circuit layer and occupies part of the thickness of the substrate core.

An embodiment of the present application provides a method of forming a semiconductor package structure, including: forming an accommodating space in an upper surface of the substrate; fixing the photonic chip to the surface of the accommodating space in an inclined manner; the optical fiber is arranged on the substrate, and the optical fiber is arranged to emit light which is directly connected with the photosensitive area of the photonic chip.

In some embodiments, the receiving space is formed in the upper surface of the substrate using a machining process.

In some embodiments, further comprising: and an underfill material is filled between the photonic chip and the substrate, and the underfill material does not coat the photosensitive area of the photonic chip.

In some embodiments, further comprising: and forming a light-transmitting glue on the bottom filling material, wherein the light-transmitting glue covers the light-sensing area of the optical element.

In some embodiments, the strength of the underfill material is greater than the strength of the light-transmitting glue.

In some embodiments, after forming the bottom encapsulant material, the optical fibers are formed on a substrate and then an optically transmissive glue is formed that partially encapsulates the optical fibers.

In some embodiments, further comprising: and forming a light-transmitting glue for coating the optical element, wherein the light-transmitting glue is also formed between the optical element and the substrate.

In some embodiments, light emitted by the optical fiber is directly coupled to the photosensitive region of the photonic chip through the light-transmissive glue.

In some embodiments, further comprising: a molding compound is formed that encapsulates the light-transmitting glue, the optical fibers, and the substrate.

In some embodiments, the photonic chip is bonded to the first sidewall of the receiving space, and the photonic chip is spaced apart from the second sidewall of the receiving space.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A shows a schematic diagram of a conventional semiconductor package structure.

Fig. 1B to 17D illustrate a process of forming a semiconductor package structure according to an embodiment of the present application.

Fig. 18-23 show schematic diagrams of semiconductor package structures according to various embodiments of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "essentially" and "about" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms can refer to both an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: the words "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

Referring to fig. 1B, a first dielectric layer 14 is formed on the substrate core 10 and the first wiring layer 12. In some embodiments, the substrate core 10, the first line layer 12, and the first dielectric layer 14 form a substrate 100. In some embodiments, the substrate core 10 and the first dielectric layer 14 are a nucleus layer (PNL) or a Wafer Layer (WL). In some embodiments, the first dielectric layer 14 is a non-metallic material, such as Polyimide (PI), epoxy (epoxy), pre-preg (PP), ajinomotobuild-up (ABF), and/or acrylic (acrylic). In some embodiments, the first dielectric layer 14 is formed using an organic photosensitive or/and non-photosensitive liquid or/and dry film material. In some embodiments, the first dielectric layer 14 may be formed, for example, by spin coating, lamination, chemical Vapor Deposition (CVD), or the like. In some embodiments, the first circuitry layer 12 includes a second dielectric layer 16 and an inner circuitry 18. In some embodiments, the material and formation process of the second dielectric layer 16 is the same as the first dielectric layer 14. In some embodiments, the material of the inner line 18 includes Cu, au, ag, al, pd, pt, ni, alloys thereof, or combinations thereof. In some embodiments, the internal traces 18 are formed using Physical Vapor Deposition (PVD), sputtering, electroplating, electroless plating (E' less), and/or printing and/or potting processes.

Referring to fig. 2, the accommodating space 30 shown in fig. 3 is formed in the substrate 100 using a machining process (e.g., using the roller 20). In some embodiments, the accommodating space 30 is formed in the first line layer 12 and the first dielectric layer 14. In some embodiments, the accommodating space 30 is formed in the first line layer 12, the first dielectric layer 14, and the substrate core 10. In some embodiments, the accommodating space 30 avoids the inner wires 18 of the first wire layer 12 and the wires in the substrate core 10. In some embodiments, the accommodating space 30 is formed to have a V-shaped cross section as shown in the drawings, and the accommodating space 30 may also be formed to have a cross section of a U-shape, an inverted trapezoid, or other suitable shapes. In some embodiments, the included angle between the sidewall of the accommodating space 30 and the horizontal plane is 10 ° to 80 °, that is, the bottom angle α of the accommodating space 30 is 20 ° to 160 °.

In some embodiments, a photolithography process 31 (e.g., using laser drilling) is used to form openings in the first dielectric layer 14 that expose the inner lines 18, as shown in fig. 4, and a first seed layer 40 is formed in the openings and on the first dielectric layer 14. In some embodiments, the material of the first seed layer 40 includes Cu, au, ag, al, pd, pt, ni, alloys thereof, or combinations thereof. In some embodiments, the first seed layer 40 is formed using a Physical Vapor Deposition (PVD), sputtering, electroplating, electroless plating (E' less), and/or printing and/or potting process.

Referring to fig. 5, a first mask layer 50 is formed on the first seed layer 40. In some embodiments, the first mask layer 50 is a Photoresist (PR) material, and a first exposure process 51 is performed to cure the first mask layer 50.

Referring to fig. 6, the first mask layer 50 is patterned and a first metal layer 60 is formed in the patterned first mask layer 50. In some embodiments, the material of first metal layer 60 includes Cu, au, ag, al, pd, pt, ni, alloys thereof, or combinations thereof. In some embodiments, first metal layer 60 is formed using a Physical Vapor Deposition (PVD), sputtering, electroplating, electroless (E' less), and/or printing and/or potting process.

Referring to fig. 7, the first mask layer 50 is removed and the first seed layer 40 is patterned using the first metal layer 60 as a mask. The first metal layer 60 and the first seed layer form a first via 70 through the first dielectric layer 40 in some embodiments and a first line 72 on the first dielectric layer 14 in other embodiments.

Referring to fig. 8, a photonic chip (PIC) 80 is placed in the accommodating space 30 using a first clamp 81. In some embodiments, a vacuum cavity 82 is provided between the first clip 81 and the photonic chip 80 to hold the photonic chip 80. In some embodiments, the photonic chip 80 is electrically connected to the first trace 72 in the accommodating space 30 through the first solder ball 84.

Referring to fig. 9A, a reflow process 91 is performed to bond the first solder balls 84 to the first wires 72 located in the accommodating space 30. In some embodiments, the length of the photonic chip 80 in the accommodating space 30 is less than the total length of the photonic chip 80. In some embodiments, the photosensitive element 850 in the photosensitive region 85 of the photonic chip 80 is located outside the accommodating space 30. In some embodiments, the first side of the photonic chip 80 (the side facing the first solder balls 84) is the active side, and the photosensitive region 85 is located in the active side. In some embodiments, the photonic chip 80 is bonded to the first line 72 at the first sidewall 301 of the receiving space 30, and the photonic chip 80 is spaced apart from the second sidewall 302 of the receiving space, i.e., there is a distance between the photonic chip 80 and the second sidewall 302.

Referring to fig. 9B, in some embodiments, the side 83 of the photonic chip 80 abuts against the second sidewall 302 of the accommodating space 30.

Fig. 9C shows the structure in the dotted line box D in fig. 9B, the first solder ball 84 is melted into a flattened solder after the reflow process, and covers a portion of the sidewall of the connection 220 at the bottom of the photonic chip 80 and a portion of the sidewall of the first wire 72, and the connection 220, the first solder ball 84, and the first wire 72 constitute a micro bump (ubump) having a diameter of 10 μm to 30 μm and a pitch (pitch) of 15 μm to 60 μm.

Referring to fig. 10, the electronic component 102 is placed on the substrate 100 using the second clamp 101. In some embodiments, a second vacuum chamber 104 is provided between the second clamping member 101 and the electronic component 102 to hold the electronic component 102. The electronic component 102 is electrically connected to the first via 70 and the first wiring 72. In some embodiments, the electronic component 102 is an electronic chip (EIC). In some embodiments, the length of the photonic chip 80 and the electronic component 102 is tens of μm to hundreds of μm.

Referring to fig. 11, a second reflow process 111 is performed such that the second solder balls 110 of the electronic component 102 are bonded to the first via holes 70 and the first wires 72.

Referring to fig. 12, an underfill material 120 is disposed between the electronic component 102 and the substrate 100, and between the photonic chip 80 and the substrate 100. Underfill material 120 also encapsulates the lower portion of photonic chip 80, with photosensitive region 85 of photonic chip 80 not being encapsulated by underfill material 120. In some embodiments, the underfill material 120 is an adhesive layer. In some embodiments, the underfill material 120 is optically transmissive or opaque. In embodiments where the underfill material 120 is opaque, the underfill material 120 does not encapsulate the photo-sensing region 85 of the photonic chip 120. In some embodiments, the underfill material 120 is a non-metallic material, such as Polyimide (PI), epoxy (epoxy), prepreg (PP), ajinomotobuild-up film (ABF), and/or acrylic (acrylic). In some embodiments, the underfill material 120 is formed using an organic photosensitive or/and non-photosensitive liquid or/and dry film material. The underfill material 120 may be provided to improve structural strength and avoid the occurrence of cracks or fractures. The underfill material 120 protects the connections 220 at the bottom of the photonic chip 80 and the traces 72 of the substrate 100.

Referring to fig. 13, the structure is reversed and the third solder balls 130 are formed on the substrate core 10 of the substrate 100. In some embodiments, the third solder balls 130 have a diameter of 30 μm to 200 μm and a pitch of 50 μm to 400 μm.

Fig. 1 to 13 are illustrated by taking a single package structure as an example, in an actual production process, a plurality of package structures are formed together, and then referring to fig. 14, a singulation process is performed to form a single package structure. In some embodiments, the structure is cut using a second roller 141.

Referring to fig. 15, the optical fiber 150 is placed on the substrate 100 using the third clamping member 151. In some embodiments, a third vacuum lumen 152 is provided between the third clamping member 151 and the optical fiber 150 to hold the optical fiber 150. In some embodiments, the optical fiber 150 is a Fiber Array Unit (FAU). In some embodiments, the optical fiber 150 is a single optical fiber. Adhesive layer 154 is positioned between optical fiber 150 and substrate 110. In some embodiments, the material of the adhesion layer 154 is the same as the material of the underfill material 120. The light emitted by the optical fiber 150 of embodiments of the present application may be directed towards the photonic chip 80, providing a light path from the optical fiber 150 to the photonic chip 80 that does not need to be turned. In some embodiments, the thickness of the optical fiber 150 is 10 μm to 50 μm. In some embodiments, the optical fiber 150 and the photosensitive region 85 of the photonic chip 80 are located at the same height.

Referring to fig. 16, a light-transmitting glue 160 is formed on the underfill material 120. The light-transmitting glue 160 also encapsulates the electronic component 102 and portions of the optical fibers 150. In some embodiments, the light-transmissive glue 160 is a non-metallic material, such as Polyimide (PI), epoxy (epoxy), pre-cured resin (PP), ajinomotobueld-up film (ABF), and/or acrylic (acrylic). In some embodiments, the light-transmitting glue 160 is formed using an organic photosensitive or/and non-photosensitive liquid or/and dry film material. In some embodiments, the light-transmitting glue 160 is not formed. The use of the light-transmitting adhesive 160 for packaging can ensure that light in a coupling path between the photonic chip 80 and the optical fiber 150 can pass smoothly to maintain the optical path, and the use of the light-transmitting adhesive 160 can also package the photonic chip 80 to avoid being damaged. In some embodiments, the strength of the material of the underfill material 120 is greater than the strength of the material of the light-transmitting glue 160.

Fig. 17A illustrates a semiconductor package 170 ultimately formed in accordance with the present application, in which the photosensitive region 85 of the photonic chip 80 receives light 172 emitted by the optical fiber 150 during operation. The optical fiber 150 may provide a light pattern to be transmitted directly to the grating of the photosensitive region 85 of the photonic chip 80 through the light-transmitting paste 160 (see fig. 17B and 17C). The light-transmitting glue 160 and the underfill material 120 protect the devices on the substrate 100 and keep the photonic chip 80 tilted, and also ensure adhesion between the optical fiber 150 and the substrate 100.

Fig. 17B-17D illustrate a specific configuration of the photosensitive region 85 of the photonic chip 80 of the present application. Wherein photosensitive element 850 of photosensitive area 85 comprises waveguide 852 and cladding layer 854 that encases waveguide 852. In some embodiments, the waveguide 852 has a grating 856 thereon and the cross-sectional view of the grating 856 is non-rectangular (e.g., trapezoidal as shown), with the grating 856 being located at the end of the waveguide 852. Fig. 17C shows a top view of a waveguide 852 according to some embodiments, where the waveguide 852 may be bent, the laser diode 858 connects the waveguide 852, the waveguide 852 may be connected to the core 853 of the photonic chip 80 and transmits the signal from the grating 856 to the core 853, as required for signal transmission. Fig. 17D illustrates a cross-sectional view of photosensitive region 85 of photonic chip 80 taken along line B-B of fig. 17C, where capping layer 854 is shown in dashed lines, in accordance with some embodiments.

Fig. 18 shows an embodiment different from fig. 17A, in fig. 18, a mold compound 180 encapsulating the electronic element 102, the light-transmissive glue 160, and a portion of the optical fiber 150 on the substrate 100 is also formed.

Fig. 19 shows an embodiment different from fig. 17A, in fig. 19, a pair of photonic chips 80 and an optical fiber 150 are formed on the left and right sides of the electronic component 102, respectively. Fig. 19 shows only one cross section, and in a top view, a plurality of pairs of photonic chips 80 and optical fibers 150 may be formed around the electronic component 102.

Fig. 20 shows an embodiment different from fig. 17A, in fig. 20, the underfill material 120 is not formed, and the light-transmissive glue 160 encapsulates the entire photonic chip 80.

Fig. 21 shows an embodiment different from fig. 17A, in fig. 21, the electronic component 102 is formed in the cavities in the first dielectric layer 14 and the first circuit layer 12, and the accommodating space 30 leaves the lowermost corner portion and the side wall of the single supporting photonic chip 80. In some embodiments, after forming the accommodating space 30 shown in fig. 3, the first dielectric layer 14 and the portion of the first circuit layer 12 adjacent to the accommodating space 30 are further removed, and finally the structure shown in fig. 21 is formed.

Fig. 22 shows a different embodiment from fig. 17A, in fig. 22, the photonic chip 80 is farther away from the sidewall of the accommodating space 30 where it is bonded, and the connection 220 of the photonic chip 80 includes a high conductive pillar 221.

Fig. 23 shows a different embodiment from fig. 17A, in fig. 23, a photonic chip 80 is in contact with an optical fiber 150. In some embodiments, when the optical fiber 150 is placed as shown in fig. 150, the optical fiber 150 is placed close to the photonic chip 80 to contact the photonic chip 80. In some embodiments, the optical fiber 150 may be formed on the substrate 100 first, and then the photonic chip 80 may be placed on the substrate 100 such that the photonic chip 80 rests on the optical fiber 150.

Embodiments of the present application tilt and directly couple the photonic chip 80 to the optical fiber 150, reducing the transmission path of light and avoiding light loss due to refraction. The use of the underfill material 120 and the light-transmissive glue 160 of the present application enhances the strength of the structure, keeps the photosensitive devices 80 tilted to continuously receive light directly emitted by the optical fibers 150, and maintains good connections between the devices.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A semiconductor package structure, comprising:

a substrate, wherein the upper surface of the substrate is partially provided with an accommodating space,

the photonic chip is positioned on the substrate, a first part of a first side of the photonic chip is positioned in the accommodating space and is electrically connected to the substrate at the first side wall of the accommodating space, and a photosensitive area of the photonic chip is positioned outside the accommodating space;

an optical fiber on the substrate, light emitted by the optical fiber being directly coupled to a photosensitive element in the photosensitive region of the photonic chip.

2. The semiconductor package of claim 1, wherein the optical fiber and the photo-sensing region of the photonic chip are at a same height.

3. The semiconductor package structure of claim 1, further comprising:

and the bottom filling material is positioned between the photonic chip and the substrate, and the photosensitive region is not coated by the bottom filling material.

4. The semiconductor package structure of claim 3, further comprising:

and the light-transmitting glue is positioned on the bottom filling material, covers the photosensitive area and is positioned on a path of the light coupling of the optical fiber to the photosensitive element of the photosensitive area.

5. The semiconductor package structure of claim 1, wherein the accommodating space has a V-shaped cross section.

6. The semiconductor package structure of claim 1, further comprising:

and the electronic element is positioned on the substrate and outside the accommodating space, and the electronic element is positioned outside a path through which the light of the optical fiber is coupled to the photosensitive area.

7. The semiconductor package of claim 1, wherein the first side of the photonic chip is an active side.

8. The semiconductor package of claim 1, wherein the photosensitive element of the photosensitive region of the photonic chip comprises a waveguide.

9. The semiconductor package of claim 8, wherein the end of the waveguide has a grating, the grating having a non-rectangular cross-section.

10. The semiconductor package of claim 1, wherein the photonic chip is in contact with the optical fiber.

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