CN115799212A - Through hole interconnection structure and process implementation method thereof - Google Patents

Abstract

The invention discloses a through hole interconnection structure and a process realization method thereof, wherein the through hole interconnection structure comprises the following components: the third through hole is arranged on the back surface of the first substrate, and the first metal layer and the second metal layer are sequentially arranged on the front surface of the first substrate; the first metal layer comprises a plurality of densely distributed first metal structures, and the second metal layer comprises a plurality of densely distributed second metal structures which are positioned on the upper layer of the first metal structure technology; and the bottom of the third through hole penetrates through the front surface of the first substrate, falls on the first metal structure and the second metal structure, and fills a region enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure. The invention can obviously and effectively increase the effective contact area between the silicon through hole and the metal interconnection layer, thereby greatly reducing the current density and having lower electromigration failure risk.

Description

A through-hole interconnection structure and its process realization method

technical field

The invention relates to the technical field of semiconductor integrated circuit technology, in particular to a through-silicon via interconnection structure and a process realization method thereof.

Background technique

A three-dimensional integrated circuit refers to the formation of a three-dimensional integrated circuit structure with interconnections in the vertical direction by stacking chips. With the continuous improvement of chip integration, the method of simply reducing the critical size of semiconductor devices has approached the physical limit. In order to achieve higher integration and device capacity, three-dimensional integrated circuit technology is increasingly used in the field of chip manufacturing. Compared with two-dimensional integrated circuits, three-dimensional integrated circuits greatly shorten the interconnection length, and have the advantages of higher bandwidth, lower parasitic capacitance and interconnection delay, and lower power consumption.

Through-silicon vias refer to metal through-holes formed through silicon substrates through integrated circuit manufacturing techniques such as photolithography and etching. Through-silicon vias are the core of three-dimensional integration technology. As a bridge between the circuit on the back of the silicon chip and the circuit on the front of the silicon chip, it can reduce the lead resistance between the chips of the three-dimensional integrated circuit and reduce power consumption.

In the prior art, according to the process section of TSV processing, it can be divided into via-first process, intermediate via process, and via-last process. Circle stacks are formed after thinning. Moreover, according to the manufacturing process of the TSV, it can be divided into a front TSV and a back TSV. Among them, the front-side through-silicon vias are formed by photolithography and etching on the front side of the wafer (device surface), including two types of integration schemes: the first through-hole process and the intermediate through-hole process. The backside TSVs are formed by photolithography and etching on the backside of the wafer (substrate surface) after the wafers are stacked, which belongs to the post-throughhole process. The front-side TSVs need to be stacked, the back side is thinned, and the silicon-exposed copper process is used to realize the connection between the front and back circuits. On the other hand, through-silicon vias on the back are directly etched from the back of the wafer to connect the front-side circuits, and the process complexity is relatively low. However, since the through-silicon vias on the back need to pass through the thick silicon substrate to communicate with the back-end metal layer on the front, the requirements for photolithographic alignment and etching processes are higher.

The backside TSV process needs to complete the effective interconnection of the circuit through the back metal wiring of the wafer. In consideration of the difficulty of the process, it is generally selected to connect to the first layer of metal wiring closest to the silicon substrate. However, due to the limitation of the design rules of the first-layer metal wiring, the first-layer metal wiring cannot cover the complete large-scale TSV, and usually only multiple mesh metal wiring can be used to connect the TSV. Perform layout and routing, and then connect the first-layer metal connection to the second-layer metal connection and other metal layers through through holes.

According to the well depth requirements of different devices, as the thickness of the silicon substrate increases, the accuracy of aligning the front layer through the backside will decrease accordingly, and a large overlay alignment deviation will appear. At the same time, due to the inclination angle formed by etching and the existence of the sidewall liner dielectric, there is often obvious size shrinkage at the bottom of the TSV. The above reasons will lead to a reduction in the effective area when the TSV is connected to the first-layer metal wiring, and the risk of electromigration failure will be greatly increased due to the excessive current density of the connection part.

In addition, when large-sized TSVs are connected to metal lines with relatively small line widths, when a large current passes through, since the contact area of each metal line is relatively small, the passing current density is relatively large. Bringing a sharp increase in the risk of electromigration failure.

Due to design rules, the width of each conductive trench used to fill the metal wiring cannot exceed the maximum specification, so the effect of improving the current density by increasing the trench width is limited.

Contents of the invention

The object of the present invention is to overcome the above-mentioned defects in the prior art, and provide a through-hole interconnection structure and a process realization method thereof.

To achieve the above object, the technical scheme of the present invention is as follows:

The present invention provides a via interconnection structure, comprising:

a third through hole provided on the back side of the first substrate and a first metal layer and a second metal layer sequentially provided on the front side of the first substrate;

The first metal layer includes a plurality of densely distributed first metal structures, and the second metal layer includes a plurality of densely distributed second metal structures located on the upper layer of the first metal structure;

The bottom of the third through hole passes through the front surface of the first substrate, falls on the first metal structure and the second metal structure, and fills up the side walls and the second metal structure of the first metal structure. The area enclosed by the technical lower surface of the second metal structure.

Further, the first metal layer includes a first metal interconnection layer, the second metal layer includes a second metal interconnection layer, and the first metal structure includes a first metal interconnection layer located in the first metal interconnection layer. An interconnection metal line, the second metal structure includes a second interconnection metal line in the second metal interconnection layer.

Further, any one of the second interconnection metal lines and a corresponding first interconnection metal line in the lower layer are parallel to each other and arranged in a dislocation, and the bottom of the third through hole passes through the first After the front surface of the substrate, it falls on the first interconnection metal lines and the second interconnection metal lines, and fills the sidewalls of the first interconnection metal lines and the second interconnection metal lines. The area enclosed by the lower surface of the craft of the lines.

Further, each of the first interconnection metal lines is parallel to each other, each of the second interconnection metal lines is parallel to each other, and is arranged orthogonally to the first interconnection metal lines, the After passing through the front surface of the first substrate, the bottom of the third via hole lands on the first interconnection metal line and the second interconnection metal line, and fills up the first interconnection The area enclosed by the sidewall of the metal line and the process lower surface of the second interconnection metal line.

Further, it also includes:

a second via layer disposed between the first metal interconnection layer and the second metal interconnection layer, the second via layer comprising a plurality of densely distributed second via holes;

Each of the first interconnection metal lines is distributed in an array according to rows and columns, and each of the second interconnection metal lines is distributed in an array according to rows and columns, and is arranged in rows/columns with the first interconnection metal lines The upper phase overlap setting, and the phase misalignment setting on the column/row;

Any one of the second interconnection metal lines on the upper and lower overlapping rows/columns is connected to the two first interconnection metal lines on the corresponding two sides of the lower layer through a second via hole respectively. A chain structure is formed on the row/column;

The bottom of the third via hole falls on the first interconnection metal line and the second interconnection metal line after passing through the front surface of the first substrate, and fills up the first interconnection metal line. An area surrounded by the sidewalls of the interconnection metal lines, the sidewalls of the second through holes and the process lower surface of the second interconnection metal lines.

Further, the first metal layer includes a first via layer, the second metal layer includes a first metal interconnection layer, and the first metal structure includes a first via in the first via layer. hole, the second metal structure includes a first interconnection metal line located in the first metal interconnection layer; any one of the first through holes passes through one of the first through holes corresponding to the upper surface of the process and the upper layer The process lower surface of the interconnection metal line is connected, and the bottom of the third through hole falls on the first through hole and the first interconnection metal line after passing through the front surface of the first substrate , and fill up the area enclosed by the sidewall of the first through hole and the process lower surface of the first interconnection metal line.

Further, it further includes: a fifth dielectric layer disposed on the second metal layer, and a second substrate bonded to the fifth dielectric layer.

Further, the third vias include through silicon vias.

The present invention also provides a process realization method of a via interconnection structure, comprising the following steps:

Step S1: providing a first substrate;

Step S2: sequentially forming a first metal layer and a second metal layer on the front surface of the first substrate, including forming a plurality of densely distributed first metal structures in the first metal layer, and A plurality of densely distributed second metal structures located on the upper layer of the first metal structure are formed in the second metal layer;

Step S3: forming a fifth dielectric layer on the second metal layer, and bonding a second substrate on the fifth dielectric layer;

Step S4: forming a trench with a pattern of via holes on the back surface of the first substrate, and making the bottom of the trench pass through the front surface of the first substrate to stop at the first metal structure and on the second metal structure;

Step S5: filling the trench with via metal, and filling up the area enclosed by the sidewall of the first metal structure and the process lower surface of the second metal structure, forming a layer and the second metal layer are interconnected by a third via.

Further, the step S2 specifically includes:

sequentially forming a first dielectric layer and a second dielectric layer on the front surface of the first substrate;

forming a first metal interconnection layer as the first metal layer in the second dielectric layer, including forming first interconnection metal lines distributed in an array in rows and columns as the first metal structure;

A third dielectric layer and a fourth dielectric layer are sequentially formed on the second dielectric layer, a second metal interconnection layer serving as the second metal layer is formed in the fourth dielectric layer, and a second metal interconnection layer is formed on the third dielectric layer. forming in the dielectric layer to connect the second via layer between the second metal interconnection layer and the first metal interconnection layer, including forming the second metal structure as the second metal structure distributed in rows and columns to form an array; interconnecting metal lines, and the second via holes in the second via hole layer, and making the second interconnect metal lines overlap with the first interconnect metal lines in rows/columns, And the columns/rows are staggered, so that any one of the second interconnection metal lines is connected to the two first interconnection metal lines on the corresponding two sides of the lower layer through one of the second via holes. , forming a chain structure on the row/column;

The step S4 specifically includes:

Using a mask, etch to form the trench on the back side of the first substrate, and use the etching selectivity to stop the bottom of the trench at the first substrate on the front side of the first substrate. on the medium layer;

forming a liner dielectric layer on the inner wall of the trench;

Use anisotropic dielectric etching to remove the liner dielectric layer on the bottom of the trench, and further remove the first dielectric layer below the trench by using an etching selectivity ratio, so that the trench The bottom of the trench stops on the second dielectric layer, exposing the process lower surface of the first interconnection metal line in the trench region;

Using the etching selectivity, remove the second dielectric layer and the third dielectric layer below the trench, stop the bottom of the trench on the fourth dielectric layer, and expose the trench region The sidewall of the first interconnection metal line, the sidewall of the second via hole and the process lower surface of the second interconnection metal line;

The step S5 specifically includes:

A barrier layer and a seed layer are sequentially formed on the inner wall of the trench, and then a through-hole metal is filled in the trench and planarized to form a through-silicon hole as the third through-hole.

It can be seen from the above technical solution that, without changing the layout and wiring of the metal interconnection layer, the present invention further extends the through-silicon via downwards to form, for example, two layers of metal interconnection layers (first metal interconnection layer, The second metal interconnection layer) and the through hole (second through hole) between them are simultaneously connected, so that the contact area of the through silicon hole is significantly increased by using the metal sidewall and the underlying metal in the vertical direction, and the probability of electromigration failure is reduced. risk. When TSVs are misaligned, using the through holes (second through holes) and the second metal interconnection layer (second metal interconnection layer) can effectively connect and shunt the flow, avoiding the problem caused by the contact area. The problem of excessive current density caused by the reduction. Moreover, the TSV also plays the role of connecting two metal interconnection layers at the same time, so that the current in the contact area of the TSV can be evenly distributed, so there will be no current density caused by the small contact area of a single trench in the past. excessive phenomenon.

Description of drawings

1-2 are schematic diagrams of a via interconnection structure according to the first embodiment of the present invention;

3-4 are schematic diagrams of a via interconnection structure according to the second embodiment of the present invention;

5-6 are schematic diagrams of a via interconnection structure according to the third embodiment of the present invention;

7-8 are schematic diagrams of a via interconnection structure according to a fourth embodiment of the present invention;

FIG. 9 is a flow chart of a process implementation method of a rear TSV interconnection structure according to a preferred embodiment of the present invention;

FIG. 10 is a schematic diagram of a device structure processed by backside TSV photolithography and silicon etching processes according to a preferred embodiment of the present invention;

FIG. 11 is a schematic diagram of the device structure after processing by a sidewall liner oxide layer deposition process in a preferred embodiment of the present invention;

12 is a schematic diagram of the device structure after the etching process for opening the bottom pad oxide layer according to a preferred embodiment of the present invention;

Fig. 13 is a schematic diagram of the device structure processed by a metal layer dielectric etching process according to a preferred embodiment of the present invention;

Fig. 14 is a schematic diagram of the device structure after processing by a TSV copper metallization process according to a preferred embodiment of the present invention;

FIG. 15 is a schematic diagram of an effective contact area of a TSV using a conventional single-layer metal interconnection layer scheme;

FIG. 16 is a schematic diagram of the comparison of the effective contact area of TSVs with the overlay alignment deviation between the present invention and the conventional single-layer metal interconnection layer scheme.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. the embodiment. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. As used herein, "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items.

The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1-FIG. 2 , they show a cross-sectional view and a top view of the same through-hole interconnection structure (the same below). As shown in FIGS. 1-2 , a through-hole interconnection structure of the present invention includes: a third through-hole 103 ′ disposed on the back of the first substrate 100 and a third through-hole 103 ′ disposed on the front of the first substrate 100 in turn. The first metal layer 101' and the second metal layer 102'.

Wherein, the first metal layer 101' includes a plurality of densely distributed first metal structures 1011'; the second metal layer 102' includes a plurality of densely distributed second metal structures 1021' located on the upper layer of the first metal structure 1011' . The so-called upper process layer refers to a process hierarchical structure located relatively upper in the front direction of the first substrate 100 .

The bottom of the third through hole 103' passes through the front surface of the first substrate 100, falls on the first metal structure 1011' and the second metal structure 1021', and fills up the side walls of the first metal structure 1011' and the second metal structure 1021'. The area enclosed by the process lower surface of the two metal structures 1021 ′.

In some embodiments, the first metal layer 101' may include the first metal interconnection layer 101; the second metal layer 102' may include the second metal interconnection layer 102. The first metal structure 1011' may include a first interconnection metal line 1011 in the first metal interconnection layer 101; the second metal structure 1021' may include a second interconnection metal line in the second metal interconnection layer 102 1021.

In some embodiments, the first substrate 100 may be a first wafer substrate or a first wafer substrate. Alternatively, the first substrate 100 may also be a general term for a wafer or any possible process hierarchy above the wafer.

In some embodiments, the first substrate 100 may be a silicon substrate.

Further, the third through hole 103' may be a conductive through silicon hole 103 located on the backside of the silicon substrate.

The following specific embodiments of the present invention will be described in detail below by taking the rear TSV structure as an example.

Refer to Figures 1-2. The first metal interconnection layer 101 includes a group of densely arranged first interconnection metal lines 1011 parallel to each other; the second metal interconnection layer 102 also includes a group of densely arranged second interconnection metal lines 1021 parallel to each other. Moreover, the first interconnection metal lines 1011 and the second interconnection metal lines 1021 are also parallel to each other. At the same time, the first interconnection metal lines 1011 and the second interconnection metal lines 1021 are mutually misaligned in the vertical direction. That is, any one of the second interconnection metal lines 1021 and a corresponding first interconnection metal line 1011 in the lower layer are parallel to each other and arranged in a dislocation. Therefore, in the plan view direction, there is one first interconnection metal line 1011 at the lower position between any two adjacent second interconnection metal lines 1021 .

After passing through the front surface of the first substrate 100, the bottom of the TSV 103 lands on the first metal interconnection layer 101 and the second metal interconnection layer 102, that is, on the first interconnection metal line 1011 and the second metal interconnection layer 102. The two interconnection metal lines 1021 and fill the area surrounded by the projection of the TSV 103 surrounded by the sidewall of the first interconnection metal line 1011 and the process lower surface of the second interconnection metal line 1021 .

Compared with the method (the existing method) in which the through-silicon via 103 only falls on the first metal interconnection layer 101, the above-mentioned through-hole interconnection structure in FIGS. The sidewall of an interconnection metal line 1011 and the area of the gap between adjacent first interconnection metal lines. When the first interconnection metal lines 1011 and the second interconnection metal lines 1021 have the same line width and the gap between the lines, the effective contact area of the through-hole interconnection structure in FIGS. The sum of the projected area of , and the area of the sidewall of the first interconnection metal line 1011 in the region surrounded by the projection.

Refer to Figure 3-Figure 4. The difference between this embodiment and the through-hole interconnection structure shown in FIG. 1-FIG. The included second interconnection metal lines 1021 are also parallel to each other; however, the second interconnection metal lines 1021 and the first interconnection metal lines 1011 are arranged orthogonally to each other, and their projections in the vertical direction form a network shape structure.

After passing through the front surface of the first substrate 100, the bottom of the TSV 103 falls on the first interconnection metal line 1011 and the second interconnection metal line 1021, and fills the area surrounded by the projection of the TSV 103 The region enclosed by the sidewalls of the first interconnection metal lines 1011 and the process lower surface of the second interconnection metal lines 1021 . The effective contact area includes the process lower surface and sidewall of the first interconnection metal line 1011 and the process lower surface of the second interconnection metal line 1021 within the area surrounded by the projection of the TSV 103 .

Compared with the through-hole interconnection structure in Fig. 1-Fig. 2, although the effective contact area of this embodiment is smaller, when the overlay alignment deviation between the first metal interconnection layer 101 and the second metal interconnection layer 102 When changed, the effective contact area does not change.

Refer to Figures 5-6. The difference between this embodiment and the through-hole interconnection structure shown in FIGS. 1-2 and 3-4 is that a second via The hole layer 104 ; the second through hole layer 104 includes a plurality of densely distributed second through holes 1041 .

Moreover, the first interconnection metal lines 1011 and the second interconnection metal lines 1021 no longer form a parallel arrangement structure in the form of long lines, but the first interconnection metal lines 1011 are in the form of short lines An arrangement structure forming an array distribution in rows and columns is formed; the arrangement structure forming an array distribution in rows and columns is also formed in the form of short lines between the second interconnection metal lines 1021 . Each of the first interconnection metal lines 1011 and each of the second interconnection metal lines 1021 are arranged to overlap each other in rows/columns, and are arranged to be staggered in columns/rows. Therefore, in the top view direction, there is one first interconnection metal line 1011 located below any two adjacent second interconnection metal lines 1021 in a row/column.

At the same time, any one of the second interconnection metal lines 1021 on the upper and lower overlapping rows/columns, and the lower layer between the two first interconnection metal lines 1011 on the corresponding sides of the row/column respectively pass through a second via The holes 1041 are connected, so that the second interconnection metal line 1021, the second through hole 1041, the first interconnection metal line 1011, the second through hole 1041, and the second interconnection metal line 1021 are sequentially formed on the row/column. chain-like repeating structure, and thus constitute a chain-like array formed by multiple chain-like structures parallel to each other.

After passing through the front surface of the first substrate 100, the bottom of the TSV 103 falls on the first interconnection metal line 1011 and the second interconnection metal line 1021, and fills the area surrounded by the projection of the TSV 103 The area surrounded by the sidewall of the first interconnection metal line 1011 , the sidewall of the second via hole 1041 and the process lower surface of the second interconnection metal line 1021 .

The TSV 103 interconnection structure in this embodiment, compared with the existing TSV interconnection structure using a single-layer metal interconnection layer scheme, has the same wiring in the projection direction, but increases the contact in the vertical direction area. Moreover, compared with the through-hole interconnection structure in Fig. 1-Fig. 2 and Fig. 3-Fig. A chain array including the second through holes 1041 is sufficient.

Refer to Figures 7-8. The difference between this embodiment and the through-hole interconnection structure shown in FIGS. 101 formed. The first metal structure 1011' includes a first via 1201 in the first via layer 120, and the second metal structure 1021' includes a first interconnection metal line 1011 in the first metal interconnection layer 101. In this embodiment, the second metal interconnection layer 102 for connecting with the TSV 103 in the above-mentioned embodiments is omitted, and the first through-hole layer 120 is added under the process of the first metal interconnection layer 101 . It can also be understood that the second via layer 104 in the embodiment shown in FIGS. 5-6 is moved to the lower layer of the first metal interconnection layer 101 and used as the first via layer 120 in this embodiment.

At the same time, the original parallel wiring of dense lines is still retained between the first interconnection metal lines 1011 of the first metal interconnection layer 101 . The chains of multiple first via holes 1201 are arranged in the same direction as the first interconnection metal lines 1011 between the first via holes 1201 in the first via hole layer 120, and each chain of first via holes 1201 is connected to the first via hole 1201. A corresponding first interconnection metal line 1011 on the upper layer of the process overlaps each other, and each first through hole 1201 in the chain of first through holes 1201 passes through its upper surface of the process and the first interconnection metal line at the corresponding position on the upper layer The lower surface of the 1011 process is connected. That is, a double damascene structure in which a plurality of first through holes 1201 are formed on the filled slot of the first interconnection metal line 1011 is formed.

After passing through the front surface of the first substrate 100, the bottom of the through-silicon via 103 lands on the first through-hole 1201 and the first interconnection metal line 1011, and completely covers the first through-hole in the area surrounded by its projection. through hole 1201 , and fill up the area enclosed by the sidewall of the first through hole 1201 and the process lower surface of the first interconnection metal line 1011 . Compared with the TSV 103 interconnection structure solutions in the other embodiments above, this embodiment does not need to change the wiring of the first metal interconnection layer 101 at all, and can form the first via with the first metal interconnection layer 101 at the same time. The hole layer 120 uses the sidewall of the first through hole 1201 to increase the effective contact area with the TSV 103 .

In some embodiments, a fifth dielectric layer 110 (refer to FIG. 10 ) may also be provided on the second metal interconnection layer 102 on the front side of the first substrate 100, and a second substrate may also be bonded to the fifth dielectric layer 110. Bottom 200.

Further, the second substrate 200 may be bonded with the first substrate 100 to form an integral structure stacked up and down. A three-dimensional integrated circuit structure with interconnections in the vertical direction can thus be formed.

Wherein, the first metal interconnection layer 101 , the second metal interconnection layer 102 , and the fifth dielectric layer 110 all belong to the process hierarchy above the first substrate 100 .

The second substrate may be a second wafer or a second wafer. Alternatively, the second substrate may also be a general term for a wafer or any possible process hierarchy above the wafer.

In the following, a process implementation method of a through-hole interconnection structure of the present invention will be described in detail by means of specific embodiments and in conjunction with the accompanying drawings.

Refer to Figures 10-14 and Figures 1-2. A process realization method of a through-hole interconnection structure of the present invention includes the following steps:

Step S1: providing a first substrate 100;

Step S2: sequentially forming a first metal layer 101' and a second metal layer 102' on the front surface of the first substrate 100, including forming a plurality of densely distributed first metal structures 1011' in the first metal layer 101', and forming a plurality of densely distributed second metal structures 1021' located on the first metal structure 1011' in the second metal layer 102';

Step S3: forming a fifth dielectric layer 110 on the second metal layer 102', and bonding the second substrate 200 on the fifth dielectric layer 110;

Step S4: Form a via hole pattern groove 1031 on the back surface of the first substrate 100, and make the bottom of the groove 1031 pass through the front surface of the first substrate 100, and stop at the first metal structure 1011' and the second metal structure 1011' respectively. on the metal structure 1021';

Step S5: filling the trench 1031 with a through-hole metal, and filling up the area surrounded by the sidewall of the first metal structure 1011' and the process lower surface of the second metal structure 1021', forming a connection with the first metal layer 101' Through silicon vias 103 interconnected with the second metal layer 102'.

Refer to Figures 10-14. In some embodiments, the process implementation method for forming a through-silicon via interconnection structure of the present invention as shown in FIGS. The process implementation method of the connected structure can be understood with reference to this embodiment).

Refer to Figure 10. In step S1, the first substrate 100 may be, for example, a first silicon wafer substrate. The process implementation method of step S2 may specifically include:

Firstly, a deposition process may be used to sequentially form the first dielectric layer 106 and the second dielectric layer 107 with different etching selectivity on the front surface of the first substrate 100 .

Then, the first metal interconnection layer 101 as the first metal layer 101' can be formed in the second dielectric layer 107 by using processes such as photolithography, line trench etching, and metal filling, including forming the first metal structure 1011' A plurality of first interconnection metal lines 1011 distributed in an array are formed in rows and columns.

Next, a deposition process may be used to sequentially form a third dielectric layer 108 and a fourth dielectric layer 109 on the second dielectric layer 107 .

Then, a double damascene process can be used to form the second metal interconnection layer 102 as the second metal layer 102' in the fourth dielectric layer 109, and form a connection between the second metal interconnection layer 102 in the third dielectric layer 108. The second via layer 104 between the first metal interconnection layer 101 includes the second interconnection metal lines 1021 formed as the second metal structure 1021' distributed in an array in rows and columns, and the second via layer 104 The second through hole 1041. And through the layout design, the second interconnection metal lines 1021 and the first interconnection metal lines 1011 can be arranged to overlap on the row/column, and to be arranged in a staggered position on the column/row; at the same time, to make any one of the first interconnection metal lines 1011 The two interconnection metal lines 1021 are respectively connected to the two first interconnection metal lines 1011 located on corresponding two sides of the lower layer through a second via hole 1041 . Thus, a chain structure is formed on the row/column, and thus a chain array formed by a plurality of chain structures parallel to each other is formed.

It should be noted that, when forming the second interconnection metal lines 1021 and the second via holes 1041, the trenches may be formed first, then the via holes are formed, and then the second interconnection metal lines 1021 and the second via holes 1041 may be formed by metal filling. The process order of the via hole 1041 (trench priority) can also be the process sequence of forming the via hole first, then forming the trench, and then forming the second interconnection metal line 1021 and the second via hole 1041 by metal filling (the via hole priority ).

Then, through step S3, the fifth dielectric layer 110 may be firstly formed on the second metal interconnection layer 102 and planarized. Next, the first substrate 100 is bonded to the second substrate 200 through the fifth dielectric layer 110 .

The second substrate 200 may be, for example, a second wafer substrate.

The process implementation method of step S4 and step S5 can be shown in Figure 9, and can specifically include:

(1) Perform TSV photolithography step 301 .

Refer to Figure 10. First, a hard mask film 105 is deposited on the back of the first substrate 100 that has been bonded to the second substrate 200 and has been thinned. Then, glue coating, exposure, and development are performed on the hard mask film 105 to form a photolithography pattern.

In some embodiments, the hard mask film 105 may be formed using silicon oxide.

(2) Execute step 302 of TSV hard mask etching.

Next, the dielectric etching of the hard mask film 105 can be performed by using the photolithography pattern, and the pattern of the TSV is etched on the hard mask film 105 .

(3) Perform silicon via silicon etching step 303 .

The silicon in the first substrate 100 below is etched using the through-silicon hole pattern on the hard mask film 105, and the silicon in the first substrate 100 is etched using an etching gas with a high silicon/silicon oxide selectivity ratio. A trench 1031 with a TSV pattern is formed by etching on the backside of the substrate 100 , and the bottom of the trench 1031 stops on the first dielectric layer 106 on the front side of the first substrate 100 .

The material of the first dielectric layer 106 may be one or more of materials such as silicon oxide/silicon oxycarbide/low dielectric constant material/silicon nitride/silicon carbonitride.

(4) Perform pad oxide layer deposition step 304 .

Refer to Figure 11. A pad oxide layer 111 as a pad dielectric layer can be formed on the inner wall of the trench 1031 by atomic layer deposition or chemical vapor deposition.

In some embodiments, the material of the pad oxide layer 111 may be silicon oxide.

(5) A pad opening etching step 305 is performed.

Refer to Figure 12. An anisotropic dielectric etching process can be used to remove the pad oxide layer 111 on the bottom of the trench 1031, and the first dielectric layer 106 below the trench 1031 can be further removed by using the etching selectivity, so that the bottom of the trench 1031 stop on the second dielectric layer 107 .

Wherein, the first dielectric layer 106 and the second dielectric layer 107 may be composed of more than one different dielectric layers. For example, the material of the first dielectric layer 106 may be silicon oxide, and the material of the second dielectric layer 107 may be sequentially composed of silicon nitride and silicon oxide. In this way, the silicon oxide (first dielectric layer 106) can be removed by using an etching process with a high silicon oxide/silicon nitride selectivity ratio, and stop on the silicon nitride of the second dielectric layer 107, so that the trench 1031 The process lower surface of the first interconnection metal lines 1011 in the region is exposed.

(6) Executing step 306 of etching the metal layer medium with a high selectivity ratio.

Refer to Figure 13. The second dielectric layer 107 and the third dielectric layer 108 located in the first metal interconnection layer 101 and the second via layer 104 under the trench 1031 can be further removed by using an anisotropic dielectric etching process with a higher selectivity Material, so that the bottom of the trench 1031 stops on the fourth dielectric layer 109, exposing the process lower surface and sidewall of the first interconnection metal line 1011 in the trench 1031 area, the sidewall of the second via hole 1041 and the second The process lower surface of the interconnection metal lines 1021 .

In some embodiments, the material of the second dielectric layer 107 and the third dielectric layer 108 can be one or more of materials such as silicon oxide/silicon oxycarbide/low dielectric constant material/silicon nitride/silicon carbonitride , and need to be different from the material of the pad oxide layer 111 on the sidewall of the TSV.

The etching gas used in this process step has an etching rate higher than the etching rate of the pad oxide layer 111 and the fourth dielectric layer 109 to the material of the second dielectric layer 107 and the third dielectric layer 108, and the etching rate The selection ratio can be greater than 10:1, for example, to ensure that the pad oxide layer 111 will not be completely removed during the etching process of the second dielectric layer 107 and the third dielectric layer 108, and stop on the fourth dielectric layer 109 .

When etching the material of the second dielectric layer 107 and the third dielectric layer 108, the inverted trapezoidal shape presented after the second through hole 1041 is turned upside down can be used to expand the material of the third dielectric layer 108 between the second through holes 1041. The process window during etching, so that the medium between the second through holes 1041 can be effectively removed during back etching, ensuring the quality of the interconnection contact.

(7) Perform barrier layer/seed layer deposition step 307 .

Refer to Figure 14. Next, a copper metallization process for the TSV 103 is required. Firstly, a physical vapor deposition process may be used to deposit a barrier layer on the inner wall of the trench 1031 as a diffusion barrier layer for the subsequently filled copper metal.

In some embodiments, the material of the barrier layer may be one or more of materials such as tantalum/tantalum nitride/titanium/titanium nitride.

A copper seed layer can then be deposited on the barrier layer using a physical vapor deposition process.

(8) Execute step 308 of TSV copper electroplating.

Subsequently, a copper electroplating process may be used to fill the through-hole metal copper on the copper seed layer in the trench 1031 .

(9) Execute copper/barrier chemical mechanical polishing step 309 .

Finally, a chemical mechanical polishing process may be used to remove excess copper and barrier material on the back surface of the first substrate 100 and stop on the hard mask film 105 . A final TSV 103 is formed.

It can be seen from FIG. 9 that the metal layer dielectric etching step 306 with a high selectivity ratio in the above process flow is a key process step of the present invention, and is a distinguishing step not involved in the conventional TSV process integration scheme. Compared with the conventional damascene metal layer dielectric etching process, the dielectric etching process used in the present invention has a higher etching selectivity ratio for the metal layer dielectric, and can remove through-silicon vias under the condition of less loss of the pad oxide layer 111 103 is the dielectric between the metal interconnection layers below.

Refer to Figure 15. When a single-layer metal interconnection layer layout is adopted, the TSV 103 falls on the dense lines of the first metal interconnection layer 101, the critical dimension of the bottom of the TSV 103 is assumed to be 4 μm, and the critical dimension of the first interconnection metal line 1011 The size/gap is assumed to be 0.4/0.4 μm respectively, including more than 5 parallel lines to ensure that the TSVs 103 completely land on the dense lines. The effective contact area should be equal to the area of each line surrounded by the TSVs 103 . Assuming that the distance from the axis of symmetry of a single line to the center of the TSV 103 is x, the area enclosed by the line by the TSV 103 can be calculated by the following formula:

Where: h ₁ =x+0.2 μm, h ₂ =x−0.2 μm, r=2 μm, h1/h2 is the distance from both sides of the line to the center of the TSV 103 , and r is the radius of the bottom of the TSV 103 .

When the TSV 103 is placed in the center, there are 5 lines in the area where the TSV 103 falls, that is, the first line x=1.6 μm, the second line x=0.8 μm, and the third line x=0 μm, The fourth line x=0.8 μm, the fifth line x=1.6 μm. At this time, it can be calculated that the effective contact area of each line is 0.95 μm ² , 1.46 μm ² , 1.60 μm ² , 1.46 μm ² , 0.95 μm ² , and the total effective contact area is 6.42 μm ² .

Define the X-direction overlay alignment deviation of the TSV 103 and the first metal interconnection layer 101 as d, then x=|d-1.6|μm for the first line, x=|d-0.8| for the second line μm, the third line x=dμm, the fourth line x=d+0.8 μm, the fifth line x=d+1.6 μm, and so on. When d=0.4 μm, a total of 6 lines are in contact with the TSV 103, and the calculated effective contact area of each line is 0.23 μm ² , 1.27 μm ² , 1.56 μm ² , 1.56 μm ² , 1.27 μm ² , 0.23 μm ² , the total effective contact area is 6.15 μm ² , which is 95.8% of that in the middle. Moreover, at this time, the minimum contact area of a single line is only 0.23 μm ² , which is only 24.2% of the minimum contact area when it is centered, and there is a great risk of electromigration failure.

However, when the interconnection structure described in the first embodiment shown in FIGS. 1-2 of the present invention is adopted, the area where the TSV 103 falls is an effective contact, and the effective contact area also includes the first metal interconnection layer. 101 line sidewall. At this time, the effective contact area on the surface of the first metal interconnection layer 101 and the second metal interconnection layer 102 is equal to the area of the opening of the TSV 103, and the effective contact area of the sidewall is equal to the second area in the area where the TSV 103 falls. The product of the boundary length of the first metal interconnection layer 101 and the depth of the line groove of the first metal interconnection layer 101 . Taking the aforementioned TSV 103 with a critical dimension of 4 μm as an example, the opening area of the TSV 103 is 12.57 μm ² . Assuming that the critical dimensions/gap of the dense lines of the first metal interconnection layer 101 and the second metal interconnection layer 102 are 0.4/0.4 μm respectively, and assuming that the distance from the axis of symmetry of a single line to the center of the TSV 103 is x, then The boundary length of a single line in the area where the TSV 103 falls can be calculated by the following formula:

Where h ₁ =x+0.2 μm, h ₂ =x−0.2 μm, r=2 μm.

When the TSV 103 is placed in the center, the boundary lengths of the above five lines in the area where the TSV 103 falls can be calculated to be 4.60 μm, 7.28 μm, 7.96 μm, 7.28 μm, and 4.60 μm, assuming that the groove depth is 0.3 μm, the effective contact area of the side wall is 9.52 μm ² . Only the sidewall area has exceeded the effective contact area obtained by using the single-layer metal interconnection layer. After adding the surface contact area, the total effective contact area of this interconnection structure has reached 22.09μm ² , which is a single-layer metal interconnection layer. way 3.44 times.

When the Y-direction overlay alignment deviation of the TSV 103 and the first metal interconnection layer 101 is 0.4 μm, the boundary lengths of the above six lines in the area where the TSV 103 falls can be calculated to be 1.74 μm, respectively, 6.32 μm, 7.80 μm, 7.80 μm, 6.32 μm, 1.74 μm. At this time, the effective contact area of the sidewall is still 9.52 μm ² . The total effective contact area is 22.09 μm ² , which is 3.74 times that of the single-layer metal interconnection layer.

The effective contact area of the above two schemes with different overlay alignment deviations is shown in Figure 16. It can be seen that the overlay alignment deviation has a great influence on the effective contact area of the single-layer metal interconnection layer scheme, with a variation of 4.2% ( solid line), while the effective contact area of the TSV interconnection structure solution of the present invention is less affected by overlay alignment deviation, and the variation range is only 1.8% (dashed line).

It can be seen that, adopting the TSV interconnection structure of the present invention can significantly and effectively increase the effective contact area between the TSV and the metal interconnection layer, thereby greatly reducing the current density and having a lower electric current density. Migration failure risk.

Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes are within the scope and spirit of the present invention described in the claims. Furthermore, the invention described herein is capable of other embodiments and of being practiced or carried out in various ways.

Claims (10)

1. A via interconnect structure, comprising:

the third through hole is arranged on the back surface of the first substrate, and the first metal layer and the second metal layer are sequentially arranged on the front surface of the first substrate;

the first metal layer comprises a plurality of densely distributed first metal structures, and the second metal layer comprises a plurality of densely distributed second metal structures which are positioned on the upper layer of the first metal structure technology;

the bottom of the third through hole penetrates through the front surface of the first substrate, falls on the first metal structure and the second metal structure, and fills an area enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure.

2. The via interconnect structure of claim 1, wherein the first metal layer comprises a first metal interconnect layer, wherein the second metal layer comprises a second metal interconnect layer, wherein the first metal structure comprises a first interconnect metal line in the first metal interconnect layer, and wherein the second metal structure comprises a second interconnect metal line in the second metal interconnect layer.

3. The via interconnection structure of claim 2, wherein any one of the second interconnection metal lines is parallel to and offset from a corresponding one of the first interconnection metal lines in a lower layer, and a bottom of the third via, after passing through the front surface of the first substrate, falls on the first interconnection metal line and the second interconnection metal line and fills a region surrounded by a sidewall of the first interconnection metal line and a process lower surface of the second interconnection metal line.

4. The via interconnection structure of claim 2, wherein the first interconnection metal lines are parallel to each other, the second interconnection metal lines are parallel to each other and orthogonal to the first interconnection metal lines, and a bottom of the third via, after passing through the front surface of the first substrate, falls on the first interconnection metal lines and the second interconnection metal lines and fills a region surrounded by sidewalls of the first interconnection metal lines and a process lower surface of the second interconnection metal lines.

5. The via interconnect structure of claim 2, further comprising:

a second via layer disposed between the first metal interconnect layer and the second metal interconnect layer, the second via layer including a plurality of densely-distributed second vias;

the first interconnection metal lines are distributed in an array form by rows and columns, the second interconnection metal lines are distributed in an array form by rows and columns, and are overlapped with the first interconnection metal lines in the rows/columns and are arranged in the rows/columns in a staggered manner;

any one second interconnection metal line on the vertically overlapped row/column is connected with the two first interconnection metal lines on the two corresponding sides of the lower layer through one second through hole respectively, and a chain-shaped structure is formed on the row/column;

and the bottom of the third through hole falls on the first interconnection metal line and the second interconnection metal line after penetrating through the front surface of the first substrate, and fills a region surrounded by the side wall of the first interconnection metal line, the side wall of the second through hole and the process lower surface of the second interconnection metal line.

6. The via interconnect structure of claim 1, wherein the first metal layer comprises a first via layer, the second metal layer comprises a first metal interconnect layer, the first metal structure comprises a first via in the first via layer, the second metal structure comprises a first interconnect metal line in the first metal interconnect layer; and the bottom of the third through hole falls on the first through hole and the first interconnection metal line after penetrating through the front surface of the first substrate, and fills a region enclosed by the side wall of the first through hole and the process lower surface of the first interconnection metal line.

7. The via interconnect structure of claim 1, further comprising: the second substrate is bonded on the fifth dielectric layer.

8. The via interconnect structure of claim 1, wherein the third via comprises a through silicon via.

9. A process implementation method of a through hole interconnection structure is characterized by comprising the following steps:

step S1: providing a first substrate;

step S2: sequentially forming a first metal layer and a second metal layer on the front surface of the first substrate, wherein the forming of the first metal structure in the first metal layer and the forming of the second metal structure in the second metal layer are positioned on the upper layer of the first metal structure;

and step S3: forming a fifth dielectric layer on the second metal layer, and bonding a second substrate on the fifth dielectric layer;

and step S4: forming a through hole pattern groove on the back surface of the first substrate, and enabling the bottom of the groove to penetrate through the front surface of the first substrate and respectively stop on the first metal structure and the second metal structure;

step S5: and filling the groove with through hole metal, filling the area enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure, and forming a third through hole interconnected with the first metal layer and the second metal layer.

10. The method for realizing the process of the via interconnection structure according to claim 9, wherein the step S2 specifically comprises:

sequentially forming a first dielectric layer and a second dielectric layer on the front surface of the first substrate;

forming a first metal interconnection layer serving as the first metal layer in the second dielectric layer, wherein the first metal interconnection layer comprises first interconnection metal lines serving as the first metal structures and distributed in an array formed by rows and columns;

sequentially forming a third dielectric layer and a fourth dielectric layer on the second dielectric layer, forming a second metal interconnection layer serving as the second metal layer in the fourth dielectric layer, and forming a second through hole layer connected between the second metal interconnection layer and the first metal interconnection layer in the third dielectric layer, wherein the second metal interconnection layer comprises second interconnection metal lines and second through holes in the second through hole layer, the second interconnection metal lines and the first interconnection metal lines are formed as the second metal structures and distributed in an array manner according to rows and columns, the second interconnection metal lines and the first interconnection metal lines are overlapped in the rows/columns and are arranged in the staggered manner in the rows/columns, any one of the second interconnection metal lines is connected with two first interconnection metal lines on two corresponding sides of the lower layer through one of the second through holes, and a chain-shaped structure is formed in the rows/columns;

the step S4 specifically includes:

etching the back surface of the first substrate by using a mask to form the groove, and stopping the bottom of the groove on the first dielectric layer on the front surface of the first substrate by using an etching selection ratio;

forming a liner dielectric layer on the inner wall of the groove;

removing the liner dielectric layer on the bottom of the groove by using anisotropic dielectric etching, and further removing the first dielectric layer below the groove by using an etching selection ratio to stop the bottom of the groove on the second dielectric layer and expose the process lower surface of the first interconnection metal line in the groove region;

removing the second dielectric layer and the third dielectric layer below the trench by using an etching selection ratio, so that the bottom of the trench is stopped on the fourth dielectric layer, and the side wall of the first interconnection metal line, the side wall of the second through hole and the process lower surface of the second interconnection metal line in the trench region are exposed;

the step S5 specifically includes:

and sequentially forming a barrier layer and a seed crystal layer on the inner wall of the groove, then filling through hole metal in the groove, and flattening to form a silicon through hole serving as the third through hole.

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