CN115799212A - Through hole interconnection structure and process implementation method thereof - Google Patents
Through hole interconnection structure and process implementation method thereof Download PDFInfo
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Abstract
The invention discloses a through hole interconnection structure and a process realization method thereof, wherein the through hole interconnection structure comprises the following components: the third through hole is arranged on the back surface of the first substrate, and the first metal layer and the second metal layer are sequentially arranged on the front surface of the first substrate; the first metal layer comprises a plurality of densely distributed first metal structures, and the second metal layer comprises a plurality of densely distributed second metal structures which are positioned on the upper layer of the first metal structure technology; and the bottom of the third through hole penetrates through the front surface of the first substrate, falls on the first metal structure and the second metal structure, and fills a region enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure. The invention can obviously and effectively increase the effective contact area between the silicon through hole and the metal interconnection layer, thereby greatly reducing the current density and having lower electromigration failure risk.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit processes, in particular to a through silicon via interconnection structure and a process implementation method thereof.
Background
The three-dimensional integrated circuit refers to a three-dimensional integrated circuit structure formed by stacking chips with interconnections in the vertical direction. With the increasing integration of chips, the physical limit has been approached by simply reducing the critical dimension of the semiconductor device. In order to achieve higher integration and device capacity, three-dimensional integrated circuit technology is increasingly applied to the field of chip manufacturing. Compared with a two-dimensional integrated circuit, the three-dimensional integrated circuit has the advantages of greatly shortened interconnection length, higher bandwidth, lower parasitic capacitance and interconnection delay, lower power consumption and the like.
Through-silicon-vias refer to metal vias formed through a silicon substrate by integrated circuit fabrication techniques such as photolithography and etching. The silicon through hole is the core of the three-dimensional integration technology, is used as a bridge between a circuit on the back side of the silicon chip and a circuit on the front side of the silicon chip, can reduce lead resistance between chips of the three-dimensional integrated circuit, and reduces power consumption.
In the prior art, the process segment of through-silicon-via processing can be divided into a first through-hole process, a middle through-hole process and a last through-hole process, and the difference is that the through-silicon-via is formed before and after the last process or after the wafer is stacked and thinned. Also, according to the through-silicon-via manufacturing process, it can be divided into a front through-silicon-via and a back through-silicon-via. The front silicon through hole is formed by photoetching and etching on the front surface (device surface) of a wafer, and the front silicon through hole comprises two integration schemes of a through hole first process and a through hole middle process. The back side through-silicon-via is formed by performing photolithography and etching on the back side (substrate side) of the wafer after the wafers are stacked, and belongs to a through-hole post-processing technology. The front-side through-silicon-via needs to be communicated with the front-side circuit and the back-side circuit through stacking, back-side thinning and silicon copper exposure processes. The backside through-silicon-via is formed by etching an opening directly from the backside of the wafer to connect the front side circuit, and the process complexity is relatively low. However, the back silicon through hole needs to penetrate through the thick silicon substrate to be communicated with the back metal layer on the front side, so that the requirements on photoetching alignment and etching processes are higher.
The back-side through-silicon-via process requires the effective interconnection of circuits to be completed through the back-end metal wiring of the wafer. Due to the process difficulty, the first metal line closest to the silicon substrate is generally selected for connection. However, due to the limitation of the design rule of the first layer of metal wires, the first layer of metal wires cannot cover the complete large-size through-silicon-vias, and usually only a plurality of meshed metal wires are used to connect the through-silicon-vias for layout and routing, and then the first layer of metal wires are connected to the second layer of metal wires and other metal layers through the through-holes.
According to the requirements of different devices on the well depth, along with the increase of the thickness of the silicon substrate, the precision of aligning the front layer through the back surface is reduced, and the problem of larger overlay alignment deviation can occur. Meanwhile, due to the inclined angle formed by etching and the existence of the side wall liner medium, the bottom of the silicon through hole often has an obvious size shrinkage phenomenon. The above reasons all lead to the reduction of effective area when the through-silicon via is connected with the first layer of metal connecting wire, and can be because of the connection part current density is too big, greatly increased electromigration inefficacy's risk.
In addition, the large-sized silicon through hole is connected with the metal connecting line with relatively small line width, and when a large current flows through the silicon through hole, the contact area of each metal connecting line is relatively small, the density of the flowing current is relatively overlarge, and the risk of electromigration failure is increased greatly.
The width of each conductive trench for filling the metal line cannot exceed the maximum specification due to the design rule, and thus the effect of improving the current density by increasing the trench width is limited.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a through hole interconnection structure and a process implementation method thereof.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the present invention provides a via interconnect structure comprising:
the third through hole is formed in the back surface of the first substrate, and the first metal layer and the second metal layer are sequentially arranged on the front surface of the first substrate;
the first metal layer comprises a plurality of densely distributed first metal structures, and the second metal layer comprises a plurality of densely distributed second metal structures which are positioned on the upper layer of the first metal structure technology;
and the bottom of the third through hole penetrates through the front surface of the first substrate, falls on the first metal structure and the second metal structure, and fills a region enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure.
Further, the first metal layer includes a first metal interconnection layer, the second metal layer includes a second metal interconnection layer, the first metal structure includes a first interconnection metal line in the first metal interconnection layer, and the second metal structure includes a second interconnection metal line in the second metal interconnection layer.
Furthermore, any one of the second interconnection metal lines is parallel to and staggered with the corresponding first interconnection metal line of the lower layer, and the bottom of the third through hole, after penetrating through the front surface of the first substrate, falls on the first interconnection metal line and the second interconnection metal line and fills the area enclosed by the side wall of the first interconnection metal line and the process lower surface of the second interconnection metal line.
Furthermore, the first interconnection metal lines are parallel to each other, the second interconnection metal lines are parallel to each other and orthogonal to the first interconnection metal lines, and the bottom of the third through hole falls on the first interconnection metal lines and the second interconnection metal lines after penetrating through the front surface of the first substrate, and fills an area enclosed by the side wall of the first interconnection metal line and the process lower surface of the second interconnection metal line.
Further, still include:
a second via layer disposed between the first metal interconnect layer and the second metal interconnect layer, the second via layer including a plurality of densely distributed second vias;
the first interconnection metal lines are distributed in an array form by rows and columns, the second interconnection metal lines are distributed in an array form by rows and columns, and are overlapped with the first interconnection metal lines in the rows/columns and are arranged in the rows/columns in a staggered manner;
any one second interconnection metal line on the vertically overlapped row/column is connected with the two first interconnection metal lines on the two corresponding sides of the lower layer through one second through hole respectively, and a chain-shaped structure is formed on the row/column;
and the bottom of the third through hole falls on the first interconnection metal line and the second interconnection metal line after penetrating through the front surface of the first substrate, and fills a region surrounded by the side wall of the first interconnection metal line, the side wall of the second through hole and the process lower surface of the second interconnection metal line.
Further, the first metal layer comprises a first via layer, the second metal layer comprises a first metal interconnection layer, the first metal structure comprises a first via in the first via layer, and the second metal structure comprises a first interconnection metal line in the first metal interconnection layer; and the bottom of the third through hole falls on the first through hole and the first interconnection metal line after penetrating through the front surface of the first substrate, and fills a region enclosed by the side wall of the first through hole and the process lower surface of the first interconnection metal line.
Further, the method also comprises the following steps: the second substrate is bonded on the fifth dielectric layer.
Further, the third via comprises a through silicon via.
The invention also provides a process implementation method of the through hole interconnection structure, which comprises the following steps:
step S1: providing a first substrate;
step S2: sequentially forming a first metal layer and a second metal layer on the front surface of the first substrate, wherein the forming of the first metal structure in the first metal layer and the forming of the second metal structure in the second metal layer are positioned on the upper layer of the first metal structure;
and step S3: forming a fifth dielectric layer on the second metal layer, and bonding a second substrate on the fifth dielectric layer;
and step S4: forming a through hole pattern groove on the back surface of the first substrate, and enabling the bottom of the groove to penetrate through the front surface of the first substrate and respectively stop on the first metal structure and the second metal structure;
step S5: and filling the groove with through hole metal, filling the area enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure, and forming a third through hole interconnected with the first metal layer and the second metal layer.
Further, the step S2 specifically includes:
sequentially forming a first dielectric layer and a second dielectric layer on the front surface of the first substrate;
forming a first metal interconnection layer serving as the first metal layer in the second dielectric layer, wherein the first metal interconnection layer comprises first interconnection metal lines which are formed and distributed in an array manner according to rows and columns and serve as the first metal structure;
sequentially forming a third dielectric layer and a fourth dielectric layer on the second dielectric layer, forming a second metal interconnection layer serving as the second metal layer in the fourth dielectric layer, and forming a second through hole layer connected between the second metal interconnection layer and the first metal interconnection layer in the third dielectric layer, wherein the second metal interconnection layer comprises second interconnection metal lines and second through holes in the second through hole layer, the second interconnection metal lines and the first interconnection metal lines are formed as the second metal structures and distributed in an array manner according to rows and columns, the second interconnection metal lines and the first interconnection metal lines are overlapped in the rows/columns and are arranged in the staggered manner in the rows/columns, any one of the second interconnection metal lines is connected with two first interconnection metal lines on two corresponding sides of the lower layer through one of the second through holes, and a chain-shaped structure is formed in the rows/columns;
the step S4 specifically includes:
etching the back surface of the first substrate by using a mask to form the groove, and stopping the bottom of the groove on the first dielectric layer on the front surface of the first substrate by using an etching selection ratio;
forming a liner dielectric layer on the inner wall of the groove;
removing the liner dielectric layer on the bottom of the groove by using anisotropic dielectric etching, and further removing the first dielectric layer below the groove by using an etching selection ratio to stop the bottom of the groove on the second dielectric layer and expose the process lower surface of the first interconnection metal line in the groove region;
removing the second dielectric layer and the third dielectric layer below the trench by using an etching selection ratio, so that the bottom of the trench is stopped on the fourth dielectric layer, and the side wall of the first interconnection metal line, the side wall of the second through hole and the process lower surface of the second interconnection metal line in the trench region are exposed;
the step S5 specifically includes:
and sequentially forming a barrier layer and a seed crystal layer on the inner wall of the groove, then filling through hole metal in the groove, and flattening to form a silicon through hole serving as the third through hole.
According to the technical scheme, under the condition that the layout and wiring of the metal interconnection layers are not changed, the silicon through holes further extend downwards to form simultaneous connection with, for example, two metal interconnection layers (a first metal interconnection layer and a second metal interconnection layer) and through holes (second through holes) between the two metal interconnection layers, so that the contact area of the silicon through holes is remarkably increased by using the metal side walls in the vertical direction and the lower layer metal, and the risk of electromigration failure is reduced. When the silicon through holes are aligned and deviated, the through holes (second through holes) and the second metal interconnection layer (second metal interconnection layer) can play an effective connection and shunt role, and the problem of overlarge current density caused by reduction of contact area is avoided. In addition, the silicon through hole also plays a role of simultaneously connecting two metal interconnection layers, so that the current of a contact area of the silicon through hole is uniformly distributed, and the phenomenon of overlarge current density caused by smaller contact area of a single groove in the prior art can be avoided.
Drawings
Fig. 1-2 are schematic views of a via interconnect structure according to a first embodiment of the present invention;
FIGS. 3-4 are schematic views of a via interconnect structure according to a second embodiment of the present invention;
FIGS. 5-6 are schematic views of a via interconnect structure according to a third embodiment of the present invention;
fig. 7-8 are schematic views of a via interconnect structure according to a fourth embodiment of the present invention;
FIG. 9 is a flow chart of a method for implementing the backside TSV interconnect structure in accordance with a preferred embodiment of the present invention;
FIG. 10 is a schematic diagram of a device structure after backside TSV lithography and silicon etching processes are performed in accordance with a preferred embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating a device structure after a sidewall spacer oxide deposition process in accordance with a preferred embodiment of the present invention;
FIG. 12 is a schematic diagram of a device structure after a bottom pad oxide open etch process in accordance with a preferred embodiment of the present invention;
FIG. 13 is a schematic structural diagram of a device after being processed by a metal layer dielectric etching process according to a preferred embodiment of the present invention;
FIG. 14 is a schematic diagram illustrating a device structure after a through-silicon-via copper metallization process in accordance with a preferred embodiment of the present invention;
FIG. 15 is a schematic diagram of an effective contact area of a through silicon via using a conventional single metal interconnect layer scheme;
fig. 16 is a graph comparing the effective contact area of the through-silicon via with the overlay alignment deviation between the present invention and a conventional single metal interconnect layer scheme.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
The following provides a more detailed description of embodiments of the present invention, with reference to the accompanying drawings.
Referring to fig. 1-2, shown are cross-sectional and top views (the same below) of the same via interconnect structure. As shown in fig. 1 to 2, a via interconnection structure of the present invention includes: a third via 103' provided on the back surface of the first substrate 100, and a first metal layer 101' and a second metal layer 102' provided on the front surface of the first substrate 100 in this order.
Wherein the first metal layer 101 'includes a plurality of densely distributed first metal structures 1011'; second metal layer 102' includes a plurality of densely distributed second metal structures 1021' situated as an upper process layer of first metal structures 1011 '. The process upper layer refers to a process hierarchy located at an upper layer in the front surface direction of the first substrate 100.
The bottom of the third via 103' penetrates the front surface of the first substrate 100, falls on the first metal structure 1011' and the second metal structure 1021', and fills the area enclosed by the sidewall of the first metal structure 1011' and the process bottom surface of the second metal structure 1021'.
In some embodiments, first metal layer 101' may include a first metal interconnect layer 101; the second metal layer 102' may include a second metal interconnect layer 102. The first metal structure 1011' may comprise a first interconnect metal line 1011 located in the first metal interconnect layer 101; the second metal structure 1021' may comprise a second interconnect metal line 1021 in the second metal interconnect layer 102.
In some embodiments, the first substrate 100 may be a first wafer substrate or a first chip substrate. Alternatively, the first substrate 100 may be a generic term for a wafer or chip and any possible process level structures thereon.
In some embodiments, the first substrate 100 may be a silicon substrate.
Further, the third via 103' may be a conductive through silicon via 103 located on the backside of the silicon substrate.
The following embodiments of the present invention will be described in detail by taking a backside tsv structure as an example.
Refer to fig. 1-2. Wherein the first metal interconnection layer 101 comprises a set of densely arranged first interconnection metal lines 1011 parallel to each other; the second metal interconnection layer 102 also includes a set of densely packed second interconnection metal lines 1021 that are parallel to each other. The first interconnection metal line 1011 and the second interconnection metal line 1021 are also parallel to each other. Meanwhile, the first interconnection metal line 1011 and the second interconnection metal line 1021 are arranged in a vertically staggered manner. That is, any one of the second interconnection metal lines 1021 and a corresponding one of the first interconnection metal lines 1011 in the lower layer are parallel to each other and are arranged in a staggered manner. Thus, in a top view, a first interconnection metal line 1011 is disposed at a lower position between any two adjacent second interconnection metal lines 1021.
The bottom of the through-silicon via 103, after passing through the front surface of the first substrate 100, falls on the first metal interconnection layer 101 and the second metal interconnection layer 102, i.e. on the first interconnection metal line 1011 and the second interconnection metal line 1021, and fills the area surrounded by the sidewall of the first interconnection metal line 1011 and the process bottom surface of the second interconnection metal line 1021 in the area surrounded by the projection of the through-silicon via 103.
Compared with the method (conventional method) in which the through-silicon via 103 is only located on the first metal interconnection layer 101, the above-described through-hole interconnection structure of fig. 1-2 utilizes the sidewall of the first interconnection metal line 1011 in the first metal interconnection layer 101 and the area of the gap between adjacent first interconnection metal lines. When the line widths and the gaps between the lines of the first interconnection metal line 1011 and the second interconnection metal line 1021 are the same, the effective contact area of the via interconnection structure of fig. 1-2 reaches the maximum, which is equal to the sum of the projected area of the through-silicon via 103 and the area of the sidewall of the first interconnection metal line 1011 in the area surrounded by the projection.
Refer to fig. 3-4. The difference between the present embodiment and the via interconnection structure of fig. 1-2 is that the first interconnection metal lines 1011 included in the first metal interconnection layer 101 are parallel to each other, and the second interconnection metal lines 1021 included in the second metal interconnection layer 102 are also parallel to each other; however, the second interconnection metal lines 1021 and the first interconnection metal lines 1011 are orthogonal to each other, and their projections in the vertical direction form a mesh structure.
After passing through the front surface of the first substrate 100, the bottom of the through-silicon via 103 falls on the first interconnection metal line 1011 and the second interconnection metal line 1021, and fills the area surrounded by the sidewall of the first interconnection metal line 1011 and the process bottom surface of the second interconnection metal line 1021 in the area surrounded by the projection of the through-silicon via 103. The effective contact area includes the process bottom surface and the sidewall of the first interconnect metal line 1011 in the area surrounded by the projection of the through-silicon via 103, and the process bottom surface of the second interconnect metal line 1021.
Although the effective contact area is smaller in this embodiment compared to the via interconnection structures of fig. 1-2, the effective contact area does not change when the overlay alignment deviation between the first metal interconnection layer 101 and the second metal interconnection layer 102 changes.
Refer to fig. 5-6. The difference between this embodiment and the via interconnection structures in fig. 1-2 and fig. 3-4 is that a second via layer 104 is further disposed between the first metal interconnection layer 101 and the second metal interconnection layer 102; the second via layer 104 includes a plurality of densely distributed second vias 1041.
Moreover, the arrangement structures which are parallel to each other are not formed between the first interconnection metal lines 1011 and between the second interconnection metal lines 1021 in a long line form any more, but the arrangement structures which are distributed in an array form by rows and columns are formed between the first interconnection metal lines 1011 in a short line form; the second interconnection metal lines 1021 are also arranged in short lines in an array of rows and columns. The first interconnection metal lines 1011 and the second interconnection metal lines 1021 are arranged in a row/column overlapping manner, and are arranged in a column/row staggered manner. Thus, in a top view, a first interconnection metal line 1011 is disposed at a lower position between any two adjacent second interconnection metal lines 1021 in the same row/column.
Meanwhile, any one of the second interconnecting metal lines 1021 on the vertically overlapped rows/columns is connected with the two first interconnecting metal lines 1011 on the lower layer on the corresponding two sides of the same row/column through a second through hole 1041, so that a chain-like repeating structure formed by sequentially connecting the second interconnecting metal lines 1021, the second through holes 1041, the first interconnecting metal lines 1011, the second through holes 1041 and the second interconnecting metal lines 1021 on the rows/columns is formed, and a chain-like array formed by a plurality of chain-like structures in parallel is formed.
The bottom of the through silicon via 103, after passing through the front surface of the first substrate 100, falls on the first interconnection metal line 1011 and the second interconnection metal line 1021, and fills the area surrounded by the sidewall of the first interconnection metal line 1011, the sidewall of the second via 1041, and the process bottom surface of the second interconnection metal line 1021 in the area surrounded by the projection of the through silicon via 103.
Compared with the existing through silicon via interconnection structure adopting a single-layer metal interconnection layer scheme, the through silicon via 103 interconnection structure in the embodiment has the same wiring in the projection direction, but increases the contact area in the vertical direction. In addition, compared with the via interconnection structures shown in fig. 1-2 and fig. 3-4, in this embodiment, the wiring of the metal interconnection layer does not need to be changed, and only the interconnection metal lines need to be changed from densely arranged parallel lines to a chain-like array including the second vias 1041.
Refer to fig. 7-8. The difference between this embodiment and the via interconnect structure of fig. 1-2 is that the first metal layer 101 'takes the form of the first via layer 120 structure, and the second metal layer 102' is formed with the first metal interconnect layer 101. First metal structure 1011 'comprises a first via 1201 in first via layer 120 and second metal structure 1021' comprises a first interconnect metal line 1011 in first metal interconnect layer 101. The second metal interconnection layer 102 for connecting with the through silicon via 103 in the above embodiment is omitted, and the first via layer 120 is added below the first metal interconnection layer 101. It is also understood that the second via layer 104 in the embodiment of fig. 5-6 is moved to a position under the process of the first metal interconnect layer 101 and serves as the first via layer 120 in this embodiment.
Meanwhile, the original dense parallel line routing manner still remains among the first interconnection metal lines 1011 of the first metal interconnection layer 101. A plurality of chains of first vias 1201 are arranged between the first vias 1201 in the first via layer 120 in the same direction as the first interconnection metal lines 1011, each chain of first vias 1201 overlaps a corresponding first interconnection metal line 1011 located on an upper layer of the process, and each first via 1201 in the chain of first vias 1201 is connected to the lower surface of the first interconnection metal line 1011 on a corresponding position on the upper layer through the upper surface of the chain. That is, a dual damascene structure in which a plurality of first vias 1201 are disposed in the filling line groove of the first interconnection metal line 1011 is formed.
After passing through the front surface of the first substrate 100, the bottom of the through-silicon via 103 falls on the first via 1201 and the first interconnection metal line 1011, completely covers the first via 1201 in the area surrounded by the projection thereof, and fills the area surrounded by the sidewall of the first via 1201 and the process lower surface of the first interconnection metal line 1011. Compared with the interconnection structure scheme of the through silicon via 103 in the other embodiments, the present embodiment does not need to change the wiring of the first metal interconnection layer 101 at all, and can increase the effective contact area with the through silicon via 103 by using the sidewall of the first via 1201 in a manner of forming the first via layer 120 simultaneously with the first metal interconnection layer 101.
In some embodiments, a fifth dielectric layer 110 (see fig. 10) may be further disposed on the second metal interconnection layer 102 on the front surface of the first substrate 100, and a second substrate 200 may be further bonded to the fifth dielectric layer 110.
Further, the second substrate 200 may be bonded to the first substrate 100 to form a stacked structure. Thereby forming a three-dimensional integrated circuit structure having interconnects in a vertical direction.
The first metal interconnection layer 101, the second metal interconnection layer 102, the fifth dielectric layer 110, and the like all belong to a process hierarchy structure above the first substrate 100.
The second substrate may be a second wafer or a second die. Alternatively, the second substrate may be a wafer or chip and any possible process level structure thereon.
The process implementation method of the via interconnection structure according to the present invention is described in detail below with reference to the accompanying drawings.
Reference is made to fig. 10-14 and fig. 1-2. The invention discloses a process implementation method of a through hole interconnection structure, which comprises the following steps of:
step S1: providing a first substrate 100;
step S2: sequentially forming a first metal layer 101' and a second metal layer 102' on the front surface of the first substrate 100, including forming a plurality of densely-distributed first metal structures 1011' in the first metal layer 101', and forming a plurality of densely-distributed second metal structures 1021' on top of the first metal structures 1011' in the second metal layer 102 ';
and step S3: forming a fifth dielectric layer 110 on the second metal layer 102', and bonding a second substrate 200 on the fifth dielectric layer 110;
and step S4: forming a via pattern trench 1031 on the back surface of the first substrate 100, and causing the bottom of the trench 1031 to penetrate the front surface of the first substrate 100, stopping on the first metal structure 1011 'and the second metal structure 1021', respectively;
step S5: the trench 1031 is filled with via metal, and the sidewall of the first metal structure 1011 'and the area surrounded by the process bottom surface of the second metal structure 1021' are filled with via metal, so as to form a through silicon via 103 interconnected with the first metal layer 101 'and the second metal layer 102'.
Refer to fig. 10-14. In some embodiments, a process implementation method for forming a through silicon via interconnect structure of the present invention as shown in fig. 5-6 is described as an example (for the process implementation methods of the through silicon via interconnect structures in the other embodiments, it can be understood with reference to this embodiment).
Refer to fig. 10. In step S1, the first substrate 100 may be, for example, a first silicon wafer substrate. The process implementation method of the step S2 may specifically include:
first, a first dielectric layer 106 and a second dielectric layer 107 having different etching selection ratios may be sequentially formed on the front surface of the first substrate 100 using a deposition process.
Then, processes such as photolithography, line trench etching, and metal filling may be used to form the first metal interconnection layer 101 as the first metal layer 101 'in the second dielectric layer 107, including forming a plurality of first interconnection metal line 1011 patterns distributed in an array formed by rows and columns as the first metal structure 1011'.
Next, a deposition process may be used to sequentially form a third dielectric layer 108 and a fourth dielectric layer 109 on the second dielectric layer 107.
Then, a dual damascene process may be used to form the second metal interconnection layer 102 as a second metal layer 102 'in the fourth dielectric layer 109, and form the second via layer 104 in the third dielectric layer 108 to connect between the second metal interconnection layer 102 and the first metal interconnection layer 101, including forming the second interconnection metal lines 1021 as a second metal structure 1021' arranged in a row-column formation array, and forming the second vias 1041 in the second via layer 104. Through layout design, the second interconnection metal line 1021 and the first interconnection metal line 1011 are arranged in a row/column overlapping manner and arranged in a column/row staggered manner; meanwhile, any one of the second interconnection metal lines 1021 and two first interconnection metal lines 1011 located on two corresponding sides of the lower layer are connected through a second via hole 1041. Thereby forming a chain-like structure on the rows/columns and thus constituting a chain-like array formed by a plurality of chain-like structures in parallel with each other.
It should be noted that, when forming the second interconnection metal line 1021 and the second via 1041, a process sequence of forming a trench first and then forming a via, and then forming the second interconnection metal line 1021 and the second via 1041 through metal filling (trench is preferred), or a process sequence of forming a via first and then forming a trench, and then forming the second interconnection metal line 1021 and the second via 1041 through metal filling (via is preferred) may be adopted.
Then, in step S3, a fifth dielectric layer 110 may be formed on the second metal interconnection layer 102 and planarized. Next, first substrate 100 is bonded to second substrate 200 through fifth dielectric layer 110.
The second substrate 200 may be, for example, a second wafer substrate.
The process implementation method of step S4 and step S5 may be as shown in fig. 9, and may specifically include:
(1) A through silicon via lithography step 301 is performed.
Refer to fig. 10. First, the hard mask film 105 deposition is performed on the back surface of the first substrate 100 which has been bonded to the second substrate 200 and subjected to back surface thinning. Then, resist coating, exposure, and development are performed on the hard mask film 105 to form a lithographic pattern.
In some embodiments, the hard mask film 105 may be formed using silicon oxide.
(2) A through silicon via hard mask etch step 302 is performed.
Next, a dielectric etching of the hard mask film 105 may be performed using the photolithography pattern to etch a pattern of through silicon vias on the hard mask film 105.
(3) A through silicon via silicon etch step 303 is performed.
The silicon in the underlying first substrate 100 is etched using the through-silicon via pattern provided on the hard mask film 105, and a trench 1031 having a through-silicon via pattern is etched on the back surface of the first substrate 100 using an etching gas having a high silicon/silicon oxide selectivity, such that the bottom of the trench 1031 is stopped on the first dielectric layer 106 on the front surface of the first substrate 100.
The first dielectric layer 106 may be one or more of silicon oxide/silicon oxycarbide/low-k material/silicon nitride/silicon carbonitride.
(4) A liner oxide deposition step 304 is performed.
Refer to fig. 11. A pad oxide layer 111 as a pad dielectric layer may be formed on the inner wall of the trench 1031 by an atomic layer deposition or chemical vapor deposition process.
In some embodiments, the pad oxide layer 111 material may be silicon oxide.
(5) A liner open etch step 305 is performed.
Refer to fig. 12. The pad oxide layer 111 at the bottom of the trench 1031 may be removed by an anisotropic dielectric etch process, and the first dielectric layer 106 under the trench 1031 may be further removed by using an etch selectivity, so that the bottom of the trench 1031 is stopped on the second dielectric layer 107.
The first dielectric layer 106 and the second dielectric layer 107 may be composed of more than one different dielectric layers. For example, the material of the first dielectric layer 106 may be silicon oxide, and the material of the second dielectric layer 107 may be sequentially composed of silicon nitride and silicon oxide. Thus, by using an etching process with a high silicon oxide/silicon nitride selectivity, silicon oxide (first dielectric layer 106) can be removed and stopped on the silicon nitride of the second dielectric layer 107, thereby exposing the process lower surface of the first interconnection metal line 1011 in the region of the trench 1031.
(6) A high selectivity metal layer dielectric etch step 306 is performed.
Refer to fig. 13. The second dielectric layer 107 and the third dielectric layer 108 in the first metal interconnection layer 101 and the second via layer 104 under the trench 1031 may be further removed by using a dielectric etching process with higher selectivity anisotropy, so that the bottom of the trench 1031 is stopped on the fourth dielectric layer 109, and the process lower surface and the sidewalls of the first interconnection metal line 1011, the sidewalls of the second via 1041, and the process lower surface of the second interconnection metal line 1021 in the region of the trench 1031 are exposed.
In some embodiments, the second dielectric layer 107 and the third dielectric layer 108 may be one or more of silicon oxide/silicon oxycarbide/low-k material/silicon nitride/silicon carbonitride, etc., and need to be different from the liner oxide layer 111 on the sidewall of the through silicon via.
The etching gas used in the process step has an etching rate higher than the etching rates of the materials of the second dielectric layer 107 and the third dielectric layer 108 than the etching rates of the liner oxide layer 111 and the fourth dielectric layer 109, and the etching rate selection ratio is, for example, greater than 10.
When the second dielectric layer 107 and the third dielectric layer 108 are etched, the inverted trapezoid shape of the second through hole 1041 after being turned upside down can be used to enlarge the process window when the third dielectric layer 108 between the second through holes 1041 is etched, so that the dielectric between the second through holes 1041 can be effectively removed when the back etching is performed, and the interconnection contact quality is ensured.
(7) A barrier/seed layer deposition step 307 is performed.
Refer to fig. 14. A copper metallization process of the through-silicon via 103 is required next. First, a physical vapor deposition process may be used to deposit a barrier layer on the inner walls of the trench 1031 as a diffusion barrier layer for the subsequently filled copper metal.
In some embodiments, the barrier layer material may be one or more of tantalum/tantalum nitride/titanium nitride, and the like.
A copper seed layer may then be deposited on the barrier layer using a physical vapor deposition process.
(8) A through-silicon via copper plating step 308 is performed.
Subsequently, a copper electroplating process may be used to fill the copper via metal on the copper seed layer in the trench 1031.
(9) A copper/barrier layer chemical mechanical polishing step 309 is performed.
Finally, a chemical mechanical polishing process may be used to remove excess copper and barrier material from the backside surface of the first substrate 100 and stop on the hard mask film 105. Resulting in the formation of a final through-silicon via 103.
As can be seen from fig. 9, the metal layer dielectric etching step 306 with high selectivity in the above process flow is a key process step of the present invention, and is a distinct step not involved in the conventional backside tsv process integration scheme. Compared with the conventional Damascus metal layer medium etching process, the medium etching process used by the invention has higher etching selection ratio to the metal layer medium, and can remove the medium between the metal interconnection layers below the silicon through hole 103 under the condition of less loss of the liner oxide layer 111.
Refer to fig. 15. When a single-layer metal interconnection layer layout is adopted, the through silicon vias 103 fall on the dense lines of the first metal interconnection layer 101, the critical dimension of the bottom of the through silicon vias 103 is assumed to be 4 μm, the critical dimension/gap of the first interconnection metal lines 1011 is assumed to be 0.4/0.4 μm, respectively, and more than 5 lines are included in parallel to each other to ensure that the through silicon vias 103 completely fall on the dense lines. The effective contact area should be equal to the area of each line surrounded by the through-silicon vias 103. Assuming that the distance from the symmetry axis of a single line to the center of the through silicon via 103 is x, the area of the line surrounded by the through silicon via 103 can be calculated by the following formula:
wherein: h is 1 ＝x+0.2μm，h 2 = x-0.2 μm, r =2 μm, h1/h2 is the distance from both sides of the line to the center of the through-silicon via 103, and r is the radius of the bottom of the through-silicon via 103.
When the through-silicon via 103 is placed centrally, there are 5 lines in the area where the through-silicon via 103 falls, i.e., the first line x =1.6 μm, the second line x =0.8 μm, the third line x =0 μm, the fourth line x =0.8 μm, and the fifth line x =1.6 μm. At this time, the effective contact area of each line is calculated to be 0.95 μm 2 ，1.46μm 2 ，1.60μm 2 ，1.46μm 2 ，0.95μm 2 The total effective contact area is 6.42 μm 2 。
The offset of the alignment of the silicon via 103 and the first metal interconnection layer 101 in the X direction is defined as d,then x = | d-1.6| μm for the first line, x = | d-0.8| μm for the second line, x = d μm for the third line, x = d μm for the fourth line, x = d +0.8 μm for the fourth line, x = d +1.6 μm for the fifth line, and so on. When d =0.4 μm, a total of 6 lines are in contact with the through-silicon via 103, and the effective contact area of each line is calculated to be 0.23 μm 2 ，1.27μm 2 ，1.56μm 2 ，1.56μm 2 ，1.27μm 2 ，0.23μm 2 The total effective contact area is 6.15 μm 2 And is 95.8% of the centered ones. And, the minimum contact area of the single line is only 0.23 μm 2 Centered only at 24.2% of the minimum contact area, there is a significant risk of electromigration failure.
When the interconnect structure according to the first embodiment of the present invention shown in fig. 1-2 is adopted, the regions where the through-silicon vias 103 are located are all effectively contacted, and the effective contact area further includes the line sidewall of the first metal interconnect layer 101. At this time, the effective contact area at the surface of the first metal interconnection layer 101 and the second metal interconnection layer 102 is equal to the area of the opening of the through silicon via 103, and the sidewall effective contact area is equal to the product of the boundary length of the first metal interconnection layer 101 in the region where the through silicon via 103 falls and the depth of the wire groove of the first metal interconnection layer 101. Taking the above-mentioned through-silicon via 103 with a critical dimension of 4 μm as an example, the area of the opening of the through-silicon via 103 is 12.57 μm 2 . Assuming that the critical dimension/gap of the dense lines of the first metal interconnection layer 101 and the second metal interconnection layer 102 are both 0.4/0.4 μm, and assuming that the distance from the symmetry axis of a single line to the center of the through-silicon via 103 is x, the boundary length of the single line in the area where the through-silicon via 103 is located can be calculated by the following formula:
wherein h is 1 ＝x+0.2μm，h 2 ＝x-0.2μm，r＝2μm。
When the through silicon via 103 is placed in the center, the boundary lengths of the above 5 lines in the region where the through silicon via 103 falls can be calculated to be 4.60 μm,7.28 μm,7.96 μm,7.28 μm, and 4.60 μm respectively, assuming that the depth of the wire groove is 4.60 μm,7.28 μm,7.96 μm,7.28 μm, and 4.60 μm respectively0.3 μm, the effective contact area of the sidewall is 9.52 μm 2 . The total effective contact area of the interconnection structure reaches 22.09 mu m after the side wall area only exceeds the effective contact area obtained by adopting a single-layer metal interconnection layer mode and the surface contact area is added 2 And 3.44 times of the mode of a single metal interconnection layer.
When the Y-direction overlay alignment deviation of the through silicon via 103 and the first metal interconnection layer 101 is 0.4 μm, the boundary lengths of the 6 lines in the region where the through silicon via 103 falls can be calculated to be 1.74 μm,6.32 μm,7.80 μm,7.80 μm,6.32 μm, and 1.74 μm, respectively. At this time, the effective contact area of the sidewall is still 9.52 μm 2 . The total effective contact area is 22.09 μm 2 And 3.74 times of the single-layer metal interconnection layer mode.
The effective contact areas of the two schemes are shown in fig. 16 when alignment deviations of different alignments occur, it can be seen that the alignment deviations of the alignments have a large influence on the effective contact area of the single-layer metal interconnection layer scheme, and the variation range is 4.2% (solid line), whereas the effective contact area of the through-silicon-via interconnection structure scheme of the present invention has a small influence on the alignment deviations of the alignments, and the variation range is only 1.8% (dotted line).
Therefore, by adopting the silicon through hole interconnection structure, the effective contact area between the silicon through hole and the metal interconnection layer can be obviously and effectively increased, so that the current density is greatly reduced, and the electromigration failure risk is lower.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations fall within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A via interconnect structure, comprising:
the third through hole is arranged on the back surface of the first substrate, and the first metal layer and the second metal layer are sequentially arranged on the front surface of the first substrate;
the first metal layer comprises a plurality of densely distributed first metal structures, and the second metal layer comprises a plurality of densely distributed second metal structures which are positioned on the upper layer of the first metal structure technology;
the bottom of the third through hole penetrates through the front surface of the first substrate, falls on the first metal structure and the second metal structure, and fills an area enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure.
2. The via interconnect structure of claim 1, wherein the first metal layer comprises a first metal interconnect layer, wherein the second metal layer comprises a second metal interconnect layer, wherein the first metal structure comprises a first interconnect metal line in the first metal interconnect layer, and wherein the second metal structure comprises a second interconnect metal line in the second metal interconnect layer.
3. The via interconnection structure of claim 2, wherein any one of the second interconnection metal lines is parallel to and offset from a corresponding one of the first interconnection metal lines in a lower layer, and a bottom of the third via, after passing through the front surface of the first substrate, falls on the first interconnection metal line and the second interconnection metal line and fills a region surrounded by a sidewall of the first interconnection metal line and a process lower surface of the second interconnection metal line.
4. The via interconnection structure of claim 2, wherein the first interconnection metal lines are parallel to each other, the second interconnection metal lines are parallel to each other and orthogonal to the first interconnection metal lines, and a bottom of the third via, after passing through the front surface of the first substrate, falls on the first interconnection metal lines and the second interconnection metal lines and fills a region surrounded by sidewalls of the first interconnection metal lines and a process lower surface of the second interconnection metal lines.
5. The via interconnect structure of claim 2, further comprising:
a second via layer disposed between the first metal interconnect layer and the second metal interconnect layer, the second via layer including a plurality of densely-distributed second vias;
the first interconnection metal lines are distributed in an array form by rows and columns, the second interconnection metal lines are distributed in an array form by rows and columns, and are overlapped with the first interconnection metal lines in the rows/columns and are arranged in the rows/columns in a staggered manner;
any one second interconnection metal line on the vertically overlapped row/column is connected with the two first interconnection metal lines on the two corresponding sides of the lower layer through one second through hole respectively, and a chain-shaped structure is formed on the row/column;
and the bottom of the third through hole falls on the first interconnection metal line and the second interconnection metal line after penetrating through the front surface of the first substrate, and fills a region surrounded by the side wall of the first interconnection metal line, the side wall of the second through hole and the process lower surface of the second interconnection metal line.
6. The via interconnect structure of claim 1, wherein the first metal layer comprises a first via layer, the second metal layer comprises a first metal interconnect layer, the first metal structure comprises a first via in the first via layer, the second metal structure comprises a first interconnect metal line in the first metal interconnect layer; and the bottom of the third through hole falls on the first through hole and the first interconnection metal line after penetrating through the front surface of the first substrate, and fills a region enclosed by the side wall of the first through hole and the process lower surface of the first interconnection metal line.
7. The via interconnect structure of claim 1, further comprising: the second substrate is bonded on the fifth dielectric layer.
8. The via interconnect structure of claim 1, wherein the third via comprises a through silicon via.
9. A process implementation method of a through hole interconnection structure is characterized by comprising the following steps:
step S1: providing a first substrate;
step S2: sequentially forming a first metal layer and a second metal layer on the front surface of the first substrate, wherein the forming of the first metal structure in the first metal layer and the forming of the second metal structure in the second metal layer are positioned on the upper layer of the first metal structure;
and step S3: forming a fifth dielectric layer on the second metal layer, and bonding a second substrate on the fifth dielectric layer;
and step S4: forming a through hole pattern groove on the back surface of the first substrate, and enabling the bottom of the groove to penetrate through the front surface of the first substrate and respectively stop on the first metal structure and the second metal structure;
step S5: and filling the groove with through hole metal, filling the area enclosed by the side wall of the first metal structure and the process lower surface of the second metal structure, and forming a third through hole interconnected with the first metal layer and the second metal layer.
10. The method for realizing the process of the via interconnection structure according to claim 9, wherein the step S2 specifically comprises:
sequentially forming a first dielectric layer and a second dielectric layer on the front surface of the first substrate;
forming a first metal interconnection layer serving as the first metal layer in the second dielectric layer, wherein the first metal interconnection layer comprises first interconnection metal lines serving as the first metal structures and distributed in an array formed by rows and columns;
sequentially forming a third dielectric layer and a fourth dielectric layer on the second dielectric layer, forming a second metal interconnection layer serving as the second metal layer in the fourth dielectric layer, and forming a second through hole layer connected between the second metal interconnection layer and the first metal interconnection layer in the third dielectric layer, wherein the second metal interconnection layer comprises second interconnection metal lines and second through holes in the second through hole layer, the second interconnection metal lines and the first interconnection metal lines are formed as the second metal structures and distributed in an array manner according to rows and columns, the second interconnection metal lines and the first interconnection metal lines are overlapped in the rows/columns and are arranged in the staggered manner in the rows/columns, any one of the second interconnection metal lines is connected with two first interconnection metal lines on two corresponding sides of the lower layer through one of the second through holes, and a chain-shaped structure is formed in the rows/columns;
the step S4 specifically includes:
etching the back surface of the first substrate by using a mask to form the groove, and stopping the bottom of the groove on the first dielectric layer on the front surface of the first substrate by using an etching selection ratio;
forming a liner dielectric layer on the inner wall of the groove;
removing the liner dielectric layer on the bottom of the groove by using anisotropic dielectric etching, and further removing the first dielectric layer below the groove by using an etching selection ratio to stop the bottom of the groove on the second dielectric layer and expose the process lower surface of the first interconnection metal line in the groove region;
removing the second dielectric layer and the third dielectric layer below the trench by using an etching selection ratio, so that the bottom of the trench is stopped on the fourth dielectric layer, and the side wall of the first interconnection metal line, the side wall of the second through hole and the process lower surface of the second interconnection metal line in the trench region are exposed;
the step S5 specifically includes:
and sequentially forming a barrier layer and a seed crystal layer on the inner wall of the groove, then filling through hole metal in the groove, and flattening to form a silicon through hole serving as the third through hole.
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