CN115799188A - Fan-out packaging structure capable of reducing wafer warpage and forming method - Google Patents
Fan-out packaging structure capable of reducing wafer warpage and forming method Download PDFInfo
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- CN115799188A CN115799188A CN202211473739.5A CN202211473739A CN115799188A CN 115799188 A CN115799188 A CN 115799188A CN 202211473739 A CN202211473739 A CN 202211473739A CN 115799188 A CN115799188 A CN 115799188A
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Abstract
The invention relates to a fan-out packaging structure for reducing wafer warpage, which comprises: a photoresist having a patch opening thereon; a chip located in the patch opening; and a plastic package layer which is used for plastic packaging the chip. The fan-out packaging structure can effectively reduce the warpage of the wafer, and avoids the situation that the subsequent rewiring layer process cannot be carried out due to the overlarge warpage of the wafer after the plastic packaging process. The invention also relates to a forming method of the fan-out packaging structure for reducing wafer warpage.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out packaging structure capable of reducing wafer warpage and a forming method.
Background
With the development of technology, the development of chips to be light, thin, short and small is faster and faster, and thus the importance of the miniaturized wafer level packaging technology is continuously increasing. The fan-out package has the characteristics of wafer level package, and has the advantages of low cost, high integration level and the like, so that the fan-out package is one of the most popular novel package forms. However, the conventional fan-out wafer packaging technology generally has the problem of large warpage when packaging chips. After the molding process, the embedded wafer level package (ewlb package) may not be able to perform the subsequent redistribution layer (RDL) process due to the excessive wafer warpage. Therefore, a new research idea and solution is needed for reducing the wafer warpage.
Disclosure of Invention
In order to solve at least part of the problems in the prior art, the invention provides the fan-out packaging structure for reducing the wafer warpage and the forming method thereof.
In a first aspect of the present invention, to solve the problems in the prior art, the present invention provides a fan-out package structure for reducing wafer warpage, including:
a photoresist having a patch opening thereon;
a chip located in the patch opening; and
and the plastic packaging layer is used for plastic packaging the chip.
In an embodiment of the present invention, a value of the thickness of the photoresist ranges from 0.8H ≦ 1.2H, where H is a distance from the upper surface of the chip to the upper surface of the plastic encapsulation layer.
In one embodiment of the invention, the photoresist further has a marker pattern located around the patch opening.
In one embodiment of the present invention, the mark pattern is used for positioning and aligning when a chip is mounted; and
the shape of the marker pattern comprises a cross or a triangle.
In one embodiment of the invention, the size of the patch opening is larger than that of the chip, and the gap between the edge of the chip and the edge of the patch opening is 50-100 um; and/or
The front surface of the chip with the pins is close to the photoresist, and the back surface of the chip is far away from the photoresist.
In a second aspect of the present invention, to solve the problems in the prior art, the present invention provides a method for forming a fan-out package structure to reduce wafer warpage, including:
coating bonding glue on the slide;
coating photoresist on the bonding glue;
forming a patch opening and a mark pattern at a preset position on the photoresist by a photoetching technology;
the chip is inversely arranged at the opening of the chip by a chip mounting process, and the chip is positioned and aligned by the marking graph when being mounted;
the chip is plastically packaged to form a plastic packaging layer through a plastic packaging process; and
and removing the slide glass and the bonding glue to obtain the fan-out packaging structure capable of reducing the wafer warpage.
In an embodiment of the present invention, a value of the thickness of the photoresist ranges from 0.8H ≦ 1.2H, where H is a distance from the upper surface of the chip to the upper surface of the plastic encapsulation layer.
In one embodiment of the invention, the size of the patch opening is larger than that of the chip, and the gap between the edge of the chip and the edge of the patch opening is 50-100 um.
In one embodiment of the invention, the shape of the pattern of markings comprises a cross or a triangle.
In one embodiment of the present invention, a predetermined position on the photoresist is exposed and developed to form a patch opening and a mark pattern around the patch opening.
The invention has at least the following beneficial effects: according to the fan-out packaging structure and the forming method for reducing the wafer warpage, the photoresist is added on one side of the fan-out packaging structure close to the chip pins, so that the thermal expansion coefficient mismatch between a plastic packaging material and the chips is reduced, the wafer warpage is effectively reduced, and the condition that the subsequent rewiring layer process cannot be carried out due to the overlarge wafer warpage after a plastic packaging process is avoided; a mark pattern is formed around the opening of the patch, corresponds to the chip and is used for positioning and aligning when the chip is attached, and the chip alignment precision is improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 illustrates a cross-sectional view of a fan-out package structure to reduce wafer warpage in accordance with one embodiment of the present invention;
FIG. 2 shows a schematic diagram of an existing fan-out package structure equivalent to a circular board model;
FIG. 3 shows a schematic diagram of a fan-out package structure equivalent to a circular plate model to reduce wafer warpage in accordance with one embodiment of the present invention;
4A-4F illustrate cross-sectional views of a process of forming a fan-out package structure that reduces wafer warpage in accordance with one embodiment of the present invention;
FIG. 5 is a diagram illustrating warpage simulation results of a conventional embedded wafer level package; and
FIG. 6 is a graph illustrating warpage simulation results for a fan-out package structure with reduced wafer warpage according to one embodiment of the present invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the sequence of the steps.
FIG. 1 shows a cross-sectional view of a fan-out package structure to reduce wafer warpage in accordance with one embodiment of the present invention.
As shown in fig. 1, a fan-out package structure for reducing wafer warpage includes a photoresist 101, a patch opening 102, a mark pattern 103, a chip 104, and a molding layer 105.
The photoresist 101 has a patch opening 102 and a mark pattern 103, wherein the size of the patch opening 102 is larger than that of the chip 104, and the gap between the chip edge and the patch opening edge is 50-100 um. Wherein the marker patterns 103 are located in the vicinity of the patch opening 102, one marker pattern 103 for each chip 104. The shape of the mark pattern 103 includes, but is not limited to, a cross, a triangle, etc. for positioning alignment when mounting a chip. The thickness H of the photoresist is not a fixed value, and the value range of the thickness H of the photoresist is 0.8H less than or equal to 1.2H according to the size, the arrangement and different plastic packaging materials of the chip, wherein H is the distance from the upper surface (back surface) of the chip 104 to the upper surface of the plastic packaging layer 105.
When the plastic package material used by the plastic package chip is epoxy plastic package material (EMC), the Coefficient of Thermal Expansion (CTE) of the plastic package material is about 10 ppm/DEG C, the CTE of silicon is about 2.8 ppm/DEG C, and due to the large CTE mismatch between the plastic package material and the chip, the wafer warpage is too large after the plastic package process of the traditional embedded wafer level package, and the subsequent RDL process cannot be performed. The photoresist 103 is added on one side of the fan-out packaging structure close to the pin of the chip 101, the CTE of the photoresist is about 50 ppm/DEG C, the CTE mismatch between a plastic packaging material and the chip is reduced, and the wafer warping is effectively reduced.
FIG. 2 shows a schematic diagram of an existing fan-out package structure equivalent to a circular board model; fig. 3 shows a schematic diagram of a fan-out package structure equivalent to a circular plate model for reducing wafer warpage according to one embodiment of the present invention.
The principle of adding photoresist to reduce wafer warpage is as follows:
as shown in fig. 2, the conventional fan-out package structure is equivalent to a circular board model, and the molding compound above the chip is used as an upper board 20; the lower plate 21 is composed of a plastic package material and a chip, and the chip and the plastic package material in the lower plate 21 are equivalent to a new material by using a composite material equivalent method. The molding compound of the upper plate 20 has a coefficient of thermal expansion of about 10 ppm/deg.C and the die has a coefficient of thermal expansion of about 2.8 ppm/deg.C, so that the lower plate 21 has a coefficient of thermal expansion between 10 ppm/deg.C and 2.8 ppm/deg.C. The upper plate 20 has a greater coefficient of thermal expansion, thus causing wafer warpage.
As shown in fig. 3, in the present invention, a layer of photoresist is added to the bottom of the fan-out package structure, and the fan-out package structure can be regarded as a three-layer board model. The upper plate 30 is made of a molding compound, the middle plate 31 is made of a molding compound and chips, and the lower plate 32 is made of a photoresist and chips. The coefficient of thermal expansion of the photoresist is about 50 ppm/deg.C, so the lower plate 32 has a larger CTE to balance the larger CTE of the upper plate 30, which can effectively reduce wafer warpage.
Fig. 4A-4F illustrate cross-sectional views of a process of forming a fan-out package structure that reduces wafer warpage in accordance with one embodiment of the present invention.
A method for forming a fan-out packaging structure for reducing wafer warpage comprises the following steps:
step 1, as shown in fig. 4A, a bonding adhesive 202 is coated on a slide 201.
Step 2, as shown in fig. 4B, a photoresist 203 is coated on the bonding glue 202.
Step 3, as shown in fig. 4C, a patch opening 204 and a mark pattern 205 are formed at a predetermined position on the photoresist 203 by a photolithography technique. Exposure and development are performed at predetermined positions on the photoresist 203 to form a patch opening 204 and a mark pattern 205 around the patch opening. One for each chip 205. The shape of the marker pattern 205 includes, but is not limited to, a cross, a triangle, and the like. The size of the patch opening 204 is larger than that of the chip, so that the gap between the edge of the attached chip and the edge of the patch opening is 50-100 um.
Step 4, as shown in fig. 4D, the chip 206 is flipped over at the chip opening 204 by a chip mounting process, and is aligned by the mark pattern 205 when the chip is mounted.
Step 5, as shown in fig. 4E, the chip 206 is plastic-packaged by a plastic packaging process to form a plastic packaging layer 207.
And 6, as shown in fig. 4F, removing the carrier 201 and the bonding adhesive 202 by a bonding stripping process to obtain the fan-out package structure for reducing the wafer warpage. In the fan-out package structure for reducing the warpage of the wafer, the thickness H of the photoresist 203 is not a constant value, and the thickness H of the photoresist is different according to the size, arrangement and different molding compounds of the chip, and the value range of the thickness H is 0.8H less than or equal to 1.2H, wherein H is the distance from the upper surface (back surface) of the chip 206 to the upper surface of the molding layer 207.
When the plastic package material used for plastic packaging the chip is epoxy plastic package material (EMC), the Coefficient of Thermal Expansion (CTE) of the plastic package material is about 10 ppm/DEG C, the CTE of silicon is about 2.8 ppm/DEG C, and due to large CTE mismatch between the plastic package material and the chip, after the plastic packaging process of the traditional embedded wafer level packaging, due to the fact that the wafer is warped too much, the subsequent RDL process cannot be carried out. The photoresist is added on one side of the fan-out packaging structure close to the chip 206 pin, the CTE of the photoresist is about 50 ppm/DEG C, the CTE mismatch between the plastic packaging material and the chip is reduced, and the wafer warping is effectively reduced.
FIG. 5 is a diagram illustrating warpage simulation results of a conventional embedded wafer level package; FIG. 6 shows a graph of warpage simulation results for a fan-out package structure with reduced wafer warpage according to one embodiment of the present invention.
As shown in fig. 5 and fig. 6, simulation results show that the wafer warpage gradually increases from the center to the edge, wherein the maximum warpage of the conventional embedded wafer level package is 5.1mm, and the maximum warpage of the fan-out package structure for reducing the wafer warpage is 1mm, which indicates that the fan-out package structure of the present invention can effectively reduce the wafer warpage.
The invention has at least the following beneficial effects: according to the fan-out packaging structure and the forming method for reducing the wafer warpage, the photoresist is added on one side of the fan-out packaging structure close to the chip pins, so that the thermal expansion coefficient mismatch between a plastic packaging material and the chips is reduced, the wafer warpage is effectively reduced, and the condition that the subsequent rewiring layer process cannot be carried out due to the overlarge wafer warpage after a plastic packaging process is avoided; a mark pattern is formed around the opening of the patch, corresponds to the chip and is used for positioning and aligning when the chip is attached, and the chip alignment precision is improved.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art upon the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.
Claims (10)
1. A fan-out package structure for reducing wafer warpage, comprising:
a photoresist having a patch opening thereon;
a chip located in the patch opening; and
and the plastic packaging layer is used for plastic packaging the chip.
2. The fan-out package structure for reducing warpage of a wafer of claim 1, wherein a thickness of the photoresist ranges from 0.8H ≦ 1.2H, where H is a distance from an upper surface of the chip to an upper surface of the molding layer.
3. The fan-out package structure with reduced wafer warpage as claimed in claim 1, wherein the photoresist further has a marking pattern on it, the marking pattern being located around the patch opening.
4. The fan-out package structure with reduced wafer warpage as claimed in claim 2, wherein the marking pattern is used for alignment when a chip is mounted; and
the shape of the marker pattern comprises a cross or a triangle.
5. The fan-out package structure for reducing wafer warpage as claimed in claim 1, wherein the size of the patch opening is larger than the size of the chip, and a gap between an edge of the chip and an edge of the patch opening is 50-100 um; and/or
The front surface of the chip with the pins is close to the photoresist, and the back surface of the chip is far away from the photoresist.
6. A method for forming a fan-out package structure for reducing wafer warpage is characterized by comprising the following steps:
coating bonding glue on the slide;
coating photoresist on the bonding glue;
forming a patch opening and a mark pattern at a preset position on the photoresist by a photoetching technology;
the chip is inversely arranged at the opening of the chip by a chip mounting process, and the chip is positioned and aligned by the marking graph when being mounted;
the chip is plastically packaged to form a plastic packaging layer through a plastic packaging process; and
and removing the carrier and the bonding glue to obtain the fan-out packaging structure for reducing the wafer warpage.
7. The method as claimed in claim 6, wherein a thickness of the photoresist ranges from 0.8H ≦ H ≦ 1.2H, where H is a distance from an upper surface of the die to an upper surface of the molding layer.
8. The method as claimed in claim 6, wherein the size of the patch opening is larger than the size of the chip, and the gap between the edge of the chip and the edge of the patch opening is 50-100 um.
9. The method for forming the fan-out package structure with reduced wafer warpage of claim 6, wherein the shape of the marking pattern comprises a cross or a triangle.
10. The method for forming the fan-out package structure with reduced wafer warpage as recited in claim 6, wherein the exposing and developing are performed at predetermined locations on the photoresist to form a patch opening and a mark pattern around the patch opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211473739.5A CN115799188A (en) | 2022-11-22 | 2022-11-22 | Fan-out packaging structure capable of reducing wafer warpage and forming method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211473739.5A CN115799188A (en) | 2022-11-22 | 2022-11-22 | Fan-out packaging structure capable of reducing wafer warpage and forming method |
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| CN115799188A true CN115799188A (en) | 2023-03-14 |
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| CN202211473739.5A Pending CN115799188A (en) | 2022-11-22 | 2022-11-22 | Fan-out packaging structure capable of reducing wafer warpage and forming method |
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