CN115799088A - Electronic device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides an electronic device and a method for manufacturing the same. The electronic device comprises a substrate, a bump, a chip and an adhesion layer. The substrate comprises a first connecting pad. The bump is disposed on the first connection pad. The chip comprises a second connecting pad. The bump is disposed between the first connecting pad and the second connecting pad. The adhesion layer is arranged between the substrate and the chip. The loss factor of the adhesive layer is less than or equal to 0.01 at a frequency of 10 GHz. The manufacturing method of the electronic device comprises the following steps: providing a substrate, wherein the substrate comprises a first connection pad; applying an adhesive layer on the substrate; patterning the adhesion layer to enable the adhesion layer to generate an opening exposing the first connection pad; forming a bump on the first connection pad; and bonding the chip to the bump through the second connection pad. The electronic device and the manufacturing method thereof according to the embodiments of the present disclosure may improve the reliability of the electronic device or may be suitable for high frequency/radio signal transmission.

Description

Electronic device and method for manufacturing the same

Technical Field

The present disclosure relates to electronic devices and methods for manufacturing the same, and more particularly, to an electronic device and a method for manufacturing the same, which can improve reliability of the electronic device or can be suitable for high frequency/radio signal transmission.

Background

Electronic devices or tiled electronic devices have been widely used in various fields such as communications, displays, automotive or aerospace applications. With the rapid development of electronic devices, the electronic devices are developed to be thinner and lighter, and thus the reliability or quality requirements of the electronic devices are higher.

Disclosure of Invention

The present disclosure provides an electronic device and a method for manufacturing the same, which can improve the reliability of the electronic device or can be suitable for high frequency/radio signal transmission.

According to an embodiment of the present disclosure, an electronic device includes a substrate, a bump, a chip, and an adhesive layer. The substrate comprises a first connecting pad. The bump is disposed on the first connection pad. The chip comprises a second connecting pad. The bump is disposed between the first connecting pad and the second connecting pad. The adhesion layer is arranged between the substrate and the chip. The loss factor of the adhesive layer is less than or equal to 0.01 at a frequency of 10 GHz.

According to an embodiment of the present disclosure, a method of manufacturing an electronic device includes: providing a substrate, wherein the substrate comprises a first connecting pad; applying an adhesive layer on the substrate; patterning the adhesion layer to enable the adhesion layer to generate an opening exposing the first connection pad; forming a bump on the first connection pad; providing a chip, wherein the chip comprises a second connecting pad; and bonding the chip to the bump through the second connection pad.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1A to 1D are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to an embodiment of the disclosure;

fig. 2A to 2B are schematic cross-sectional views illustrating a method of manufacturing an electronic device according to another embodiment of the disclosure;

FIG. 3 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure;

FIG. 4 is a schematic cross-sectional view of an electronic device according to another embodiment of the disclosure;

FIG. 5 is a schematic cross-sectional view of an electronic device according to another embodiment of the disclosure;

fig. 6 is a schematic cross-sectional view of an electronic device according to another embodiment of the disclosure.

Description of the reference numerals

100. 100a, 100b, 100c, 100d, 100e: an electronic device;

110: a substrate;

110a: a surface;

112: a first connection pad;

1121: a top surface;

1122: a side surface;

120: a bump;

120a: a side edge;

121: welding flux;

122: soldering flux;

130: a chip;

130a: an upper surface;

130b: a lower surface;

130c: a side surface;

132: a second connection pad;

140. 140a, 140b, 140c, 140d, 140e: an adhesive layer;

141: an adhesive material;

142: an opening;

144: a spacer;

150: a polymer solder paste;

160: re-routing the circuit layer;

161: a first circuit layer;

162: an insulating layer;

163: a second circuit layer;

164: a conductive via;

170: an electronic component;

180: a drive element;

c1, C2: a cavity;

d: a distance;

h: a height;

t: thickness;

y: the normal direction.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and brevity, the various figures of the present disclosure illustrate only a portion of an electronic device and certain elements of the figures are not necessarily drawn to scale. In addition, the number and size of the elements in the figures are merely illustrative and are not intended to limit the scope of the present disclosure.

In the following specification and claims, the words "comprise", "comprising", "includes" and "including" are open-ended words, and thus should be interpreted to mean "including, but not limited to, \8230;".

It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present (not directly). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there are no intervening elements or film layers present between the two.

Although the terms "first," "second," "third" \8230canbe used to describe various components, the components are not limited by these terms. This term is used only to distinguish a single component from other components within the specification. The same terms may not be used in the claims, but may be replaced by the first, second and third 8230in the order in which the elements in the claims are announced. Therefore, in the following description, a first constituent element may be a second constituent element in the claims.

As used herein, the term "about," "substantially," "approximately" generally refers to within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are approximate, that is, the meanings of "about", "substantially" and "approximately" may be implied without specifically reciting "about", "approximately", "essentially" and "approximately".

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with respect to the structure between which they are disposed. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. Furthermore, the term "coupled" encompasses any direct and indirect electrical connection.

In some embodiments of the present disclosure, the area, width, thickness or height of each element, or the distance or spacing between elements may be measured using an Optical Microscope (OM), a Scanning Electron Microscope (SEM), a thin film thickness profiler (α -step), an ellipsometer, or other suitable methods. In detail, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structure image including elements to be measured, and measure the area, width, thickness or height of each element, or the distance or spacing between elements. In some embodiments of the present disclosure, material measurements may be performed using resonance methods to obtain the loss coefficient Df and the dielectric coefficient Dk of the material, thereby knowing the material properties.

The electronic device of the present disclosure may include a display apparatus, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device can be a bendable or flexible electronic device. The display device may be a non-self-luminous type display device or a self-luminous type display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat or ultrasonic waves, but not limited thereto. The electronic components of the electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. The present disclosure will be described in terms of an electronic device.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure. Features of the various embodiments may be combined and matched as desired, without departing from the spirit or ambit of the invention.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1A to 1D are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to an embodiment of the disclosure. Referring to fig. 1D, the electronic device 100 of the present embodiment may include a substrate 110, a bump 120, a chip 130, and an adhesive layer 140. The substrate 110 includes a first connection pad 112. The bump 120 is disposed on the first connection pad 112. The chip 130 includes a second connection pad 132. The bump 120 is disposed between the first connecting pad 112 and the second connecting pad 132. The adhesive layer 140 is disposed between the substrate 110 and the chip 130. The material of the first connection pad 112 may include copper, nickel, other suitable metal materials, or a combination thereof, but is not limited thereto.

The following describes a method for manufacturing the electronic device 100 of the present embodiment, wherein the method for manufacturing the electronic device 100 may include, but is not limited to, the following steps:

first, referring to fig. 1A, a substrate 110 is provided. In the present embodiment, the substrate 110 may include a first connection pad 112 disposed on the surface 110a of the substrate 110. The surface 110a is a surface of the substrate 110 facing the chip 130. In the present embodiment, the substrate 110 may be a rigid substrate, a flexible substrate, or a combination thereof, for example, the material of the substrate 110 may include glass, quartz, sapphire (sapphire), ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof, but is not limited thereto.

Then, with reference to fig. 1A, an adhesive layer 140 is applied on the surface 110a of the substrate 110. The adhesive layer 140 may cover the first connection pads 112 and the substrate 110. In the present embodiment, the material of the adhesion layer 140 may include at least one of alkane (alkane), alkene (olefin), ether (ether), nitro (nitro), dimethylamine (dimethylamine), and parylene (parylene), but is not limited thereto. In addition, in the embodiment, since the loss factor (Df) of the adhesive layer 140 is, for example, less than or equal to 0.01 (i.e., df <0.01 or Df = 0.01) at a frequency of 10 gigahertz (GHz), the electronic device 100 is suitable for high frequency or radio signal transmission, but not limited thereto. In some embodiments, the loss tangent of the adhesive layer may be less than or equal to 0.008 at a frequency of 10 GHz. In other embodiments, the loss tangent of the adhesive layer may be less than or equal to 0.005 at a frequency of 10 GHz.

In the embodiment, since the dielectric constant (Dk) of the adhesive layer 140 may be, for example, less than or equal to 3.8 (i.e., dk <3.8 or Dk = 3.8) at a frequency of 10GHz, the electronic device 100 is suitable for high frequency or radio signal transmission, but not limited thereto. In some embodiments, the adhesive layer may also have a dielectric constant of less than or equal to 3.5 at a frequency of 10 GHz.

Then, referring to fig. 1B, the adhesive layer 140 is patterned, so that an opening 142 exposing the first connection pad 112 is formed in the adhesive layer 140. In the present embodiment, the method for patterning the adhesive layer 140 may include one of photolithography (photolithography), laser drilling (laser drilling), screen printing (screen printing), and spin-on method, but is not limited thereto. The opening 142 of the adhesive layer 140 may expose the first connection pad 112, and the size of the opening 142 may be, for example, larger than the size of the first connection pad 112, but not limited thereto. In some embodiments, the size of the opening may also be smaller than or equal to the size of the first connection pad (not shown).

Then, referring to fig. 1C, after the adhesive layer 140 is patterned, the bump 120 is formed on the first connection pad 112. The bump 120 may contact the first connection pad 112. In the present embodiment, the bump 120 may be formed on the first connection pad 112 by, for example, a Printing process (Printing) or an inkjet process (dispenser), but not limited thereto. The material of the bump 120 may include, for example, but not limited to, solder (solder) and flux (flux).

Then, referring to fig. 1D, a chip 130 is provided, wherein the chip 130 may include a second connecting pad 132, after the bump 120 is formed on the first connecting pad 112, the chip 130 is bonded to the bump 120 through the second connecting pad 132, and thus the bump 120 is located between the first connecting pad 112 of the substrate 110 and the second connecting pad 132 of the chip 130. In detail, after the adhesive layer 140 is patterned and the chip 130 is flip-chip mounted on the bump 120, a reflow process and a curing process are performed to gather the solder in the bump 120 and make the bump 120 wettable (wetting) and contact the first connection pad 112 of the substrate 110 and the second connection pad 132 of the chip 130. The chip 130 has an upper surface 130a, a lower surface 130b opposite to the upper surface 130a, and a side surface 130c connecting the upper surface 130a and the lower surface 130 b. The second connecting pads 132 are disposed on the lower surface 130b of the chip 130, and the lower surface 130b is a surface of the chip 130 facing the substrate 110. The material of the second connecting pad 132 may include copper, nickel, other suitable metal materials, or a combination thereof, but is not limited thereto.

Then, after performing the reflow process, a pressing process or a vacuuming process is performed to increase the bonding strength between the chip 130 and the substrate 110. In the embodiment, the adhesive layer 140 is located between the chip 130 and the substrate 110, so that the bonding strength and the stability between the chip 130 and the substrate 110 can be increased by adhering the chip 130 and the substrate 110 together through the adhesive layer 140, and the two side edges 120a of the bump 120 can be surrounded by the adhesive layer 140, so as to reduce the probability of contact between the bump 120 and water and oxygen, thereby improving the reliability (reliability) of the electronic device 100.

In the embodiment, compared to a general primer (underfill), since the size of the adhesive layer 140 can be precisely controlled by a patterning method, a fine pitch can be easily realized. In addition, compared to a general underfill, since the thickness of the adhesive layer 140 has a better uniformity (uniformity), the distance between the chip 130 and the substrate 110 also has a better uniformity, so as to reduce the tilt problem or the variation of the tilt angle (tilt angle) of the chip 130.

In the present embodiment, the chip 130 can be made of, for example, but not limited to, a silicon wafer, a III-V compound (such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC)), sapphire, or a glass wafer. The chip 130 may also be, for example, a semiconductor package device, including but not limited to, a Ball Grid Array (BGA), a Chip Scale Package (CSP), and a 2.5D/3D package. The chip 130 may include, but is not limited to, an Integrated Circuit (IC), a transistor, a Silicon Controlled Rectifier (SCR), a valve, a thin film transistor (thin film transistor), a capacitor, an inductor, a variable capacitor (variable capacitor), a filter, a resistor, a diode, a light emitting diode (led), a Micro Electro Mechanical System (MEMS), a liquid crystal chip (liquid crystal chip), a connector, an interposer, a redistribution layer (RDL), and the like. Thus, the electronic device 100 of the present embodiment is substantially completed.

Other examples will be listed below for illustration. It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

Fig. 2A to 2B are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to another embodiment of the disclosure. The embodiment shown in fig. 2A to 2B is similar to the embodiment shown in fig. 1A to 1D, and therefore, the same elements are denoted by the same reference numerals, and the details thereof will not be repeated. The embodiment shown in fig. 2A to 2B differs from the embodiment shown in fig. 1A to 1D in that: in the method for manufacturing the electronic device 100a of the embodiment, before forming the bump 120, the adhesive material 141, the plurality of solders 121, and the soldering flux 122 are mixed into a polymer solder paste (polymer solder paste) 150.

Specifically, referring to fig. 2A, in the method for manufacturing the electronic device 100a of the present embodiment, the polymer solder paste 150 is applied on the first connection pads 112 of the substrate 110, so that the polymer solder paste 150 covers the top surfaces 1121 and the side surfaces 1122 of the first connection pads 112. The size of the solder materials 121 is, for example, 1/2 times to 1/10 times that of the first connection pads 112, but not limited thereto. In the present embodiment, the polymer solder paste 150 may be applied on the first connection pads 112 of the substrate 110 by, for example, a printing process or an inkjet process, but not limited thereto.

Then, referring to fig. 2B, the chip 130 is bonded to the bump 120 through the second bonding pad 132. In detail, after the chip 130 is flip-chip mounted on the polymer solder paste 150, a reflow process and a curing process are performed to gather the plurality of solders 121 in the polymer solder paste 150 into the bumps 120, and make the bumps 120 wettable and contact the first connection pads 112 of the substrate 110 and the second connection pads 132 of the chip 130. At this time, the adhesive material 141 in the polymer solder paste 150 is also cured into the adhesive layer 140a, so that the two side edges 120a of the bump 120 can be contacted and surrounded by the adhesive layer 140a, thereby reducing the probability of contact between the bump 120 and water and oxygen, and further improving the reliability of the electronic device 100a.

In addition, in the present embodiment, there is a cavity C1 between two adjacent bumps 120. The cavity C1 may be surrounded and defined by two adjacent bumps 120, the chip 130, and the substrate 110. Thus, the electronic device 100a of the present embodiment is substantially completed.

Fig. 3 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure. Referring to fig. 1D and fig. 3, an electronic device 100b of the present embodiment is similar to the electronic device 100a of fig. 1D, but the difference therebetween is: in the electronic device 100b of the present embodiment, at least one spacer 144 may be further included, and the spacer 144 is disposed in the adhesive layer 140 b.

Specifically, referring to fig. 3, in the present embodiment, the spacers 144 are disposed between the lower surface 130b of the chip 130 and the surface 110a of the substrate 110 for supporting the chip 130 and reducing the tilt problem or the tilt angle variation of the chip 130. The spacers 144 may overlap the chip 130 in the normal direction Y of the substrate 110. In addition, in the present embodiment, the material of the spacer 144 may be silicon dioxide (SiO), for example ₂ ) Or other suitable filler material, but not limited thereto.

In the embodiment, when the distance D between the chip 130 and the substrate 110 is A, the height H of the spacer 144 may be 0.8 times to 1.2 times A (i.e., 0.8 xA ≦ H ≦ 1.2 xA), and the thickness T of the adhesive layer 140b may be 1 times to 1.2 times A (i.e., 1 xA ≦ T ≦ 1.2 xA), but not limited thereto. The distance D is, for example, a minimum distance between the chip 130 and the substrate 110 measured along the normal direction Y of the substrate 110. The height H is, for example, a minimum height measured along the normal direction Y of the substrate 110 in a state where the spacers 144 are not pressed. In some embodiments, after the spacers 144 are compressed by the chip 130 and the substrate 110, the height H of the spacers 144 may be, for example, substantially equal to the distance D between the chip 130 and the substrate 110. The thickness T is, for example, a minimum thickness measured along the normal direction Y of the substrate 110 in a state where the adhesive layer 140b is not pressed. In some embodiments, after the adhesive layer 140b is pressed by the chip 130 and the substrate 110, the thickness T of the adhesive layer 140b may be, for example, substantially equal to the distance D between the chip 130 and the substrate 110.

Fig. 4 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure. Referring to fig. 1D and fig. 4, an electronic device 100c of the present embodiment is similar to the electronic device 100a of fig. 1D, but the difference therebetween is: the electronic device 100c of the embodiment further includes a redistribution layer 160, an electronic component 170, and/or a driving component (or referred to as a controller) 180.

Specifically, referring to fig. 4, in the present embodiment, the redistribution layer 160 is disposed on the surface 110a of the substrate 110, and the redistribution layer 160 may include, but is not limited to, a first circuit layer 161, an insulating layer 162, a second circuit layer 163, and a conductive via 164. The first circuit layer 161 is disposed on the surface 110a of the substrate 110; the insulating layer 162 is disposed on the first circuit layer 161 to cover the first circuit layer 161 and a portion of the substrate 110; the second circuit layer 163 is disposed on the insulating layer 162; the conductive via 164 penetrates the insulating layer 162 to electrically connect the first circuit layer 161 and the second circuit layer 163.

The electronic component 170, which may be a transistor, is disposed in the redistribution layer 160. In some embodiments, the electronic component may also be a valve, a thin film transistor, a capacitor, an inductor, a filter, or the like (not shown).

The driving element 180 may be attached to the edge of the substrate 110, and the driving element 180 may be electrically connected to the electronic element 170 through the redistribution layer 160. The driving element 180 may be, for example, an integrated circuit, a Flexible Printed Circuit (FPC), a Printed Circuit Board (PCB), a Chip On Board (COB) or a Chip On Film (COF), but not limited thereto.

In the embodiment, the first connection pads 112 are disposed on the second circuit layer 163 of the redistribution layer 160, and the first connection pads 112 can be electrically connected to the redistribution layer 160.

In the present embodiment, the adhesion layer 140c is disposed on the second circuit layer 163 of the redistribution circuit layer 160 to cover the exposed circuits (e.g., the second circuit layer 163) and the electronic elements 170. Therefore, in the embodiment, the adhesive layer 140c can serve as a protection layer to surround the redistribution layer 160 and the electronic element 170, so as to reduce the probability of the redistribution layer 160 and the electronic element 170 contacting water, moisture, oxygen and foreign matters, thereby improving the reliability of the electronic device 100 c.

Fig. 5 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure. Referring to fig. 2B and fig. 5, an electronic device 100d of the present embodiment is similar to the electronic device 100a in fig. 2B, but the difference therebetween is: in the electronic device 100d of the embodiment, the adhesive layer 140d may also be disposed on the upper surface 130a and the side surface 130c of the chip 130.

Specifically, referring to fig. 5, in the present embodiment, when the adhesive layer 140d is, for example, parylene, the adhesive layer 140d can uniformly cover the surface (including the upper surface 130a, the lower surface 130b and the side surface 130 c) of the chip 130, the two side edges 120a of the bump 120 and the surface 110a of the substrate 110, so as to protect the chip 130, the bump 120 and the substrate 110. Wherein, the adhesive layer 140d has a uniform thickness because parylene is a conformal coating material (conformal coating material) or a vacuum deposition coating (vacuum deposition coating). Further, the parylene may have, for example, but not limited to, N-type, C-type, D-type, or HT-type characteristics.

Fig. 6 is a schematic cross-sectional view of an electronic device according to an embodiment of the disclosure. Referring to fig. 5 and fig. 6, an electronic device 100e of the present embodiment is similar to the electronic device 100d of fig. 5, but the difference therebetween is: in the electronic device 100e of the present embodiment, the adhesive layer 140e does not cover the side 120a of the bump 120.

Specifically, referring to fig. 6, in the embodiment, when the adhesive layer 140e is, for example, a sheet molding compound (sheet molding compound), a vacuum heating method is required to uniformly cover the adhesive layer 140e on the surface of the chip 130 (including the upper surface 130a, a portion of the lower surface 130b and the side surface 130 c) and the surface 110a of the substrate 110, so as to protect the chip 130, the bump 120 and the substrate 110. In some embodiments, which are not shown, the adhesive layer may not cover the lower surface 130b of the chip 130 and be aligned with the side surface 130c of the chip 130, that is, the adhesive layer disposed on the substrate 110 may also extend from the substrate 110 directly through the side surface 130c of the chip 130 to the upper surface 130a of the chip 130.

In the present embodiment, the cavity C2 may be surrounded and defined by two adjacent bumps 120, chips 130, and substrates 110. The cavity C2 may expose the bump 120, the first connecting pad 112 and the second connecting pad 132. The cavity C2 may be air or vacuum.

In summary, in the electronic device and the manufacturing method thereof according to the embodiment of the disclosure, the adhesive layer is disposed between the substrate and the chip, so that the bonding strength and the stability between the chip and the substrate can be increased. Because the two sides of the bump can be surrounded by the adhesive layer, the probability of the bump contacting with water and oxygen can be reduced, and the reliability of the electronic device can be improved. In addition, in the embodiment, since the loss factor of the adhesive layer can be less than or equal to 0.01 at a frequency of 10GHz, the electronic device can be suitable for high frequency or radio signal transmission. In addition, in some embodiments, the adhesive layer may have a dielectric constant of less than or equal to 3.8 at a frequency of 10GHz, thereby making the electronic device suitable for high frequency or radio signal transmission.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure.

Claims (10)

1. An electronic device, comprising:

a substrate including a first connection pad;

the bump is arranged on the first connecting pad;

the chip comprises a second connecting pad, wherein the bump is arranged between the first connecting pad and the second connecting pad; and

and the adhesion layer is arranged between the substrate and the chip, and the loss coefficient of the adhesion layer is less than or equal to 0.01 under the frequency of 10 GHz.

2. The electronic device of claim 1, wherein the adhesive layer has a dielectric constant of less than or equal to 3.8 at a frequency of 10 GHz.

3. The electronic device of claim 1, wherein the adhesive layer is further disposed on the top surface and the side surface of the chip.

4. The electronic device of claim 1, further comprising:

at least one spacer disposed in the adhesive layer.

5. The electronic device of claim 1, wherein the material of the adhesive layer comprises at least one of an alkane, an alkene, an ether, a nitro group, dimethylamine, and parylene.

6. A method of manufacturing an electronic device, comprising:

providing a substrate, wherein the substrate comprises a first connection pad;

applying an adhesive layer on the substrate;

patterning the adhesion layer to enable the adhesion layer to generate an opening exposing the first connecting pad;

forming a bump on the first connection pad;

providing a chip, wherein the chip comprises a second connecting pad; and

and bonding the chip to the bump through the second connecting pad.

7. The method of claim 6, wherein the bump is formed on the first connecting pad by a printing process or an inkjet process.

8. The method of claim 6, wherein the patterning process is one of photolithography, laser drilling, screen printing, and spinning.

9. The method of claim 6, wherein the adhesive layer has a loss tangent of 0.01 or less at a frequency of 10 GHz.

10. The method of claim 6, wherein the adhesive layer has a dielectric constant of less than or equal to 3.8 at a frequency of 10 GHz.

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