CN115794206A

CN115794206A - Information transmission method and computing device

Info

Publication number: CN115794206A
Application number: CN202211483138.2A
Authority: CN
Inventors: 周豪
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2023-03-14

Abstract

The embodiment of the application discloses an information transmission method and computing equipment, which are used for realizing that a BMC chip manages a plurality of VRs through Complex Programmable Logic Devices (CPLDs) and reducing the adaptation workload. The application is applied to the computing equipment which can comprise a BMC chip, a CPLD and a plurality of VRs, wherein the BMC chip is connected with the CPLD, and the CPLD is connected with the VRs. When the CPLD receives the information sent by the BMC chip, the destination address of the information is the first BMC defined address of the first VR, and the first VR is one of the VRs, then the CPLD may determine the first CPLD defined address corresponding to the first BMC defined address, and send the information to the first VR based on the first CPLD defined address, so that the first VR and the first BMC defined address only need to be adapted once on the BMC chip, and subsequently, if the address of the first VR needs to be modified, the CPLD can be modified, thereby reducing the adaptation workload and shortening the development cycle.

Description

Information transmission method and computing device

Technical Field

The present application relates to the field of computers, and in particular, to an information transmission method and a computing device.

Background

With the rapid growth of the computing industry, the demand for servers has also increased. In order to ensure stable supply of the server, the server needs to consider implementation of multiple compatible schemes at the beginning of design, and particularly, the compatibility of a combination scheme of different Voltage Regulators (VRs) is an important measure of the compatibility of a motherboard in the server.

At present, management of multiple VRs in a server is mainly implemented by directly connecting multiple VRs through a Baseboard Management Controller (BMC) chip on a motherboard (for example, management contents may include online upgrade, temperature and voltage acquisition, and the like of the VRs), where an address of a VR is set by setting peripheral hardware and by setting a pull-down resistor of the peripheral hardware. Then, when a component (e.g., a motherboard, a network card, or a backplane) in the server needs to be replaced, a combination scheme of a group of VRs corresponding to the component needs to be replaced, a large number of resistance values need to be modified on peripheral hardware, and address adaptation of the VRs needs to be performed on the BMC chip, which is very heavy in workload and increases a development cycle.

Disclosure of Invention

The embodiment of the application provides an information transmission method and computing equipment, which are used for realizing that a BMC chip manages a plurality of VRs through Complex Programmable Logic Devices (CPLDs) and reducing the adaptation workload.

A first aspect of the present application provides an information transmission method, which is used for a computing device, where the computing device includes a BMC chip, a CPLD, and multiple VRs, where the BMC chip is connected to the CPLD, and the CPLD is connected to the multiple VRs; the method comprises the following steps: the CPLD receives information sent by the BMC chip, the destination address of the information is a first BMC definition address of a first VR, and the first VR is one of the VRs; the CPLD determines a first CPLD definition address corresponding to the first BMC definition address; the CPLD sends the information to the first VR based on the first CPLD defined address.

In this application, since the CPLD is programmable, after the first VR and the corresponding first BMC definition address are adapted in the BMC chip, the corresponding relationship between the first BMC definition address and the first CPLD definition address may be written in the CPLD. When the address of the first VR needs to be changed, only the CPLD definition address corresponding to the first BMC definition address needs to be changed in the CPLD, and the first VR and the corresponding first BMC definition address do not need to be changed in the BMC chip, that is, only the first VR and the first BMC definition address need to be adapted once on the BMC chip, which reduces the adaptation workload and shortens the development cycle.

In some possible implementations, the CPLD stores a second mapping table, where the second mapping table includes a mapping from the first BMC defined address to the first CPLD defined address, and the determining, by the CPLD, the first CPLD defined address corresponding to the first BMC defined address includes: and the CPLD determines the first CPLD defined address corresponding to the first BMC defined address according to the second mapping table.

In some possible implementations, before the CPLD determines the first CPLD defined address corresponding to the first BMC defined address, the method further includes: the CPLD obtains a first allocation of addresses that includes a mapping of the first VR to the first CPLD defined address, then the CPLD may address the first VR based on the first allocation of addresses such that the CPLD may send the information to the first VR based on the first CPLD defined address.

In some possible implementations, the computing device includes a memory to store a first version number, the memory coupled to the CPLD to enable the CPLD to retrieve the first version number from the memory and determine the first allocation scheme corresponding to the first version number from a plurality of allocation schemes.

In some possible implementations, before the CPLD determines the first address allocation scheme corresponding to the first version number, the method further includes: the CPLD obtains a plurality of address allocation schemes and version numbers corresponding to the address allocation schemes to obtain a first mapping table, and then the CPLD may determine the first address allocation scheme corresponding to the first version number based on the first mapping table.

In some possible implementations, before the CPLD determines the first CPLD defined address corresponding to the first BMC defined address, the method further includes: the CPLD determines the first BMC defined address corresponding to the first VR; the CPLD determines a second mapping table based on the first BMC-defined address and the first address allocation scheme, the second mapping table including a mapping of the first BMC-defined address to the first CPLD-defined address. Then the CPLD may determine the first CPLD definition address corresponding to the first BMC definition address according to the second mapping table.

In some possible implementations, after the CPLD sends the information to the first VR based on the first CPLD-defined address, the method further includes: the CPLD receives the relevant data sent by the first VR; and the CPLD sends the related data to the BMC chip. Thus, the CPLD obtains the required correlation data.

In some possible implementations, the information includes upgrade data to indicate to the first VR that firmware to be upgraded based on the upgrade data is to be obtained, such that the first VR may upgrade the firmware.

In some possible implementations, the relevant data includes one or more of current, voltage, and/or temperature, such that the CPLD can assess the health of a component disposed by the first VR based on the relevant data.

A second aspect of the present application provides a computing device comprising: the system comprises a Baseboard Management Controller (BMC) chip, a Complex Programmable Logic Device (CPLD) and a plurality of Voltage Regulators (VRs), wherein the BMC chip is connected with the CPLD, and the CPLD is connected with the VRs; the BMC chip is used for sending information to the CPLD, the destination address of the information is a first BMC definition address of a first VR, and the first VR is one of the VRs; the CPLD is used for determining a first CPLD definition address corresponding to the first BMC definition address; the CPLD is further configured to send the information to the first VR based on the first CPLD defined address.

In some possible implementations, the CPLD stores a second mapping table that includes a mapping of the first BMC defined address to the first CPLD defined address; the CPLD is further used for determining the first CPLD definition address corresponding to the first BMC definition address according to the second mapping table.

In some possible implementations, the computing device further includes a motherboard, a backplane, and a network card; the BMC chip and the CPLD are arranged on the mainboard, the network card and the backboard are electrically connected with the mainboard, and at least one of the VRs is arranged on the mainboard, the backboard and the network card respectively.

In some possible implementations, the CPLD is further configured to obtain a first address allocation scheme, where the first address allocation scheme includes mapping of the first VR to the first CPLD defined address, and address setting is performed on the first VR based on the first address allocation scheme.

In some possible implementations, the computing device further includes: a memory connected to the CPLD; the memory is used for storing a first version number; the CPLD is further used for acquiring the first version number from the memory; the CPLD is further configured to determine the first address allocation scheme corresponding to the first version number, where the first address allocation scheme is one of the plurality of address allocation schemes.

In some feasible implementation manners, the CPLD is further configured to obtain a plurality of address allocation schemes and version numbers corresponding to the address allocation schemes, obtain a first mapping table, and determine the first address allocation scheme corresponding to the first version number based on the first mapping table.

In some possible implementations, the information is used to request corresponding relevant data from the first VR: the first VR for sending the relevant data to the CPLD based on the information; the CPLD is also used for sending the related data to the BMC chip.

A third aspect of the present application provides a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to perform the method of any of the first aspects above.

A fourth aspect of the present application provides a computer program product comprising computer executable instructions stored in a computer readable storage medium; the computer executable instructions may be read by at least one processor of the device from a computer readable storage medium, the execution of which by the at least one processor causes the device to carry out the method provided by the first aspect or any one of the possible implementations of the first aspect described above.

A fifth aspect of the present application provides a communication device that may include at least one processor, a memory, and a communication interface. At least one processor is coupled with the memory and the communication interface. The memory is configured to store instructions, the at least one processor is configured to execute the instructions, and the communication interface is configured to communicate with other communication devices under control of the at least one processor. The instructions, when executed by at least one processor, cause the at least one processor to perform the method of the first aspect or any possible implementation of the first aspect.

A sixth aspect of the present application provides a chip system, which includes a processor configured to support implementation of the functions recited in the first aspect or any one of the possible implementation manners of the first aspect.

In one possible design, the system-on-chip may also include a memory, storage, for holding necessary program instructions and data. The chip system may be formed by a chip, or may include a chip and other discrete devices.

For technical effects brought by any one of the possible implementation manners of the second aspect to the sixth aspect, reference may be made to technical effects brought by different possible implementation manners of the first aspect or the first aspect, and details are not described herein again.

Drawings

FIG. 1 is a schematic diagram of a computing device architecture;

FIG. 2 is a schematic diagram of a computing device according to an embodiment of the present disclosure;

fig. 3 is a schematic flowchart of an information transmission method according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a communication device according to an embodiment of the present application.

Detailed Description

The embodiment of the application provides an address setting method for multiple VRs, which is used for decoupling a BMC chip and the VRs, improving the fault tolerance rate and reducing the adaptation workload.

Embodiments of the present application are described below with reference to the accompanying drawings.

The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely descriptive of the various embodiments of the application and how objects of the same nature can be distinguished. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 1, which is a schematic structural diagram of a computing device 100, the computing device may include: a BMC chip 110 and a plurality of VRs 120.

The BMC chip 110 is a single board controller, and is generally used to manage each hardware constituting the server, thereby managing the server. For example, in an embodiment of the present application, the BMC chip 110 may be used to manage multiple VRs 120 in the VR control system 100.

Computing device 100 may include components such as a motherboard, backplane, and network card, each of which may be provided with one or more VRs 120.VR 120 may locate components in computing device 100 for health monitoring and voltage regulation of those components. Where a worker may be programmed in VR120 with firmware that monitors the corresponding component, the firmware may be used to obtain relevant data such as voltage, current, temperature, etc. in the component, and then the relevant data may be stored in a register. The BMC chip may then access the registers of VR120 to obtain relevant data to enable monitoring of the health of the components in computing device 100.

The main board is also called a main board (main board), a system board (system board), or a motherboard (motherboard), which is one of the most important components of a computer. The motherboard is generally a rectangular circuit board, on which main circuit systems forming a computer are mounted, and generally includes elements such as a Basic Input Output System (BIOS) chip, an input/output (I/O) control chip, a keyboard and panel control switch interface, an indicator light connector, an expansion slot, and a dc power supply connector for the motherboard and the plug-in card. The backplane is a circuit board or frame that supports other circuit boards, components, and interconnections between the components, and provides power and data signals to the supported components. A network card is a piece of computer hardware designed to allow computers to communicate over a computer network. The network card has a unique Media Access Control (MAC) address for enabling other devices to interconnect with the computing device 100 via cable or wirelessly.

With the rapid growth of the computing industry, the demand for servers has also increased. In order to ensure stable supply of the server, the server needs to consider implementation of multiple compatible schemes at the beginning of design, particularly, the compatibility of different VR combination schemes is met, and the compatibility is an important measurement index of the mainboard compatibility in the server.

At present, the management of multiple VRs in the server is mainly realized by directly connecting multiple VRs through a BMC chip on a motherboard (for example, the management content may include online upgrade, temperature and voltage acquisition, and the like of the VRs), where the address of the VR is set by setting peripheral hardware and by setting a pull-down resistor of the peripheral hardware. Then, when a component (e.g., a motherboard, a network card, or a backplane) in the server needs to be replaced, a combination scheme of a group of VRs corresponding to the component needs to be replaced, a large number of resistance values need to be modified on peripheral hardware, and address adaptation of the VRs needs to be performed on the BMC chip, which results in a large workload and a high error rate, and increases a development cycle.

In summary, in the above technical solutions, when a compatible scheme is replaced, a worker needs to develop a new code for the BMC chip to adapt to different power combination schemes, so that a development period is increased. Moreover, since the number of VRs is large, the number of modification points is increased by several times, and the error rate is increased. In addition, since the BMC chip is directly connected to all VRs through an integrated circuit bus (IIC) interface, it brings challenges to the layout and routing of a Printed Circuit Board (PCB), and is also not favorable for Signal Integrity (SI) on a transmission path.

Therefore, the application provides an information transmission method and a computing device, which are used for realizing that a BMC chip manages a plurality of VRs through Complex Programmable Logic Devices (CPLDs) and reducing the adaptation workload.

The application is applied to the computing device, the computing device can comprise a BMC chip, a CPLD and a plurality of VRs, the BMC chip is connected with the CPLD, and the CPLD is connected with the VRs. When the CPLD receives the information sent by the BMC chip, the destination address of the information is the first BMC defined address of the first VR, and the first VR is one of the VRs, then the CPLD may determine the first CPLD defined address corresponding to the first BMC defined address, and send the information to the first VR based on the first CPLD defined address.

In some possible implementations, the computing device may be a server or a terminal device.

The server may have a relatively large difference due to different configurations or performances, and may include at least one Central Processing Unit (CPU) (e.g., at least one processor) and a memory, and at least one storage medium (e.g., at least one mass storage device) for storing an application program or data. The memory and storage medium may be, among other things, transient or persistent storage. The program stored in the storage medium may include at least one module, and each module may include a series of instruction operations in the server. Still further, the central processor may be configured to communicate with the storage medium to execute a series of instruction operations in the storage medium on the server. The Server may also include at least one power source, at least one wired or wireless network interface, at least one input output interface, and/or at least one operating system, such as Windows Server, mac OS X, unix, linux, freeBSD, netWare, and the like. In some possible implementations, the server may also be a cloud server, which is not limited herein.

The server may be a functional module deployed in a server, or one server, or a server cluster composed of a plurality of servers, or one cloud computing service center, which is not limited in this embodiment of the present application. A server, also called a server, is a device that provides computing services. Since the server needs to respond to and process the service request to provide reliable service, the server generally needs to have the capability of undertaking and guaranteeing the service, and the server needs to have strong processing capability, high stability, high reliability, high security, expandability and manageability. In the embodiment of the present application, the server may be an x86 server, which is also called a Complex Instruction Set (CISC) architecture server, that is, a Personal Computer (PC) server in general, and is a server based on a PC architecture and using an intel or other x86 instruction set compatible processor chip and a windows operating system.

A terminal device, which may also be referred to as a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), a terminal, etc., is a device for providing voice and/or data connectivity to a user, or a chip disposed in the device, such as a handheld device with a wireless connection function, a vehicle-mounted device, etc. Currently, some examples of terminal devices are: a mobile phone, a desktop computer, a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned driving (self driving), a wireless terminal in remote surgery (remote medical supply), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety, a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), a home gateway device (5G-gateway, 5G-RG) supporting 5G joining, and the like.

In the embodiment of the present application, the computing device is described by taking a server as an example.

Referring to fig. 2, a schematic structural diagram of a computing device 200 according to an embodiment of the present disclosure is provided, where the computing device 200 may include: BMC chip 210, CPLD220, and multiple components (for example, component 1, component 2, and component 3, respectively), where each of the multiple components may be a motherboard, a backplane, or a network card, etc., and each component is provided with one or more VRs 230 (for example, component 1 is provided with one or VR 230-1 and VR 230-2, component 2 is provided with one or VR 230-3 and VR 230-4, and component 3 is provided with one or VR 230-5 and VR 230-6, and CPLD220 is connected to VRs 230-1-VR 230-6, respectively). The BMC chip 110 is connected with the CPLD220, and the CPLD220 is connected with a plurality of VRs 230. In some possible implementations, the BMC chip 110 and the CPLD220 may be disposed in a motherboard.

It should be noted that BMC may be referred to differently in different scenarios. For example, in some scenarios, the BMC chip 210 may also be referred to as an integrated live hs-out (iLO), and in another scenario, may also be referred to as an integrated delta remote access controller (idacc). Therefore, both iLO and irdac may be understood as the BMC chip 210 in the embodiment of the present application.

It should be noted that the CPLD220 is a digital integrated circuit whose logic functions are built by the user according to their own needs, and the basic design method is to generate corresponding target files by means of an integrated development software platform and using methods such as schematic diagrams and hardware description languages, and to download and store the codes by means of a download cable, thereby implementing a designed digital system. In the embodiment of the present application, the BMC chip 210 may be connected to the CPLD220 through an IIC interface, and the CPLD220 is respectively connected to the VRs 230 through IIC interfaces.

In some possible implementation manners, the CPLD220 may further be externally connected with a memory 240, where the memory 240 is used to store version numbers corresponding to components such as a motherboard, a backplane, and a network card, and the CPLD may match a corresponding address allocation scheme according to the version numbers corresponding to the motherboard, the backplane, and the network card. For example, the CPLD may match the address allocation schemes of multiple VRs disposed on the motherboard according to the version number corresponding to the motherboard, and may match the address allocation schemes of the VRs on the backplane according to the version number corresponding to the backplane. In some possible implementations, the memory may be a bill of material identity document (BOM ID) module. In some possible implementations, the CPLD220 may be connected to the memory 240 through an IIC interface. In some possible implementations, the memory 240 may be a memristor.

In some possible implementations, the CPLD220 may obtain multiple address allocation schemes and corresponding version numbers of the respective address allocation schemes. For example, the worker may write a plurality of address allocation schemes and version numbers corresponding to the respective address allocation schemes in the CPLD220 in a programming manner, and the CPLD220 may also obtain the plurality of address allocation schemes and the version numbers corresponding to the respective address allocation schemes from a third-party device, which is not limited herein. The memory 240 may store a version number corresponding to the current address allocation scheme, and after the CPLD220 acquires the version number from the memory 240, the CPLD220 determines the corresponding address allocation scheme based on the version number, and then performs address setting on the multiple VRs 230 based on the address allocation scheme.

Therefore, the present application provides an information transmission method and a computing device, which are used for implementing that the BMC chip 210 manages a plurality of VRs 230 through the CPLD220, and reducing the adaptation workload.

In this application, since the CPLD220 is programmable, after the first VR and the corresponding first BMC definition address in the VRs 230 are adapted in the BMC chip 210, the CPLD220 may write the corresponding relationship between the first BMC definition address and the first CPLD definition address. When the address of the first VR needs to be changed, only the CPLD definition address corresponding to the first BMC definition address needs to be changed in the CPLD220, and the first VR and the corresponding first BMC definition address do not need to be changed in the BMC chip 210, that is, only the first VR and the first BMC definition address need to be adapted once on the BMC chip 210, which reduces the adaptation workload and shortens the development cycle.

The foregoing embodiment describes the computing device 200 provided by the present application, and next describes an information transmission method performed based on the computing device 200.

Referring to fig. 3, an information transmission method provided in an embodiment of the present application mainly includes the following steps:

301. the CPLD acquires a plurality of address allocation schemes and version numbers corresponding to the address allocation schemes to obtain a first mapping table.

Note that the address allocation scheme is used to indicate CPLD-defined addresses of multiple VRs in a component. For example, the network card is provided with VR1 and VR2, and the corresponding address allocation scheme may include a CPLD definition address for VR1 and a CPLD definition address for VR 2; VR3 and VR4 are provided in the backplane, then the corresponding address assignment scheme may include defining an address for the CPLD of VR3 and a CPLD of VR 4. It should be noted that VR is used to monitor relevant data, such as voltage, temperature, current, etc., on the component on which it is disposed. When the VR obtains the relevant data, the relevant data can be stored in a register corresponding to the CPLD address of the VR.

In some possible implementations, one address assignment scheme may correspond to one version number. For example, address allocation scheme 1 corresponds to a version number of 001 and address allocation scheme 2 corresponds to a version number of 002. In some possible implementations, the worker may store a first version number corresponding to the first address allocation scheme to be used in the memory.

In some possible implementations, the plurality of address allocation schemes and the corresponding version numbers thereof may be determined by a worker or a third party, which is not limited herein. In some possible implementations, the worker may write the multiple address allocation schemes and their corresponding version numbers into the CPLD in a programming manner, which is not limited herein.

In some possible implementations, the plurality of address allocation schemes and their corresponding version numbers may form a first mapping table, which is exemplarily shown in table 1 below, as the first mapping table:

TABLE 1

Version number	Address allocation scheme
		001	Address allocation scheme 1
002	Address allocation scheme 2
		003	Address resolutionPreparation scheme 3

302. The CPLD determines a first address allocation scheme corresponding to a first version number in memory based on a first mapping table.

In some possible implementations, the first allocation scheme may include a mapping of the first VR to the first CPLD defined address, the first allocation scheme being one of a plurality of allocation schemes. For example, as shown in table 1 (first mapping table), if the current first version number in the memory is 001, the address allocation scheme 1 is corresponded.

In some possible implementations, when a worker needs to replace a component and needs to change the address allocation schemes of multiple VRs set in the component, the version number needs to be changed into a first version number in the memory, where the first version number corresponds to a first address allocation scheme, and the first address allocation scheme is the address allocation scheme of the multiple VRs preset in the replaced component. Then, the CPLD may determine the current version number from the memory as the first version number and determine a first address allocation scheme corresponding to the first version number based on the first mapping table. For example, the version number currently in memory is 001, and after replacing the component, the worker changes the version number from 001 to 002 in memory, and then the CPLD determines from the BOM ID module to 002 and determines the address assignment scheme 2 based on the first mapping table.

In some possible implementations, the memory may store version numbers corresponding to respective components of the multiple components, and the CPLD may obtain the version numbers from the memory and determine the address allocation schemes corresponding to the respective components based on the version numbers. Illustratively, in the memory, the version number corresponding to the network card is 001, and the version number of the backplane is 002, then the CPLD determines a corresponding address allocation scheme 1 based on 001, and determines a corresponding address allocation scheme 2 based on 002, where the address allocation scheme 1 is used for performing address equipment for the network card, and the address allocation scheme 2 is used for performing address equipment for the backplane.

303. The CPLD performs address setting for the first VR based on the first address allocation scheme.

In some possible implementations, the CPLD sets the address of a register of one VR, i.e., the CPLD defines the address. The register is used to store relevant data, which may be one or more of current, voltage, and/or temperature of the component in which the VR is located.

Illustratively, the first address allocation scheme includes for the address devices of VR1 and VR2 in component 1, VR1 corresponding to address 12 and VR2 corresponding to address 22, as shown in Table 2:

TABLE 2

VR	CPLD defined address
		VR1	Address 12
VR2	Address 22

304. The CPLD determines a first BMC defined address corresponding to the first VR.

In some possible implementation manners, a worker may adapt a corresponding relationship between multiple VRs and multiple BMCs definition addresses in the BMC chip in advance, for example, adapt in the BMC chip in a pull-down resistor manner, or adapt in other manners, which is not limited herein. In some possible implementation manners, a worker may program in the CPLD in advance, and write the corresponding relationship between the VR and BMC defined addresses in each component into the CPLD.

Illustratively, as shown in table 3, address correspondence is defined for each VR and BMC in component 1:

TABLE 3

VR	BMC defined addresses
		VR1	Address 11
VR2	Address 21

Then, if the first VR is the VR for component 1, the CPLD may determine the first BMC defined address corresponding to the first VR based on table 3.

Therefore, the staff only needs to adapt each VR and the corresponding BMC defined address in one component once in the BMC chip, when the component is subsequently replaced (for example, the component 1 is replaced by the component 2), the staff only needs to modify the version number corresponding to the component in the memory (for example, the version number 1 corresponding to the component 1 is changed into the version number 2 corresponding to the component 2), the CPLD determines a new address allocation scheme (for example, the version number 1 corresponds to the address allocation scheme 1, the version number 2 corresponds to the address allocation scheme 2) based on the new version number (the version number 2), and performs address setting on the new component (the component 2) based on the new address allocation scheme (the address allocation scheme 2), and the VR and the corresponding BMC defined address do not need to be adapted again in the BMC chip, so that the adaptation workload is reduced, and the development period is shortened.

305. The CPLD determines a second mapping table based on the first BMC-defined address and the first address allocation scheme, the second mapping table including a mapping of the first BMC-defined address to the first CPLD-defined address.

For example, the second mapping table may be as shown in the following table 4-1:

TABLE 4-1

BMC defined Address	CPLD defined address
		Address 11	Address 12
Address 21	Address 22

For example, the first BMC of the first VR defines an address of 11 and the first CPLD thereof defines an address of 12.

It should be noted that when the worker replaces the component, the worker only needs to change the version number in the memory to the version number corresponding to the new component, and may change the second mapping table, for example, change table 4-1 to the second mapping table shown in table 4-2:

TABLE 4-2

BMC defined Address	CPLD defined address
		Address 11'	Address 12
Address 21'	Address 22

For example, the BMC of the first VR defines an address as 11' and the CPLD thereof defines an address as 12.

306. The BMC chip sends information to the CPLD, the destination address of the information is a first BMC definition address of a first VR, and the first VR is one of the VRs.

Illustratively, when the CPLD receives the information sent by the BMC chip, the information points to the first BMC defined address of the first VR, and the CPLD may determine the first CPLD defined address of the first VR based on the first BMC defined address and the second mapping table, and forward the information to the first VR based on the first CPLD defined address.

It should be noted that, since the BMC chip does not sense the change of the address allocation scheme, that is, does not sense the change of the CPLD definition address of the first VR, when the BMC chip sends information to the first VR, the BMC chip still sends information based on the first BMC definition address of the first VR. For example, as shown in table 3, if the first VR is VR1, the first BMC defines an address as address 11.

In some possible implementations, the information may be request information for requesting to obtain data about a component, such as current, voltage, and/or temperature, provided by the first VR. The related data is stored in a set register, the BMC definition address may be an address initially set in the register, and the BMC definition address may also be any address, and may not be an address actually used by the first VR, and may be any information that corresponds to the first VR one to one, which is not limited herein.

307. And the CPLD determines a first CPLD definition address corresponding to the first BMC definition address according to the second mapping table.

For example, as shown in the second mapping table shown in table 4-1, if the first BMC defines the address as address 11, the CPLD defines the address as address 12; or, as shown in the second mapping table shown in table 4-2, if the first BMC defines the address as address 11', the CPLD defines the address as address 12.

308. The CPLD sends information to the first VR based on the first CPLD-defined address.

Illustratively, if the first CPLD defines the address as address 12, the CPLD sends information to the first VR based on address 12; if the first CPLD defines the address as the address 22, the CPLD sends information to the first VR based on the address 22; if the first CPLD defines an address as address 32, the CPLD sends information to the first VR based on address 32.

In some possible implementations, the information may be information to upgrade the first VR. It should be noted that there is a firmware in the first VR, the firmware is a program, and can implement the acquisition of current, voltage, and temperature, and has the functions of generating alarm information, and the like, and store the relevant data in the register corresponding to the first CPLD definition address. Illustratively, this information is used to overcome certain deficiencies in firmware; alternatively, the firmware is run with reduced computational effort by improving the algorithm.

In some possible implementations, this information may also be a request to the first VR to obtain data about the set component.

In the embodiment of the present application, if the information is used to request related data, steps 310-311 are performed; if the information is used to indicate that the first VR is upgraded, step 309 is performed.

309. The first VR upgrades based on the information.

In some possible implementations, the information may include upgrade data to indicate to the first VR that firmware to obtain relevant data is upgraded based on the upgrade data.

In some possible implementations, when the first VR receives the information, which may be information for upgrading a firmware of the first VR, the first VR may write the information in a register corresponding to the CPLD definition address indicated in the information. The first VR may then upgrade the firmware based on the information.

310. The first VR sends the relevant data to the CPLD.

In some possible implementations, after the first VR receives the information, if the information is used to request the relevant data, the first VR may feed back the requested relevant data to the CPLD.

311. And the CPLD sends related data to the BMC chip.

After the CPLD receives the relevant data sent by the first VR, the relevant data can be fed back to the BMC chip, and the BMC chip can monitor the health state of the component set by the first VR based on the relevant data. For example, the BMC chip may determine that there is an abnormality in a component set by the first VR based on the related data. For example, if the temperature in the relevant data is 99 ℃, it is determined that the component is overheated, and the BMC chip may feed back relevant alarm information.

In this application, since the CPLD is programmable, after the first VR and the corresponding first BMC definition address are adapted in the BMC chip, the corresponding relationship between the first BMC definition address and the first CPLD definition address may be written in the CPLD. When the address of the first VR needs to be changed, only the CPLD definition address corresponding to the first BMC definition address needs to be changed in the CPLD, and the first VR and the corresponding first BMC definition address do not need to be changed in the BMC chip, that is, only the first VR and the first BMC definition address need to be adapted once on the BMC chip, which reduces the adaptation workload and shortens the development period.

It should be noted that for simplicity of description, the above-mentioned embodiments of the method are described as a series of acts, but those skilled in the art should understand that the present application is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

To facilitate better implementation of the above-described aspects of the embodiments of the present application, the following also provides relevant means for implementing the above-described aspects.

Referring to fig. 4, a computing device 400 provided by an embodiment of the present application may include:

the system comprises a BMC chip 410, a CPLD 420 and a plurality of VRs 430, wherein the BMC chip 410 is connected with the CPLD 420, and the CPLD 420 is connected with the plurality of VRs 430;

the BMC chip 410 is configured to send information to the CPLD 420, where a destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the multiple VRs;

the CPLD 420 is configured to determine a first CPLD definition address corresponding to the first BMC definition address;

the CPLD 420 is further configured to send the information to the first VR based on the first CPLD defined address.

In some possible implementations, the CPLD 420 is further configured to obtain a first address allocation scheme, where the first address allocation scheme includes mapping of the first VR to the first CPLD defined address, and the first VR is addressed based on the first address allocation scheme.

In some possible implementations, the computing device 400 further includes: a memory 440 connected to the CPLD 420;

the memory 440 is used for storing a first version number;

the CPLD 420 is further configured to obtain the first version number from the memory 440;

the CPLD 420 is further configured to determine the first address allocation scheme corresponding to the first version number, where the first address allocation scheme is one of the plurality of address allocation schemes.

In some possible implementation manners, the CPLD 420 is further configured to obtain a plurality of address allocation schemes and version numbers corresponding to the address allocation schemes, obtain a first mapping table, and determine the first address allocation scheme corresponding to the first version number based on the first mapping table.

In some possible implementations, the CPLD 420 is further configured to determine the first BMC defined address corresponding to the first VR, determine a second mapping table based on the first BMC defined address and the first address allocation scheme, where the second mapping table includes a mapping from the first BMC defined address to the first CPLD defined address, and determine the first CPLD defined address corresponding to the first BMC defined address according to the second mapping table.

In some possible implementations, the first VR 430 is configured to transmit the relevant data to the CPLD 420 based on the information; the CPLD 420 is further configured to send the relevant data to the BMC chip 410.

In some possible implementations, the information includes upgrade data; the first VR 430 is further configured to upgrade the firmware based on the upgrade data, where the firmware is configured to obtain related data.

It should be noted that, because the contents of information interaction, execution process, and the like between the modules/units of the apparatus are based on the same concept as the method embodiment of the present application, the technical effect brought by the contents is the same as the method embodiment of the present application, and specific contents may refer to the description in the foregoing method embodiment of the present application, and are not described herein again.

Embodiments of the present application further provide a computer storage medium, where the computer storage medium stores a program, and the program executes some or all of the steps described in the above method embodiments.

Referring to fig. 5, a communication apparatus 500 according to another embodiment of the present application is described, including:

a receiver 501, a transmitter 502, a processor 503, and a memory 504. In some embodiments of the present application, the receiver 501, the transmitter 502, the processor 503 and the memory 504 may be connected by a bus or other means, wherein the connection by the bus is exemplified in fig. 5.

The memory 504, which may include both read-only memory and random-access memory, provides instructions and data to the processor 503. A portion of the memory 504 may also include non-volatile random access memory (NVRAM). The memory 504 stores an operating system and operating instructions, executable modules or data structures, or a subset or an expanded set thereof, wherein the operating instructions may include various operating instructions for performing various operations. The operating system may include various system programs for implementing various basic services and for handling hardware-based tasks.

The processor 503 controls the operation of the communication device 500, and the processor 503 may also be referred to as a Central Processing Unit (CPU). In a particular application, the various components of the communications device 500 are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, the various buses are referred to in the figures as a bus system.

The method disclosed in the embodiments of the present application may be applied to the processor 503 or implemented by the processor 503. The processor 503 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 503. The processor 503 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 504, and the processor 503 reads the information in the memory 504, and completes the steps of the above method in combination with the hardware thereof.

The receiver 501 may be used to receive input numeric or character information and generate signal inputs related to related settings and function control, the transmitter 502 may include a display device such as a display screen, and the transmitter 502 may be used to output numeric or character information through an external interface.

In this embodiment, the processor 503 is configured to execute the foregoing information transmission method.

In another possible design, when the computing device 400 or the communication apparatus 500 is a chip, the method includes: a processing unit, which may be, for example, a processor, and a communication unit, which may be, for example, an input/output interface, a pin or a circuit, etc. The processing unit may execute the computer executable instructions stored in the storage unit, so as to enable the chip in the terminal to execute the method for transmitting the wireless report information according to any one of the above first aspect. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, and the like, and the storage unit may also be a storage unit located outside the chip in the terminal, such as a read-only memory (ROM) or another type of static storage device that can store static information and instructions, a Random Access Memory (RAM), and the like.

The processor mentioned in any of the above may be a general purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the programs of the above methods.

It should be noted that the above-described embodiments of the apparatus are merely schematic, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiments of the apparatus provided in the present application, the connection relationship between the modules indicates that there is a communication connection therebetween, which may be specifically implemented as one or more communication buses or signal lines.

Through the above description of the embodiments, those skilled in the art will clearly understand that the present application can be implemented by software plus necessary general-purpose hardware, and certainly can also be implemented by special-purpose hardware including special-purpose integrated circuits, special-purpose CPUs, special-purpose memories, special-purpose components and the like. Generally, functions performed by computer programs can be easily implemented by corresponding hardware, and specific hardware structures for implementing the same functions may be various, such as analog circuits, digital circuits, or dedicated circuits. However, for the present application, the implementation of a software program is more preferable. Based on such understanding, the technical solutions of the present application may be substantially embodied in the form of a software product, which is stored in a readable storage medium, such as a floppy disk, a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods described in the embodiments of the present application.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.

Claims

1. An information transmission method, used for a computing device, the computing device comprising a Baseboard Management Controller (BMC) chip, a Complex Programmable Logic Device (CPLD) and a plurality of Voltage Regulators (VRs), wherein the BMC chip is connected with the CPLD, and the CPLD is connected with the VRs;

the method comprises the following steps:

the CPLD receives information sent by the BMC chip, the destination address of the information is a first BMC defined address of a first VR, and the first VR is one of the VRs;

the CPLD determines a first CPLD definition address corresponding to the first BMC definition address;

the CPLD sends the information to the first VR based on the first CPLD defined address.

2. The method of claim 1, wherein the CPLD stores a second mapping table that includes a mapping of the first BMC defined address to the first CPLD defined address, and wherein the CPLD determining the first CPLD defined address corresponding to the first BMC defined address includes:

and the CPLD determines the first CPLD defined address corresponding to the first BMC defined address according to the second mapping table.

3. The method of claim 1 or 2, further comprising:

the CPLD obtains a first address allocation scheme that includes a mapping of the first VR to the first CPLD defined address;

the CPLD performs address setting on the first VR based on the first address allocation scheme.

4. The method of claim 3, wherein the computing device includes a memory for storing a first version number, the memory being coupled to the CPLD;

the CPLD acquires the first address allocation scheme and comprises the following steps:

the CPLD acquires the first version number from the memory;

the CPLD determines the first address allocation scheme corresponding to the first version number, wherein the first address allocation scheme is one of the plurality of address allocation schemes.

5. The method of claim 4, further comprising:

the CPLD acquires a plurality of address allocation schemes and version numbers corresponding to the address allocation schemes to obtain a first mapping table;

the CPLD determining the first address allocation scheme corresponding to the first version number comprises:

the CPLD determines the first address allocation scheme corresponding to the first version number based on the first mapping table.

6. The method according to any one of claims 3-5, further comprising:

the CPLD determines the first BMC defined address corresponding to the first VR;

the CPLD determines a second mapping table based on the first BMC-defined address and the first address allocation scheme, the second mapping table including a mapping of the first BMC-defined address to the first CPLD-defined address.

7. The method according to any one of claims 1-6, further comprising:

the CPLD receives the relevant data sent by the first VR;

and the CPLD sends the related data to the BMC chip.

8. A computing device, comprising: the system comprises a Baseboard Management Controller (BMC) chip, a Complex Programmable Logic Device (CPLD) and a plurality of Voltage Regulators (VRs), wherein the BMC chip is connected with the CPLD, and the CPLD is connected with the VRs;

the BMC chip is used for sending information to the CPLD, the destination address of the information is a first BMC definition address of a first VR, and the first VR is one of the VRs;

the CPLD is used for determining a first CPLD definition address corresponding to the first BMC definition address;

the CPLD is further configured to send the information to the first VR based on the first CPLD defined address.

9. The computing device of claim 8, wherein the CPLD stores a second mapping table that includes a mapping of the first BMC-defined address to the first CPLD-defined address;

the CPLD is further configured to determine the first CPLD definition address corresponding to the first BMC definition address according to the second mapping table.

10. The computing device of claim 8 or 9, wherein the computing device further comprises a motherboard, a backplane, a network card; the BMC chip and the CPLD are arranged on the mainboard, the network card and the backboard are electrically connected with the mainboard, and at least one of the VRs is arranged on the mainboard, the backboard and the network card respectively.