CN115793313B - Display panel, electronic equipment and manufacturing method of display panel - Google Patents

Display panel, electronic equipment and manufacturing method of display panel Download PDF

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Publication number
CN115793313B
CN115793313B CN202211312076.9A CN202211312076A CN115793313B CN 115793313 B CN115793313 B CN 115793313B CN 202211312076 A CN202211312076 A CN 202211312076A CN 115793313 B CN115793313 B CN 115793313B
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black matrix
substrate
exposure
splicing
width
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CN115793313A (en
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胡佩
王建树
胡波
林丽锋
林欣
李春雨
周融
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BOE Technology Group Co Ltd
Fuzhou BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Fuzhou BOE Optoelectronics Technology Co Ltd
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Abstract

The embodiment of the invention provides a display panel, electronic equipment and a manufacturing method of the display panel. The array substrate comprises a first substrate layer, a plurality of shielding units arranged at intervals on one side of the first substrate layer facing the color film substrate, and a plurality of data signal lines which are parallel to each other and are arranged at intervals on one side of the plurality of shielding unit layers facing the color film substrate. Orthographic projections of the splicing area and the non-splicing area in the direction of the first substrate layer all span a plurality of data signal lines, the projection positions of the shielding units are arranged in one-to-one correspondence with the data signal lines, and the lateral sides of the shielding units in the width direction exceed the lateral sides of the data signal lines in the width direction. The display panel reduces poor splicing caused by splicing exposure.

Description

Display panel, electronic equipment and manufacturing method of display panel
Technical Field
The invention relates to the technical field of oversized high-resolution display, in particular to a display panel, electronic equipment and a manufacturing method of the display panel.
Background
With technological progress and continuous improvement of human living standard, the performance requirements of the market on display screens are increasing, and particularly, the requirements for high-performance products with high resolution, high refresh rate, high contrast and the like, such as oversized 98 '/110' 8K and 16K products, are increasing rapidly. At present, the size of an industrial Mask is fixed, the Panel size of an oversized product is larger than the maximum exposure area of the Mask, a Panel (display film layer) pattern cannot be completely placed in the Mask, splicing exposure is needed, and the large-size Panel is formed through two or more times of exposure.
In the process of manufacturing the color film substrate of the oversized display panel, generally, mosaic exposure is adopted for the black matrix film layer of the color film substrate, namely, a mosaic exposure area has a certain width, repeated exposure is needed for the area, due to the existence of alignment errors in the mosaic process, the situation that the black matrix of the mosaic area after exposure is inconsistent with the black matrix of the non-mosaic area can occur, and under the condition of larger errors, inconsistent display light efficiency of the display panel in the non-mosaic area and the mosaic area can be caused, namely, obvious mosaic Mura (bad) exists.
Disclosure of Invention
The embodiment of the invention aims to provide a display panel, electronic equipment and a manufacturing method of the display panel, which are used for solving the problem that poor splicing is easily generated by multi-time splicing exposure of a large-size display panel. The specific technical scheme is as follows:
The first aspect of the application provides a display panel, comprising an array substrate and a color film substrate which are oppositely arranged, wherein the color film substrate comprises a plurality of non-splicing areas and splicing areas positioned between the non-splicing areas; the array substrate includes: the color film comprises a first substrate layer, a plurality of shielding units arranged at intervals and arranged on one side of the first substrate layer, facing the color film substrate, and a plurality of data signal lines arranged at intervals and parallel to each other and arranged on one side of the shielding units, facing the color film substrate; orthographic projections of the splicing area and the non-splicing area in the first substrate layer direction all span a plurality of data signal lines, the projection positions of the shielding units are arranged in one-to-one correspondence with the data signal lines, and the lateral sides of the shielding units in the width direction exceed the lateral sides of the data signal lines in the width direction.
In this embodiment, the color film substrate includes a plurality of non-spliced regions and a spliced region located between the non-spliced regions, the non-spliced regions are regions formed by one exposure, the spliced regions are regions formed by two exposure processes, the spliced regions and the non-spliced regions span across a plurality of data signal lines, that is, the spliced regions and the non-spliced regions have certain widths, but the widths of the spliced regions are far smaller than those of the non-spliced regions. Because the splicing area is an area formed by splicing the front and back exposure, in the splicing exposure process, the alignment error between the mask plate and the substrate to be exposed is unavoidable, so that the opening ratio of the splicing area after exposure and the opening ratio of the non-splicing area after exposure are slightly different, the opening ratio can influence the light efficiency of the pixels, namely, the change of the light transmittance can cause poor splicing of the display panel macroscopically. Especially for oversized high resolution products, the pixels PPI (number of pixels per inch, pixels Per Inch) are higher, the openings are smaller, the sensitivity to transmittance changes caused by opening rate changes is higher, and the stitching Mura is more likely to occur. Therefore, in order to reduce the difference between the aperture ratio of the splicing region and the aperture ratio of the non-splicing region, a plurality of shielding units are arranged at intervals on one side of the first substrate layer facing the color film substrate, and the shielding units are arranged on the same layer. Specifically, the shielding units can be formed through a deposition and etching process, gaps among the shielding units are filled with insulating materials to form a first insulating layer, then a plurality of data signal lines are arranged at intervals on one side of the first insulating layer, facing the color film substrate, of the first insulating layer, and the data signal lines are arranged on the same layer, and can be realized through the deposition and etching process. The side of the width direction of a plurality of shielding units exceeds the side of the width direction of the data signal line, and as the shielding units are arranged on the first layer of the first substrate layer, the width fluctuation of the shielding units is small, so that the influence on the aperture ratio is small, the intensity of the edge light effect is directly influenced by the width of the shielding units when being observed from one side of the array substrate, the association degree between the edge light effect and the aperture ratio caused by splicing exposure is reduced, and poor splicing caused by splicing exposure can be reduced.
In addition, the shielding unit may have a side in the width direction of the data signal line to be more than the side in the width direction of the data signal line, so that light leakage caused by the data signal line may be reduced.
In addition, the display panel according to the embodiment of the application may further have the following technical features:
in some embodiments, the shielding unit is a first shielding block having a width which is consistent with the extending direction of the data signal line and is greater than the width of the data signal line.
In some embodiments, the shielding unit is two second shielding blocks aligned and spaced in a direction consistent with the extending direction of the data signal line, and the sum of the width and the spacing distance of the two second shielding blocks is greater than the width of the data signal line.
In some embodiments, the shielding element is made of a material comprising metal.
In some embodiments, the stitching region is formed by two exposures, the two exposures forming a mosaic pattern that is complementary.
In some embodiments, the shielding unit has a side that is spaced apart from the data signal line by a distance of 0.4 micrometers to 2 micrometers.
In some embodiments, the splice area has a width of 30 millimeters to 100 millimeters.
In some embodiments, the color film substrate includes a second substrate layer; a first black matrix is arranged on one side, facing the array substrate, of the second substrate layer; the array substrate further comprises a plurality of mutually parallel grid signal lines which are arranged at intervals and are arranged on one side of the first substrate layer facing the color film substrate, and the projection of the grid signal lines and the projection of the data signal lines on the first substrate layer are arranged in a crossing manner; the first black matrixes are arranged in one-to-one correspondence with the grid signal lines, and orthographic projection of the first black matrixes in the direction of the first substrate layer can cover orthographic projection of the grid signal lines in the direction of the first substrate layer.
In some embodiments, a second black matrix is further disposed on a side of the second substrate layer facing the TFT substrate, the orthographic projection of the second black matrix in the direction of the first substrate layer may cover the orthographic projection of the data signal line in the direction of the first substrate layer, and the lateral edge of the shielding unit in the width direction exceeds the lateral edge of the second black matrix in the width direction.
A second aspect of the present application provides an electronic device, which is a display panel as described above.
The third aspect of the present application provides a method for manufacturing a display panel, including the steps of:
forming an array substrate, wherein the array substrate comprises a first substrate layer, a plurality of shielding units are arranged at intervals on one side of the substrate, facing the color film substrate, and a plurality of data signal lines are arranged at intervals on one side of the shielding units, facing the color film substrate, and orthographic projections of the splicing area and the non-splicing area in the direction of the first substrate layer respectively span across the plurality of data signal lines, the shielding units are arranged in one-to-one correspondence with the data signal line areas, and the lateral sides of the shielding units in the width direction exceed the lateral sides of the data signal lines in the width direction;
And forming a color film substrate, wherein the color film substrate comprises a plurality of non-splicing areas and splicing areas positioned between the non-splicing areas, and the array substrate and the color film substrate are arranged in a box-to-box manner.
In some embodiments, the step of forming the array substrate includes:
Providing a first substrate layer;
Depositing a shielding unit film layer on the first substrate layer;
And exposing, developing and etching the shielding unit film layer by adopting the Gate comprising the shielding unit pattern to obtain a plurality of shielding units which are arranged at intervals and are arranged on the same layer as the Gate.
In some embodiments, the step of forming the color film substrate includes:
providing a second substrate layer;
Depositing a black matrix film layer on the second substrate layer;
providing a first mask, wherein the first mask comprises a first exposure area, a second exposure area and a third exposure area which are sequentially connected, and the first exposure area and the third exposure area are provided with complementary mosaic patterns;
aligning the initial end of the second exposure area of the first mask plate with the initial end of the black matrix film layer, and exposing the black matrix film layer once to form a first black matrix positioned in a non-splicing area and a partial structure of the first black matrix positioned in the splicing area;
Moving the first mask, aligning the initial end of a first exposure area of the first mask with the initial end of the splicing area, and exposing the black matrix film layer for the second time to form a complete structure of a first black matrix in the splicing area and a partial structure of the first black matrix in a non-splicing area and a first black matrix in another splicing area;
And repeating the step of exposing for the second time until the exposure of the black matrix film layer is completed, and obtaining the color film substrate with a plurality of non-splicing areas and splicing areas.
In some embodiments, the step of forming the color film substrate includes:
Providing a second substrate layer comprising a plurality of non-spliced regions and spliced regions between the non-spliced regions;
Depositing a black matrix film layer on the second substrate layer;
Providing a second mask, wherein the second mask comprises a fourth exposure area, a fifth exposure area and a sixth exposure area which are sequentially connected, and the fourth exposure area and the sixth exposure area are provided with complementary mosaic patterns;
Aligning the initial end of the fifth exposure area of the second mask plate with the initial end of the black matrix film layer, and exposing the black matrix film layer once to form a first black matrix and a second black matrix which are positioned in a non-splicing area and a partial structure of the first black matrix and the second black matrix which are positioned in the splicing area;
Moving the second mask plate, aligning a fourth exposure area of the second mask plate with the initial end of the splicing area, and performing second exposure on the black matrix film layer to form complete structures of a first black matrix and a second black matrix in the splicing area and partial structures of the first black matrix and the second black matrix in the non-splicing area and the first black matrix and the second black matrix in the other splicing area;
And repeating the step of exposing for the second time until the exposure of the black matrix film layer is completed, and obtaining the color film substrate with a plurality of non-splicing areas and splicing areas.
In some embodiments, the width of the pattern of the second black matrix used for forming the pattern of the fourth exposure area and the width of the pattern of the sixth exposure area of the second mask plate used for forming the pattern of the second black matrix used for forming the pattern of the fifth exposure area have a first preset difference value; or alternatively
The width of the pattern of the fourth exposure area for forming the patterned second black matrix of the second mask plate and the width of the pattern of the fifth exposure area for forming the patterned second black matrix have a second preset difference value; or alternatively
The width of the pattern of the second black matrix used for forming the pattern of the sixth exposure area of the second mask plate and the width of the pattern of the second black matrix used for forming the pattern of the fifth exposure area have a third preset difference value.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other embodiments may be obtained according to these drawings to those skilled in the art.
Fig. 1 is a top view of an internal structure of a display panel according to an embodiment of the present application;
FIG. 2 is a cross-sectional view taken along section A-A of FIG. 1 in one embodiment;
FIG. 3 is a schematic diagram of a stitching exposure process;
FIG. 4 is a schematic diagram showing the contrast of the high gray scale simulated light effect of the non-spliced region and spliced region in the prior art;
FIG. 5 is a schematic diagram of the result of high gray scale simulation of the light effect in the stitching region corresponding to the structure of FIG. 2;
FIG. 6 is a cross-sectional view taken along section A-A of FIG. 1 in a second embodiment;
FIG. 7 is a graph showing the results of high gray scale simulation of the light effect in the stitching region corresponding to the structure of FIG. 6;
FIG. 8 is a cross-sectional view taken along section A-A of FIG. 1 in a third embodiment;
FIG. 9 is a schematic diagram showing the contrast of the high gray scale simulated light effects of the middle non-stitching region and stitching region corresponding to the structure of FIG. 8;
FIG. 10 is a cross-sectional view taken along section A-A of FIG. 1 in a fourth embodiment;
FIG. 11 is a schematic diagram showing the contrast of the high gray scale simulated light effects of the middle non-stitching region and stitching region corresponding to the structure of FIG. 10;
fig. 12 is a schematic diagram of a splicing method according to an embodiment of the present application.
The reference numerals are as follows: an array substrate 100; a first substrate layer 110; a first insulating layer 120; a shielding unit 121; a pixel electrode 130; a second insulating layer 140; a data signal line 141; a color film substrate 200; a non-stitching region 210; a stitching region 220; a second substrate layer 230; a second black matrix 240; width direction W.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.
An embodiment of the present application provides a display panel, in which a top view of the display panel is shown in fig. 1, and a schematic cross-sectional view of the display panel along A-A direction in a splicing area 220 is shown in fig. 2. As shown in fig. 2, the display panel includes an array substrate 100 and a color film substrate 200 disposed opposite to each other, the array substrate 100 includes a first substrate layer 110, a plurality of shielding units 121 disposed at intervals on a side of the first substrate layer 110 facing the color film substrate 200, and a plurality of data signal lines 141 disposed at intervals and parallel to each other on a side of the plurality of shielding units 121 facing the color film substrate 200. As shown in fig. 3, the color film substrate 200 includes a plurality of non-spliced regions 210 and spliced regions 220 between the non-spliced regions 210; orthographic projections of the splicing area 220 and the non-splicing area 210 in the direction of the first substrate layer 110 span across the plurality of data signal lines 141, the positions of the shielding units 121 are arranged in one-to-one correspondence with the data signal lines 141, and the sides of the shielding units 121 in the width direction W exceed the sides of the data signal lines 141 in the width direction W. The width direction W is understood to be a direction which is in the same plane as the extending direction of the data signal lines and perpendicular thereto.
It should be understood that the display panel further includes a backlight module (not shown), which may be disposed on a side of the color film substrate 200 away from the array substrate 100, or may be disposed on a side of the array substrate 100 away from the color film substrate 200, which is not limited in the present application.
As shown in fig. 3, the color film substrate 200 includes a plurality of non-spliced regions 210 and a spliced region 220 between the non-spliced regions 210, the non-spliced regions 210 are regions formed by one exposure, the spliced region 220 is a region formed by two exposure steps, and the spliced region 220 and the non-spliced region 210 each span the plurality of data signal lines 141, i.e. the spliced region 220 and the non-spliced region 210 each have a certain width, but the width of the spliced region 220 is much smaller than the width of the non-spliced region 210. Because the stitching region 220 is a region formed by stitching two exposures, in the stitching exposure process, there is inevitably an alignment error between the mask and the substrate to be exposed, so that the aperture ratio of the stitching region 220 after exposure and the aperture ratio of the non-stitching region 210 after exposure are slightly different, the aperture ratio can affect the light efficiency of the pixels, that is, the change of the light transmittance causes the display panel to macroscopically look to have poor stitching. Especially for oversized high resolution products, the pixels PPI (number of pixels per inch, pixels Per Inch) are higher, the openings are smaller, the sensitivity to transmittance changes caused by opening rate changes is higher, and the stitching Mura is more likely to occur. As shown in fig. 4, for example, the non-spliced region 210 and the spliced region 220 of the prior art are compared with each other in terms of high gray scale, and as can be seen from fig. 4, the display starting point of the edge light effect of the spliced region 220 starts from the inner two vertical lines, while the display starting point of the edge light effect of the non-spliced region 210 starts from the outer two vertical lines, i.e. the light effect of the spliced region 220 and the non-spliced region 210 is different, and the light effect of the spliced region 220 is smaller, if the display panel is observed from the macroscopic view at the same gray scale level, the brightness of the spliced region 220 is darker, and the spliced region is displayed as poor.
As shown in fig. 2, 6, 8 and 10, in order to reduce the difference between the aperture ratio of the splicing region 220 and the aperture ratio of the non-splicing region 210, a plurality of shielding units 121 are disposed at intervals on the side of the first substrate layer 110 facing the color film substrate 200. Specifically, the plurality of shielding units 121 may be formed by a deposition and etching process, gaps between the plurality of shielding units 121 are filled with an insulating material to form the first insulating layer 120, and then the plurality of data signal lines 141 are disposed at intervals on a side of the first insulating layer 120 facing the color film substrate 200. The first insulating layer 120 may be an inorganic insulating layer, such as a SiNx layer. A second insulating layer 140 is further disposed over the plurality of data signal lines 141, and the second insulating layer 140 may be an organic insulating layer such as epoxy, acryl polyimide, or the like. The data signal lines 141 are electrically connected to the sources of one row or column of thin film transistors, and are arranged in the same layer as the sources and the drains, the drains of the thin film transistors are electrically connected to the pixel electrode 130, and the pixel electrode 130 is 2 nd ITO as shown in fig. 2, 6, 8, and 10, wherein 1 st ITO is a common electrode. The plurality of data signal lines 141 may also be implemented by a deposition etching process. The side of the width direction W of the plurality of shielding units 121 exceeds the side of the width direction W of the data signal line 141, and since the shielding units 121 are arranged on the first layer of the first substrate layer 110, the width fluctuation of the shielding units 121 is small, so that the influence on the aperture ratio is small, the intensity of the edge light effect is directly influenced by the width of the shielding units 121 when being observed from the upper part of the display panel, the association degree between the edge light effect and the aperture ratio caused by splicing exposure is reduced, and poor splicing caused by splicing exposure can be reduced. The larger the aperture ratio, the higher the efficiency of light passing, so that the display effect of the display panel is better.
FIG. 5 is a schematic diagram of a high gray scale simulated light effect result of the stitching region 220 when the structural design of FIG. 2 is adopted; FIG. 7 is a schematic diagram of the result of the high gray scale simulation of the stitching region 220 when the structural design of FIG. 6 is adopted; FIG. 9 is a high gray scale simulated light effect contrast diagram for non-stitching region 210 and stitching region 220 using the structure design of FIG. 8; FIG. 11 is a graph showing the contrast of the simulated light effects of the non-tiled region 210 and the tiled region 220 with high gray scale using the structure design of FIG. 10. As can be seen from fig. 5, 7, 9 and 11, since the shielding unit 121 is designed, the position of the edge light effect display starting point of the splicing region 220 is closer to, even equal to, the position of the edge light effect display starting point of the non-splicing region 210, i.e. the range of poor splicing is reduced, and when the range is sufficiently small, the poor splicing is difficult to be recognized by naked eyes, so that the poor splicing is not seen from the appearance, i.e. the effect of improving the poor splicing of the splicing region 220 is achieved by arranging the shielding unit 121.
In addition, the sides of the shielding unit 121 in the width direction W may be more than the sides of the data signal line 141 in the width direction W, and light leakage caused by the data signal line 141 may be reduced.
In some embodiments of the present application, as shown in fig. 2 and 8, the shielding unit 121 is a first shielding block having a width greater than that of the data signal line 141 and a direction along which the data signal line 141 extends. In this embodiment, the width of the shielding unit 121, that is, the dimension along the width direction W, the shielding unit 121 is a continuous whole, which not only can reduce the dependency of the edge light effect on the aperture ratio caused by the splice exposure, but also can ensure the uniformity of the edge light effect, and can better reduce the light leakage caused by the data signal line 141.
In other embodiments of the present application, as shown in fig. 6 and 10, the shielding unit 121 is two second shielding blocks aligned and spaced in a direction consistent with the extending direction of the data signal line 141, and the sum of the widths and the spacing distances of the two second shielding blocks is greater than the width of the data signal line.
In this embodiment, the middle of the shielding unit 121 is disconnected, but the two sides of the shielding unit 121 in the width direction W still remain beyond the two sides of the data signal line 141 in the width direction W, that is, the sum of the widths and the spacing distances of the two second shielding blocks is greater than the width of the data signal line. The middle-intermittent shielding unit 121 can still reduce the dependency of the edge light effect on the aperture ratio caused by splicing exposure, and ensure the consistency of the edge light effect. The middle of the shielding unit 121 is disconnected, and the shielding unit 121 is not used as wide for the display panel with the larger width of the data signal line 141, thereby reducing the material cost and the process time cost of the shielding unit 121.
In some embodiments of the present application, as shown in fig. 2, 6, 8, and 10, the shielding unit 121 is made of a material including metal, such as copper, aluminum, and the like. The shielding unit 121 is made of a metal material, and is conveniently fabricated on the first substrate layer 110 by a deposition method. In addition, considering that the accuracy of the Array process is high, the exposure of the Array film layer is generally aligned with the Gate layer, so as to reduce the process fluctuation of the metal layer, the metal shares the Gate layer mask plate and is manufactured in the same layer with the Gate, and when the shielding unit 121 is manufactured by using a metal material, the same metal as the Gate layer can be adopted, thereby being convenient for manufacturing in the same layer with the Gate. The shielding unit 121 is different from Gate in that it is not necessary to apply voltage to the metal layer on the circuit, and the electrical properties such as pixel load and charging rate are not affected, and only used for shielding small part of light effect at the pixel edge, and reducing gray scale difference caused by variation of aperture ratio of oversized spliced exposure area.
In some embodiments of the present application, as shown in fig. 3, the stitching region 220 is formed by two exposures, the two exposures forming a pattern that is a complementary mosaic pattern.
In this embodiment, the complementary mosaic stitching is adopted, so that the line stitching can be converted into the area stitching, compared with the line stitching, the area stitching can reduce the alignment difficulty, and the poor caused by the alignment error is uniformly distributed in the stitching area 220, so that the poor stitching can be reduced, and thus the poor stitching is not easily recognized by human eyes. The mosaic exposure is usually divided by taking sub-pixels as minimum units, the patterns in the mosaic area are divided into two parts according to a certain random rule, and the mosaic exposure area has a certain width. As shown in fig. 1, the same Mask is used for exposure on both the left side B and the right side B of the Panel, the junction area between the two is the splicing area 220, the black matrix patterns in the left splicing area 220 and the right splicing area 220 of the actual Mask design are completely complementary, after the exposure is completed, the left and right sides are spliced into complete patterns, and meanwhile, a splicing exposure area with a certain width exists.
In some embodiments of the present application, as shown in fig. 2, 6, 8, and 10, the distance between the side edge of the shielding unit 121 and the side edge of the data signal line 141 is 0.4 micrometers-2 micrometers, for example, the distance between the side edge and the side edge may be 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 1 micrometer, 1.2 micrometers, 1.5 micrometers, and 2 micrometers.
In this embodiment, when the distance between the side edge of the shielding unit 121 and the side edge of the metal trace is too small, for example, less than 0.4 μm, the shielding effect on the aperture ratio difference caused by the splice exposure is insufficient, and thus the effect on improving the splice defect is poor. When the distance between the side edge of the shielding unit 121 and the side edge of the metal wire is too large, for example, greater than 2 micrometers, more display area is lost, which is not beneficial to improving the display effect of the display panel.
In some embodiments of the present application, as shown in fig. 3, the width of the splice area 220 is 30 mm-100 mm, e.g., the width of the splice area 220 may be 30 mm, 35 mm, 40mm, 60 mm, 70 mm, 90 mm, etc.
In this embodiment, when the width of the stitching region 220 is too narrow, for example, less than 30 mm, the alignment difficulty during stitching exposure is increased, so that an alignment error is more likely to occur, resulting in poor stitching. When the width of the splice area 220 is too wide, such as greater than 100 mm, the width of the non-splice area 210 is severely reduced, and the number of splice exposures is increased, increasing the chance of poor splice. Accordingly, the width of the splice area 220 is not too narrow or too wide, and it is reasonable that the splice area 220 be within a range of 30 mm to 100 mm.
In the above embodiments, the color film substrate 200 includes the second substrate layer 230; the second substrate layer 230 is provided with a first black matrix (not shown) on a side facing the TFT substrate, and the array substrate 100 further includes a plurality of gate signal lines (not shown) disposed parallel to each other and spaced apart from each other on a side facing the color film substrate 200 of the first substrate layer 110, where the projection of the gate signal lines and the data signal lines 141 are disposed to cross each other on the first substrate layer 110.
The Gate signal lines are fabricated on the same layer as the gates (Gate) of the thin film transistors, and the Gate signal lines are electrically connected with the gates of one row or column of thin film transistors, in this embodiment, the Gate signal lines may be disposed on the same layer as the shielding units 121, and the projections of the Gate signal lines and the data signal lines 141 on the first substrate layer 110 are disposed in a crossing manner, the first black matrixes are disposed in one-to-one correspondence with the Gate signal lines, and the orthographic projections of the first black matrixes in the substrate direction of the first substrate layer 110 can cover the orthographic projections of the Gate signal lines in the substrate direction of the first substrate layer 110.
In this embodiment, the color film substrate 200 includes only the first black matrix disposed opposite to the gate signal lines, and as shown in fig. 2 and 6, there is no black matrix at the position corresponding to the data signal line 141. Meanwhile, the normal Gate layer and the Com film layer are laid out on the Gate mask, the pattern of the shielding unit 121 is newly added below the data signal line 141 in the display area, and the width of the shielding unit 121 is larger than the width of the data signal line 141 by a certain value, namely the shielding unit 121 and the Gate are manufactured on the same layer. When the shielding unit 121 is made of a metal material, the shielding unit 121 does not affect the electrical properties such as the pixel load and the charging rate, and is only used for shielding a small part of the light effect at the edge of the pixel, and can play a role in shielding the light effect, similar to that of a black matrix, because no signal is provided on a circuit. Considering that the Array process precision is high, the first layer of the shielding unit 121 is made, the metal line width fluctuation is small, the influence of the process fluctuation on the aperture ratio and the transmittance is small, the Data-to-black matrix is removed, the difference of the widths of the Data-to-black matrix in the non-splicing area 210 and the splicing area 220 does not exist, and the risk of splicing Mura with the super-large-size Data-to-black matrix mosaic can be completely avoided.
Unlike the above-mentioned scheme of disposing the first black matrix only at the position opposite to the Gate metal trace, in another embodiment, as shown in fig. 8 and 10, a second black matrix 240 is further disposed on the side of the second substrate layer 230 facing the TFT substrate, that is, in this embodiment, a second black matrix 240 corresponding to the data signal line 141 is further disposed, and the orthographic projection of the second black matrix 240 in the substrate direction of the first substrate layer 110 can cover the orthographic projection of the data signal line 141 in the substrate direction of the first substrate layer 110, and the side edge in the width direction W of the shielding unit 121 exceeds the side edge in the width direction W of the second black matrix 240.
In this embodiment, due to the existence of the second black matrix 240, as shown in fig. 9 and 11, the width of the second black matrix 240 obtained by exposing the stitching region 220 twice is often larger than the width of the second black matrix 240 of the non-stitching region 210, and due to a certain light effect outside the second black matrix 240, the area ratio of 1 pixel without the first black matrix and the second black matrix 240 is generally defined as the aperture ratio, if the width of the second black matrix 240 changes, the light effect of the pixels is affected, that is, the transmittance changes, that is, the risk of poor stitching is increased, as can be seen from fig. 9 and 11, when the width of the second black matrix 240 of the stitching region 220 is inconsistent with the width of the second black matrix 240 of the non-stitching region 210, the display starting point positions of the edge light effects are directly caused, and when the differences are large, the existence of poor stitching can be recognized by naked eyes.
Illustratively, as shown in fig. 4, the non-stitching region 210 of the conventional pixel and the stitching region 220 have high gray scale analog light effect contrast, and the conventional pixel generates a lateral electric field between 1 st ITO and 2 nd ITO, so that the liquid crystal deflects toward the electric field direction, and no light in the region of the second black matrix 240 is transmitted to generate panel brightness. As shown in FIG. 3, the 2D section of a conventional pixel simulates the light effect, the leftmost to rightmost pixel is taken as a distance unit, the ordinate is taken as a brightness value, the pixel film structure and the liquid crystal deflection and electric field deflection conditions are taken below the curve, the brightness of the range outside the second black matrix 240 is more than 0 as known from the high gray scale light effect of the non-spliced region 210, the brightness of different positions is different due to the different liquid crystal deflection directions along with the different intensities and deflection directions of the electric field, and the light effect is strongest at the edge of the ITO slit of 2 nd. Based on the fact that the width of the second black matrix 240 of the splicing area 220 is 2 micrometers larger than that of the second black matrix 240 of the non-splicing area 210, high gray scale light effects of two areas are simulated, when the width of the second black matrix 240 of the splicing area 220 is +2 micrometers, edge light effects are covered by the width of the second black matrix 240, the simulated overall transmittance is reduced by more than 4%, gray scale differences L4.4, and generally high gray scale differences 2 gray scales are recognizable by naked eyes, and at the moment, splicing Mura is obviously visible and serious.
In this embodiment, the shielding unit 121 is disposed below the data signal line 141, and the side edge of the shielding unit 121 in the width direction W exceeds the side edge of the data signal line 141 in the width direction W, that is, the side edge of the shielding unit 121 in the width direction W exceeds both the side edge of the second black matrix 240 in the width direction W and the side edge of the data signal line 141 in the width direction W. When the width of the second black matrix 240 in the stitching region 220 changes, since the width of the shielding unit 121 is consistent between the width of the stitching region 220 and the width of the non-stitching region 210, the edge light effect of the stitching region 220 is directly affected by the width of the shielding unit 121, and thus the change of the edge light effect between the stitching region 220 and the non-stitching region 210 is consistent, the poor stitching caused by the change of the width of the second black matrix 240 due to stitching exposure can be reduced.
As shown in fig. 5, 7, 9 and 11, taking the example that the distance between the shielding unit 121 and the second black matrix 240 is 0.5 micrometers, the light efficiency of the non-splicing area 210 begins from the outside of the shielding unit 121, the shielding unit 121 shields the edge light efficiency of 0.5 micrometers, and the influence of shielding 0.5 micrometers on the overall transmittance is small because the light efficiency of the outermost edge is smaller; by evaluating the same standard (such as uniform fluctuation +2micron) of the second black matrix 240 width fluctuation, the second black matrix 240 width fluctuation of the splicing area 220 is 2 microns, which is equivalent to the single edge of the pixel losing only 0.5 microns of edge light effect, and as can be seen from fig. 5, the reduced edge light effect area is greatly reduced compared with the conventional pixel, the gray level difference L0.7 between the analog non-splicing area 210 and the splicing area 220 is simulated, and the difference can not be recognized by naked eyes within two gray levels, which can greatly improve the splicing Mura caused by oversized mosaic splicing.
A second aspect of the present application provides an electronic device comprising a display panel as described above.
In the electronic device according to the embodiment of the present application, the display panel includes a plurality of shielding units 121 disposed on a side of the second substrate layer 230 facing the color film substrate 200, where a side edge in a width direction W of the shielding units 121 exceeds a side edge in a width direction W of the data signal line 141, and since the shielding units 121 are disposed on the first layer of the first substrate layer 110, a width fluctuation of the shielding units 121 is small, so that an influence on an aperture ratio is small, so that when the electronic device is observed from a side of the array substrate 100, an intensity of an edge light effect is directly affected by the width of the shielding units 121, and a degree of association between the edge light effect and the aperture ratio caused by splicing exposure is reduced, so that a poor splicing caused by the splicing exposure can be reduced.
A third aspect of the embodiment of the present application provides a method for manufacturing a display panel, including the following steps:
S1: forming an array substrate 100, wherein the array substrate 100 comprises a first substrate layer 110, a plurality of shielding units 121 are arranged at intervals on one side of a substrate facing a color film substrate 200, and a plurality of data signal lines 141 are arranged at intervals on one side of the shielding units 121 facing the color film substrate 200, orthographic projections of a splicing region 220 and a non-splicing region 210 in the direction of the first substrate layer 110 respectively span the plurality of data signal lines 141, the shielding units 121 are arranged in one-to-one correspondence with the data signal lines 141, and the side edges of the shielding units 121 in the width direction W exceed the side edges of the data signal lines 141 in the width direction W;
S2: the color film substrate 200 is formed, the color film substrate 200 comprises a plurality of non-splicing areas 210 and splicing areas 220 positioned between the non-splicing areas 210, and the array substrate 100 and the color film substrate 200 are arranged in a box-to-box manner.
In the display panel manufactured by the method, since the plurality of shielding units 121 are arranged on the side, facing the color film substrate 200, of the second substrate layer 230, the side edge of the shielding unit 121 in the width direction W exceeds the side edge of the data signal line 141 in the width direction W, and since the shielding units 121 are arranged on the first layer of the first substrate layer 110, the width fluctuation of the shielding units 121 is small, so that the influence on the aperture ratio is small, the intensity of the edge light effect is directly influenced by the width of the shielding units 121 when the array substrate 100 is observed, the degree of association between the edge light effect and the aperture ratio caused by splicing exposure is reduced, and poor splicing caused by splicing exposure can be reduced.
In some embodiments, the step of forming the array substrate 100 includes:
s11: providing a first substrate layer 110;
s12: depositing a barrier cell film layer on the first substrate layer 110;
s14: and exposing, developing and etching the film layer of the shielding unit to a mask plate by adopting the Gate comprising the pattern of the shielding unit 121 to obtain a plurality of shielding units 121 which are arranged at intervals and are arranged on the same layer as the Gate.
More specifically, a photoresist layer is coated on the film layer of the shielding unit 121 before the film layer of the shielding unit is exposed; and then, exposing the shielding unit film layer to a mask plate by using Gate so as to denature the photoresist. The Gate mask includes a Gate pattern and a pattern of the shielding unit 121, that is, the shielding unit 121, the Gate and the Gate signal line are fabricated on the same layer, which not only simplifies the process, but also helps to reduce the thickness of the display panel. The pattern of the Gate on the mask is transferred to the photoresist by development, and the denatured photoresist is etched to obtain a plurality of shielding units 121 arranged at intervals and on the same layer as the Gate. A layer of insulating material is deposited on the shielding unit 121 to insulate the Gate from the shielding unit, facilitating independent operation of the Gate and the shielding unit.
In some embodiments, the step of forming the color film substrate 200 includes:
S21a: providing a second substrate layer 230;
S22a: depositing a black matrix film layer on the second substrate layer 230;
S23a: providing a first mask plate, wherein the first mask plate comprises a first exposure area, a second exposure area and a third exposure area which are sequentially connected, and the first exposure area and the third exposure area are provided with complementary mosaic patterns;
S24a: aligning the initial end of the second exposure area of the first mask plate with the initial end of the black matrix film layer, and exposing the black matrix film layer once to form a first black matrix positioned in the non-splicing area 210 and a partial structure of the first black matrix positioned in the splicing area 220;
s25a: moving the first mask, aligning the initial end of the first exposure region of the first mask with the initial end of the splicing region 220, and performing a second exposure on the black matrix film layer to form a complete structure of the first black matrix in the splicing region 220 and a partial structure of the first black matrix in the non-splicing region 210 and the first black matrix in the other splicing region 220;
s26a: and repeating the second exposure step until the exposure of the black matrix film layer is completed, thereby obtaining the color film substrate 200 with a plurality of non-splicing areas 210 and splicing areas 220.
In this embodiment, the first exposure area and the third exposure area of the first mask have mosaic patterns with complementary patterns, after the first exposure, a partial structure of the splicing area 220, that is, a partial structure of the first black matrix is obtained, and after the second exposure, a complete structure of the splicing area 220, that is, a complete first black matrix structure is obtained.
Because the first mask plate only comprises the first black matrix which is arranged corresponding to the grid signal line, the Data black matrix is removed, and the difference of the widths of the Data black matrixes in the non-splicing area 210 and the splicing area 220 does not exist, so that the risk of mosaic splicing Mura of the oversized Data black matrix can be completely avoided.
In other embodiments, the side edge of the shielding unit 121 in the width direction W exceeds the side edge of the second black matrix 240 in the width direction W, and the step of forming the color film substrate 200 further includes:
S21b: providing a second substrate layer 230, the second substrate layer 230 including a plurality of non-spliced regions 210 and spliced regions 220 between the non-spliced regions 210;
s22b: depositing a black matrix film layer on the second substrate layer 230;
s23b: providing a second mask plate, wherein the second mask plate comprises a fourth exposure area, a fifth exposure area and a sixth exposure area which are sequentially connected, and the fourth exposure area and the sixth exposure area are provided with complementary mosaic patterns;
S24b: aligning the initial end of the fifth exposure area of the second mask plate with the initial end of the black matrix film layer to expose the black matrix film layer once to form a first black matrix and a second black matrix 240 positioned in the non-splicing area 210 and partial structures of the first black matrix and the second black matrix 240 positioned in the splicing area 220;
S25b: moving the second mask, aligning the fourth exposure area of the second mask with the starting end of the splicing area 220, and performing a second exposure on the black matrix film layer to form a complete structure of the first black matrix and the second black matrix 240 in the splicing area 220 and a partial structure of the first black matrix and the second black matrix 240 in the non-splicing area 210 and the first black matrix and the second black matrix 240 in the other splicing area 220;
S26b: and repeating the second exposure step until the exposure of the black matrix film layer is completed, thereby obtaining the color film substrate 200 with a plurality of non-splicing areas 210 and splicing areas 220.
In this embodiment, the second mask includes not only the first black matrix corresponding to the gate signal lines, but also the second black matrix 240 corresponding to the data signal lines 141, and the side edge of the shielding unit 121 in the width direction W exceeds the side edge of the data signal lines 141 in the width direction W, i.e. the side edge of the shielding unit 121 in the width direction W exceeds both the side edge of the second black matrix 240 in the width direction W and the side edge of the data signal lines 141 in the width direction W. When the width of the second black matrix 240 in the stitching region 220 changes, since the width of the shielding unit 121 is consistent between the width of the stitching region 220 and the width of the non-stitching region 210, the edge light effect of the stitching region 220 is directly affected by the width of the shielding unit 121, and thus the change of the edge light effect between the stitching region 220 and the non-stitching region 210 is consistent, the poor stitching caused by the change of the width of the second black matrix 240 due to stitching exposure can be reduced.
In some embodiments, the width of the pattern of the second black matrix 240 used to form the pattern of the fourth and sixth exposure areas of the second reticle and the width of the pattern of the second black matrix 240 used to form the pattern of the fifth exposure area have a first preset difference; or the width of the pattern of the fourth exposure area of the second mask for forming the patterned second black matrix 240 and the width of the pattern of the fifth exposure area for forming the patterned second black matrix 240 have a second preset difference; or the width of the pattern of the sixth exposure area of the second mask for forming the patterned second black matrix 240 and the width of the pattern of the fifth exposure area for forming the patterned second black matrix 240 have a third preset difference.
In this embodiment, assuming that the width of the second black matrix 240 of the non-stitching region 210 is D, as shown in fig. 12, it can be understood that the stitching region 220a corresponds to the pattern after exposure of the sixth exposure region or the fourth exposure region when the second mask is first exposed, the stitching region 220b corresponds to the pattern after exposure of the fourth exposure region or the sixth exposure region when the second mask is second exposed, the width of the second black matrix 240 of the stitching region 220a is D1, the width of the second black matrix 240 of the stitching region 220b is D3, and the width of the second black matrix 240 formed after the stitching exposure is d+x=d1+d3-D2, where x is a variable, and can be obtained according to the actual measurement value or the empirical value, and D2 is the repeated exposure width, so that the width of the second black matrix 240 of the stitching region 220 is larger than the non-stitching region 210.
By subtracting x/2 from the width of the pattern used to form the patterned second black matrix 240 in the fourth exposure region, the width of the pattern used to form the patterned second black matrix 240 in the sixth exposure region is also subtracted by x/2, i.e. the width of the pattern used to form the patterned second black matrix 240 in the fourth exposure region and the width of the pattern used to form the patterned second black matrix 240 in the fifth exposure region both have the first preset difference x/2, the width of the second black matrix 240 formed after the two exposures of the stitching region 220 is narrower than the width of the second black matrix 240 in the non-stitching region 210 by x, and the difference that the width of the second black matrix 240 formed after the two stitching exposures is wider than the width of the second black matrix 240 in the non-stitching region 210 is exactly compensated, so that the width of the second black matrix 240 formed after the two stitching exposures is equal to the width of the second black matrix 240 formed by one exposure, and the phenomenon that the stitching region 220 is prone to generate poor stitching is further improved. The specific steps are that, assuming that the width of the second black matrix 240 of the non-stitching region 210 is D, after the first exposure of the stitching region 220, the width=d1-x/2 of the second black matrix 240 of the stitching region 220a, and the width=d3-x/2 of the second black matrix 240 of the stitching region 220b after the second exposure, the width of the second black matrix 240 formed after the completion of the stitching exposure is d=d1+d3-D2-x, so that the width of the second black matrix 240 of the stitching region 220 is equal to the width of the second black matrix 240 of the non-stitching region 210.
Similarly, to pre-correct the width of the second black matrix 240 in the stitching region 220, the width of the pattern used to form the patterned second black matrix 240 in the fourth exposure region may be directly subtracted by the difference x, i.e. the second preset difference is set to x. The specific steps are that the width of the second black matrix 240 in the stitching region 220 a=d1-x, the width of the second black matrix 240 in the stitching region 220 b=d3, and the width of the second black matrix 240 formed after stitching exposure is d=d1+d3-D2-x. Or the width of the pattern of the sixth exposure area for forming the patterned second black matrix 240 is directly subtracted by the difference X, i.e., the third preset difference is also X. The specific steps are that, assuming that the width of the second black matrix 240 of the non-stitching region 210 is D, the width=d1 of the second black matrix 240 of the stitching region 220a, the width=d3-x of the second black matrix 240 of the stitching region 220b, and the width of the second black matrix 240 formed after the stitching exposure is d=d1+d3-D2-x.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (11)

1. The display panel is characterized by comprising an array substrate and a color film substrate which are oppositely arranged, wherein the color film substrate comprises a plurality of non-spliced areas and spliced areas positioned between the non-spliced areas, the non-spliced areas are areas formed by one-time exposure, the spliced areas are areas formed by two front and rear exposure, and the two exposure forms a mosaic pattern with complementary patterns;
The array substrate includes: the color film comprises a first substrate layer, a plurality of shielding units arranged at intervals and arranged on one side of the first substrate layer facing the color film substrate, and a plurality of data signal lines which are parallel to each other and arranged at intervals and are arranged on one side of the shielding units facing the color film substrate;
The shielding unit is two second shielding blocks which are consistent with the extending direction of the data signal line and are arranged in parallel at intervals, and the sum of the width and the interval distance of the two second shielding blocks is larger than the width of the data signal line;
Orthographic projections of the splicing area and the non-splicing area in the first substrate layer direction all cross over a plurality of data signal lines, projection positions of the shielding units are arranged in one-to-one correspondence with the data signal lines, and the lateral sides of the shielding units in the width direction exceed the lateral sides of the data signal lines in the width direction;
the color film substrate comprises a second substrate layer, and a second black matrix is further arranged on one side, facing the array substrate, of the second substrate layer;
the orthographic projection of the second black matrix in the first substrate layer direction can cover the orthographic projection of the data signal line in the first substrate layer direction, and the lateral edge of the shielding unit in the width direction exceeds the lateral edge of the second black matrix in the width direction.
2. The display panel of claim 1, wherein the shielding unit is made of a material including metal.
3. The display panel according to claim 1, wherein a distance by which a side of the shielding unit exceeds a side of the data signal line is 0.4 micrometers to 2 micrometers.
4. The display panel of claim 1, wherein the stitching region has a width of 30 mm to 100 mm.
5. The display panel according to any one of claims 1 to 4, wherein a side of the second substrate layer facing the array substrate is provided with a first black matrix;
the array substrate further comprises a plurality of mutually parallel grid signal lines which are arranged at intervals and are arranged on one side of the first substrate layer facing the color film substrate, and the projection of the grid signal lines and the projection of the data signal lines on the first substrate layer are arranged in a crossing manner;
the first black matrixes are arranged in one-to-one correspondence with the grid signal lines, and orthographic projection of the first black matrixes in the direction of the first substrate layer can cover orthographic projection of the grid signal lines in the direction of the first substrate layer.
6. An electronic device, characterized in that the electronic device comprises the display panel of any one of claims 1-5.
7. A method for manufacturing a display panel according to any one of claims 1 to 5, comprising the steps of:
Forming an array substrate, wherein the array substrate comprises a first substrate layer, a plurality of shielding units are arranged at intervals on one side of the substrate, facing the color film substrate, and a plurality of data signal lines are arranged at intervals on one side of the shielding units, facing the color film substrate, the orthographic projections of the splicing area and the non-splicing area in the direction of the first substrate layer respectively span across the data signal lines, the shielding units are arranged in one-to-one correspondence with the data signal line areas, the shielding units are two second shielding blocks which are consistent with the extending direction of the data signal lines and are arranged in parallel at intervals, the sum of the width and the interval distance of the two second shielding blocks is larger than the width of the data signal lines, and the side edge of the width direction of each shielding unit exceeds the side edge of the width direction of the data signal line;
The color film substrate is formed and comprises a plurality of non-spliced areas and spliced areas positioned between the non-spliced areas, the color film substrate comprises a second substrate layer, one side of the second substrate layer, which faces the array substrate, is also provided with a second black matrix, the orthographic projection of the second black matrix in the direction of the first substrate layer can cover the orthographic projection of the data signal line in the direction of the first substrate layer, and the side edge of the width direction of the shielding unit exceeds the side edge of the width direction of the second black matrix, so that the array substrate and the color film substrate are arranged in a box-to-box mode.
8. The method of manufacturing a display panel according to claim 7, wherein the step of forming the array substrate comprises:
Providing a first substrate layer;
Depositing a shielding unit film layer on the first substrate layer;
And exposing, developing and etching the shielding unit film layer by adopting the Gate comprising the shielding unit pattern to obtain a plurality of shielding units which are arranged at intervals and are arranged on the same layer as the Gate.
9. The method of manufacturing a display panel according to claim 7, wherein the step of forming the color film substrate comprises:
providing a second substrate layer;
Depositing a black matrix film layer on the second substrate layer;
providing a first mask, wherein the first mask comprises a first exposure area, a second exposure area and a third exposure area which are sequentially connected, and the first exposure area and the third exposure area are provided with complementary mosaic patterns;
aligning the initial end of the second exposure area of the first mask plate with the initial end of the black matrix film layer, and exposing the black matrix film layer once to form a first black matrix positioned in a non-splicing area and a partial structure of the first black matrix positioned in the splicing area;
Moving the first mask, aligning the initial end of a first exposure area of the first mask with the initial end of the splicing area, and exposing the black matrix film layer for the second time to form a complete structure of a first black matrix in the splicing area and a partial structure of the first black matrix in a non-splicing area and a first black matrix in another splicing area;
And repeating the step of exposing for the second time until the exposure of the black matrix film layer is completed, and obtaining the color film substrate with a plurality of non-splicing areas and splicing areas.
10. The method of manufacturing a display panel according to claim 7, wherein the step of forming the color film substrate further comprises:
Providing a second substrate layer comprising a plurality of non-spliced regions and spliced regions between the non-spliced regions;
Depositing a black matrix film layer on the second substrate layer;
Providing a second mask, wherein the second mask comprises a fourth exposure area, a fifth exposure area and a sixth exposure area which are sequentially connected, and the fourth exposure area and the sixth exposure area are provided with complementary mosaic patterns;
Aligning the initial end of the fifth exposure area of the second mask plate with the initial end of the black matrix film layer, and exposing the black matrix film layer once to form a first black matrix and a second black matrix which are positioned in a non-splicing area and a partial structure of the first black matrix and the second black matrix which are positioned in the splicing area;
Moving the second mask plate, aligning a fourth exposure area of the second mask plate with the initial end of the splicing area, and performing second exposure on the black matrix film layer to form complete structures of a first black matrix and a second black matrix in the splicing area and partial structures of the first black matrix and the second black matrix in the non-splicing area and the first black matrix and the second black matrix in the other splicing area;
repeating the step of the second exposure until the exposure of the black matrix film layer is completed, and obtaining a color film substrate with a plurality of non-splicing areas and splicing areas;
Wherein the side edge of the shielding unit in the width direction exceeds the side edge of the second black matrix in the width direction.
11. The method for manufacturing a display panel according to claim 10, wherein the width of the pattern for forming the patterned second black matrix in the fourth exposure region and the sixth exposure region of the second mask has a first preset difference from the width of the pattern for forming the patterned second black matrix in the fifth exposure region; or alternatively
The width of the pattern of the fourth exposure area for forming the patterned second black matrix of the second mask plate and the width of the pattern of the fifth exposure area for forming the patterned second black matrix have a second preset difference value; or alternatively
The width of the pattern of the second black matrix used for forming the pattern of the sixth exposure area of the second mask plate and the width of the pattern of the second black matrix used for forming the pattern of the fifth exposure area have a third preset difference value.
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001272667A (en) * 2000-03-24 2001-10-05 Seiko Epson Corp Substrate for liquid crystal device, its manufacturing method, and liquid crystal device
CN1573442A (en) * 2003-05-28 2005-02-02 株式会社日立显示器 Liquid crystal display device
KR20050024639A (en) * 2003-09-01 2005-03-11 삼성전자주식회사 method for manufacturing a panel of a liquid crystal display
JP2006235258A (en) * 2005-02-25 2006-09-07 Toppan Printing Co Ltd Photomask and method for manufacturing color filter for liquid crystal display apparatus
CN1979344A (en) * 2003-12-30 2007-06-13 Lg.菲利浦Lcd株式会社 Exposure method using exposure mask
WO2009037965A1 (en) * 2007-09-19 2009-03-26 Sharp Kabushiki Kaisha Liquid crystal display panel manufacturing method and photomask
CN103852931A (en) * 2014-03-31 2014-06-11 南京中电熊猫液晶显示科技有限公司 BM deviation prevention liquid crystal display
WO2014132819A1 (en) * 2013-02-26 2014-09-04 堺ディスプレイプロダクト株式会社 Method for manufacturing color filter, and liquid crystal display device
CN104317132A (en) * 2014-11-14 2015-01-28 京东方科技集团股份有限公司 Color electronic paper
CN113707668A (en) * 2020-05-19 2021-11-26 荣耀终端有限公司 Array substrate, preparation method thereof, liquid crystal panel and display device
CN114077089A (en) * 2021-11-24 2022-02-22 京东方科技集团股份有限公司 Display panel and display device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100679516B1 (en) * 2000-08-02 2007-02-07 엘지.필립스 엘시디 주식회사 Liquid crystal display and fabricating method of the same
US9007432B2 (en) * 2010-12-16 2015-04-14 The Massachusetts Institute Of Technology Imaging systems and methods for immersive surveillance

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001272667A (en) * 2000-03-24 2001-10-05 Seiko Epson Corp Substrate for liquid crystal device, its manufacturing method, and liquid crystal device
CN1573442A (en) * 2003-05-28 2005-02-02 株式会社日立显示器 Liquid crystal display device
KR20050024639A (en) * 2003-09-01 2005-03-11 삼성전자주식회사 method for manufacturing a panel of a liquid crystal display
CN1979344A (en) * 2003-12-30 2007-06-13 Lg.菲利浦Lcd株式会社 Exposure method using exposure mask
JP2006235258A (en) * 2005-02-25 2006-09-07 Toppan Printing Co Ltd Photomask and method for manufacturing color filter for liquid crystal display apparatus
WO2009037965A1 (en) * 2007-09-19 2009-03-26 Sharp Kabushiki Kaisha Liquid crystal display panel manufacturing method and photomask
WO2014132819A1 (en) * 2013-02-26 2014-09-04 堺ディスプレイプロダクト株式会社 Method for manufacturing color filter, and liquid crystal display device
CN103852931A (en) * 2014-03-31 2014-06-11 南京中电熊猫液晶显示科技有限公司 BM deviation prevention liquid crystal display
CN104317132A (en) * 2014-11-14 2015-01-28 京东方科技集团股份有限公司 Color electronic paper
CN113707668A (en) * 2020-05-19 2021-11-26 荣耀终端有限公司 Array substrate, preparation method thereof, liquid crystal panel and display device
CN114077089A (en) * 2021-11-24 2022-02-22 京东方科技集团股份有限公司 Display panel and display device

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