CN115792561A - Dynamic aging test system and control method thereof - Google Patents
Dynamic aging test system and control method thereof Download PDFInfo
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- CN115792561A CN115792561A CN202211233235.6A CN202211233235A CN115792561A CN 115792561 A CN115792561 A CN 115792561A CN 202211233235 A CN202211233235 A CN 202211233235A CN 115792561 A CN115792561 A CN 115792561A
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Abstract
The invention belongs to the technical field of burn-in test, and discloses a dynamic burn-in test system and a control method thereof, which comprise a program downloading module for downloading a burn-in program for a chip, a communication module for configuring an I/O port of a device for data communication, a burn-in board module for fixing the device to be tested by using a burn-in board, a display module for sending parallel excitation by using a burn-in board upper computer, outputting 0 and 1, namely low level and high level, after the device works, transmitting the low level and the high level to the burn-in board upper computer module through a burn-in board bottom return detection signal, and displaying the output signal by using an oscilloscope and judging whether the device is dynamically burned in. The invention can realize the dynamic burn-in test of the device, designs the burn-in PCB which can realize the dynamic burn-in test and is used for the burn-in test detection of the integrated circuit, and carries out the dynamic burn-in test on the device according to the designed burn-in PCB, thereby solving the problem that the device has no dynamic burn-in detection capability.
Description
Technical Field
The invention belongs to the technical field of aging tests, and particularly relates to a dynamic aging test system and a control method thereof.
Background
At present, a burn-in test is a test technology capable of eliminating early faults of products, is an important item in component screening, and is a main method for eliminating early failure products and improving system reliability in engineering. Generally, the aging process simultaneously acts through two aspects of working environment stress and electrical performance stress, so that potential defects of some products are exposed in advance, and unqualified products are removed. The device subjected to aging screening is used on electronic equipment, so that faults can be reduced, the quality and reliability of the whole machine are improved, and the development and maintenance cost of the whole machine is saved.
With the increase of the complexity of military electronic products and equipment, the application range is increasingly wide, and the requirements on the reliability of the electronic products and the equipment are higher and higher. However, in practice, due to the control of the manufacturing process such as manufacturing process, flow, material, etc., the components inevitably leave defects in the manufacturing process, so that the reliability level of the components does not meet the design requirement, and the components may fail due to various reasons at any time. The prior art does not have the dynamic burn-in capability of the device or only carries out a simple static burn-in test according to the detailed specification of the device, the static burn-in means that only voltage is provided for a power supply end of a circuit, a signal input pin does not provide a burn-in vector, and at the moment, an internal transistor basically does not turn over. In the static aging test, the chip is connected with a power supply and the ground, and other input pins are connected in parallel with a resistor and connected with a power supply end, so that the reverse bias of a transistor in the circuit is basically realized. The main function of static aging is to induce failure mechanism related to impurity contamination in high temperature environment, so that the internal impurities are accelerated to migrate to the surface of the device under stable bias voltage of the circuit. During dynamic burn-in, the circuit is connected with a power supply and the ground, and a proper burn-in vector is added on an input pin, so that node overturning is realized inside the circuit, the dynamic burn-in can realize comprehensive investigation on the electrical characteristics of nodes, dielectric media and conductive paths inside the device, and compared with static burn-in, the potential defects of the circuit can be more effectively excited. So that the static aging does not achieve the effect of dynamic aging.
Through the above analysis, the problems and defects of the prior art are as follows: in the prior art, only simple static burn-in tests can be carried out on electronic products and equipment, a failure mechanism related to magazine pollution is induced in a high-temperature environment, so that internal magazines are accelerated to migrate to the surface of a device under a stable bias voltage, the electrical characteristics of internal nodes, dielectrics and conductive paths of the device cannot be comprehensively investigated, potential defects of the circuit cannot be effectively excited, and the effect of dynamic burn-in cannot be achieved.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a dynamic aging test system and a control method thereof.
The invention is realized in this way, a dynamic burn-in test system includes:
the program downloading module is used for downloading the aging program for the chip;
the communication module is used for configuring an I/O port of the device to carry out data communication;
the burn-in board module is used for fixing the device to be tested by using a burn-in board;
the upper computer module is used for sending parallel excitation by using an upper computer of the aging machine, outputting 0 and 1, namely low level and high level, after the device works, and transmitting a return detection signal to the upper computer of the aging machine through the bottom of the aging board;
and the display module is connected with the upper computer module and used for displaying the output signal by using the oscilloscope and judging whether the device is dynamically aged.
Further, the aging board is provided with an output signal return detection unit for monitoring the output signal.
Furthermore, the burn-in board adopts a complex programmable logic device and adopts an EEPROM or FASTFLASH programming technology.
Further, the aging board in the aging board module fixes the device to be tested by using a fixing clamp.
Furthermore, a VCC pin of the aging board is connected to VCC, a GND pin is connected to GND, bankB, D and F are configured to output 2K omega resistors to GND respectively, wherein a pin 1 is connected to a 300 omega resistor and then connected to a red LED lamp as an output indication;
the bankA, C and E are configured such that inputs are respectively connected to 2K Ω resistors to a digital channel, and OE and CLR enable pins are respectively connected to 2K Ω resistors to a digital channel.
Furthermore, the connection interface of the upper computer of the aging machine and the aging machine comprises 64 digital channels, 4 analog channels, 64 feedback channels, 3 power supplies, and all program control and programming.
Another object of the present invention is to provide a method for controlling a dynamic burn-in test system, which includes:
firstly, a program downloading module is used for downloading a burn-in program for a chip, then, bankA, C and E are configured to input and respectively connect 2K omega resistors to a digital channel, OE and CLR enable pins are respectively connected with 2K omega resistors to the digital channel, bankB, D and F are configured to output and respectively connect 2K omega resistors to GND, wherein 1 pin is connected with 300 omega resistors and then connected with a red LED lamp, an ELEA-V burn-in machine upper computer is used for providing a voltage power supply and sending corresponding parallel excitation signals, when the device works, 0 and 1, namely low level and high level, are output, a return detection output signal is transmitted to the burn-in machine upper computer through the bottom of an aging board, the burn-in machine upper computer displays the output signal by using an oscilloscope, and whether the device is dynamically burn-in or not is judged by outputting the high-low level signal.
In combination with the technical solutions and the technical problems to be solved, please analyze the advantages and positive effects of the technical solutions to be protected in the present invention from the following aspects:
first, aiming at the technical problems existing in the prior art and the difficulty in solving the problems, the technical problems to be solved by the technical scheme of the present invention are closely combined with results, data and the like in the research and development process, and some creative technical effects are brought after the problems are solved. The specific description is as follows:
the invention can realize the dynamic burn-in test of the device, designs the burn-in PCB which can realize the dynamic burn-in test and is applied to the burn-in test detection work of the integrated circuit. The dynamic burn-in test is carried out on the device according to the designed burn-in board, the defect that the device has no dynamic burn-in detection capability is solved, the defect that the complex programmable logic device CPLD cannot be dynamically burned in is overcome, and the problem that the existing CPLD chip burn-in test method cannot completely investigate the electrical characteristics of internal nodes, dielectric medium and conductive paths of the device is solved.
Secondly, considering the technical scheme as a whole or from the perspective of products, the technical effect and advantages of the technical scheme to be protected by the invention are specifically described as follows:
the invention solves the problem that large-scale devices cannot be dynamically aged, further improves the quality and reliability of the whole machine, saves the development and maintenance cost of the whole machine, and can intuitively see whether the output result of the dynamic aging is realized or not after parallel excitation signals are input into the upper plate of the device.
Third, as an inventive supplementary proof of the claims of the present invention, there are also presented several important aspects:
(1) The expected income and commercial value after the technical scheme of the invention is converted are as follows:
the device after dynamic burn-in screening is used on electronic equipment, so that faults can be reduced, the quality and reliability of the whole machine are improved, and the development and maintenance cost of the whole machine is further saved.
(2) The technical scheme of the invention solves the technical problems which are always desired to be solved but are not successfully achieved:
the invention can realize the dynamic burn-in test of the device, designs the burn-in PCB which can realize the dynamic burn-in test and is applied to the burn-in test detection work of the integrated circuit. The dynamic burn-in test is carried out on the device according to the designed burn-in board, the defect that the device has no dynamic burn-in detection capability is solved, the defect that the complex programmable logic device CPLD cannot be dynamically burned in is overcome, and the problem that the existing CPLD chip burn-in test method cannot completely investigate the electrical characteristics of internal nodes, dielectric medium and conductive paths of the device is solved.
Drawings
FIG. 1 is a functional block diagram of a dynamic burn-in test system provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of an XCR3256XL-10TQG I aging board provided by an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of XCR3256XL-10TQG I provided by an embodiment of the present invention;
fig. 4 is a schematic diagram of an interface between a machine and a burn-in board according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
1. The embodiments are explained. This section is an illustrative example developed to explain the claims in order to enable those skilled in the art to fully understand how to implement the present invention.
As shown in fig. 1, which is a schematic block diagram of a dynamic burn-in design of XCR3256XL-10TQG I according to an embodiment of the present invention, a burn-in program is downloaded to a chip, and then a device I/O port is configured, an ELEA-V burn-in machine upper computer is used to send parallel excitation, when the device operates, 0 and 1, i.e., a low level and a high level, are output, a return detection signal from the bottom of an burn-in board is transmitted to the burn-in machine upper computer, and the burn-in machine upper computer displays the output signal through an oscilloscope, so that whether the device is performing dynamic burn-in can be determined.
The XCR3256XL-10TQG I chip is a complex programmable logic device which is produced by XILINX manufacturers and has 120I/O ports, the CPLD is more suitable for finishing various algorithms and combinational logic, and the programming adopts an EEPROM or FASTFLASH technology without using an external memory chip; and before aging, downloading the program by using a downloading board.
The aging principle is researched and developed according to the test condition D-parallel excitation in GJB548B-2005-1015.1, the printed board is strictly designed according to the aging principle diagram, and an imported special fixture is selected as shown in figure 2, so that the good contact of devices in the aging process is ensured; meanwhile, when the printed board is designed and arranged, the current carrying capacity of each line and the heat dissipation function of the whole board are fully considered, and 15 chips can be simultaneously aged by the single board at present.
Meanwhile, in order to facilitate output measurement, an XCR3256XL-10TQG I aging board designs output signals for return inspection according to aging requirements, facilitates monitoring of the output signals, can well monitor the working state and the electrical property of a device through an oscilloscope and an instrument and meter, and meets the requirements of aging test indexes.
In summary, the XCR3256XL-10TQG I aging board has the characteristics of simplicity in operation, convenience in monitoring equipment and instruments and the like, aging test indexes meet the electrical performance aging requirements of devices, and the overall layout is shown in FIG. 2.
XCR3256XL-10TQG I principle is as shown in FIG. 3, wherein a VCC pin is connected to VCC, a GND pin is connected to GND, bankB, D and F are configured to output 2K omega resistors to GND respectively, wherein a 1 pin is connected to a 300 omega resistor and then connected to a red LED lamp as an output indication; bankA, C, E are configured such that inputs are respectively connected to 2K Ω resistors to the digital channel, and OE, CLR enable pins are respectively connected to 2K Ω resistors to the digital channel.
The device downloads a burn-in program, and the upper computer of the burn-in machine sends parallel excitation through the burn-in board. And each device fixes a certain output pin to be connected to a back rechecking channel of the aging board, and when the device works, the upper computer of the aging machine can receive an output rechecking signal and display the waveform of the output signal on an oscilloscope.
The machine and burn-in board interface is shown in fig. 4, and provides 64 digital channels, 4 analog channels, 64 return channels, 3 power supplies, and is all programmable.
The burn-in test difficulty of the programmable logic device-CPLD device is to realize the dynamic burn-in test of the device, design a dynamic burn-in test method of an XCR3256XL-10TQG I chip, design a burn-in PCB capable of realizing the dynamic burn-in test, and apply the burn-in test detection work of an integrated circuit XCR3256XL-10TQG I. The device is subjected to dynamic burn-in test according to the designed burn-in board, the defects that the device has no dynamic burn-in detection capability, a Complex Programmable Logic Device (CPLD) cannot be dynamically burned in are overcome, and the problem that the existing CPLD chip burn-in test method cannot completely observe the electrical characteristics of nodes, dielectrics and conductive paths inside the device is solved.
2. Application examples. In order to prove the creativity and the technical value of the technical scheme of the invention, the part is the application example of the technical scheme of the claims on specific products or related technologies.
The invention has successfully carried out dynamic aging on XCR3256XL-10TQG I devices, and the electrical performance of the devices is tested after the aging is finished, and the electrical parameters are all in the specified range of a manual, which indicates that the aging scheme is a nondestructive test and can realize the dynamic aging of the devices.
It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus and its modules of the present invention may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of hardware circuits and software, e.g., firmware.
3. Evidence of the relevant effects of the examples. The embodiment of the invention achieves some positive effects in the process of research and development or use, and has great advantages compared with the prior art, and the following contents are described by combining data, diagrams and the like in the test process.
The prior art does not have the dynamic burn-in capability of the device or only carries out a simple static burn-in test according to the detailed specification of the device, wherein the static burn-in means that only voltage is provided for a power supply end of a circuit, a signal input pin does not provide a burn-in vector, and at the moment, an internal transistor basically does not turn over. In the static aging test, the chip is connected with a power supply and the ground, and other input pins are connected in parallel with a resistor and connected with a power supply end, so that the reverse bias of a transistor in the circuit is basically realized. The main function of static aging is to induce failure mechanism related to impurity contamination in high temperature environment, so that the internal impurities in the circuit are accelerated to migrate to the surface of the device under stable bias. During dynamic burn-in, the circuit is connected with a power supply and the ground, and a proper burn-in vector is added on an input pin, so that node overturning is realized inside the circuit, the dynamic burn-in can realize comprehensive investigation on the electrical characteristics of nodes, dielectric media and conductive paths inside the device, and compared with static burn-in, the potential defects of the circuit can be more effectively excited.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A dynamic burn-in test system, the dynamic burn-in test system comprising:
the program downloading module is used for downloading the aging program for the chip;
the communication module is used for configuring an I/O port of the device to carry out data communication;
the aging plate module is used for fixing the device to be tested by using the aging plate;
the upper computer module is used for sending parallel excitation by using an upper computer of the aging machine, outputting 0 and 1, namely low level and high level, after the device works, and transmitting a return detection signal to the upper computer of the aging machine through the bottom of the aging board;
and the display module is connected with the upper computer module and used for displaying the output signal by using the oscilloscope and judging whether the device is dynamically aged.
2. The dynamic burn-in test system of claim 1, wherein the burn-in board is provided with an output signal return unit for monitoring the output signal.
3. The dynamic burn-in test system of claim 1, wherein the burn-in board employs complex programmable logic devices employing EEPROM or FASTFLASH programming technology.
4. The dynamic burn-in test system of claim 1, wherein the burn-in board of the burn-in board module secures the device under test with a securing fixture.
5. The dynamic aging test system of claim 1, wherein the VCC pin of the aging board is connected to VCC, the GND pin is connected to GND, bankB, D, F are configured to output 2K Ω resistors to GND respectively, wherein 1 pin is connected to 300 Ω resistor and then connected to red LED lamp as output indication;
the bankA, C and E are configured such that inputs are respectively connected to 2K Ω resistors to a digital channel, and OE and CLR enable pins are respectively connected to 2K Ω resistors to a digital channel.
6. The dynamic burn-in test system of claim 1, wherein the connection interface between the burn-in machine host and the burn-in machine comprises 64 digital channels, 4 analog channels, 64 return-to-the-same-channel, 3 power supplies, all programmable and programmable.
7. A control method for the dynamic burn-in test system of any one of claims 1 to 6, wherein the control method for the dynamic burn-in test system comprises:
firstly, a program downloading module is used for downloading a burn-in program for a chip, then bankA, C and E are configured to input and respectively connect 2K omega resistors to a digital channel, OE and CLR enable pins are respectively connected with 2K omega resistors to the digital channel, bankB, D and F are configured to output and respectively connect 2K omega resistors to GND, wherein 1 pin is connected with 300 omega resistors and then connected with a red LED lamp, an ELEA-V burn-in machine upper computer is used for providing a voltage power supply and sending corresponding parallel excitation signals, when the device works, 0 and 1, namely low level and high level, are output, a burn-in output signal is transmitted to the burn-in machine upper computer through the bottom of an aging board, the burn-in machine upper computer displays the output signal by using an oscilloscope, and whether the device is dynamically burn-in or not is judged by outputting a high-low level signal.
8. A computer arrangement, characterized in that the computer arrangement comprises a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of the method of controlling a dynamic burn-in test system as claimed in claim 7.
9. A computer-readable storage medium, storing a computer program which, when executed by a processor, causes the processor to perform the steps of the method of controlling a dynamic burn-in test system of claim 7.
10. An information data processing terminal characterized by being used for realizing the steps of the control method of the dynamic burn-in test system according to claim 7.
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| CN202211233235.6A CN115792561A (en) | 2022-10-10 | 2022-10-10 | Dynamic aging test system and control method thereof |
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| CN202211233235.6A CN115792561A (en) | 2022-10-10 | 2022-10-10 | Dynamic aging test system and control method thereof |
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| CN115792561A true CN115792561A (en) | 2023-03-14 |
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| CN202211233235.6A Pending CN115792561A (en) | 2022-10-10 | 2022-10-10 | Dynamic aging test system and control method thereof |
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