CN115776292A - Clock phase modulation circuit, clock phase modulation method, and computer-readable storage medium - Google Patents

Abstract

The embodiment of the invention relates to the technical field of clock phase modulation in chip design, and discloses a clock phase modulation circuit, a clock phase modulation method and a computer readable storage medium, wherein the clock phase modulation circuit comprises a detection circuit, a controller and a phase modulation circuit; the detection circuit is configured to detect phase modulation parameters corresponding to the chip and output the phase modulation parameters; the phase modulation parameters comprise working parameters of the chip and/or environmental parameters of the environment where the chip is located; the controller is coupled to the output of the detection circuit and configured to: generating a clock control signal based on the received phase modulation parameters and outputting the clock control signal; the phase modulation circuit is coupled to an output of the controller and configured to: according to the received clock control signal, the clock input signal is phase modulated and the clock output signal is output. By applying the technical scheme of the invention, the phase modulation precision and flexibility of the clock phase modulation circuit can be improved, and the application scene of the clock phase modulation circuit is expanded.

Description

Clock phase modulation circuit, clock phase modulation method, and computer-readable storage medium

Technical Field

The embodiment of the invention relates to the technical field of clock phase modulation in chip design, in particular to a clock phase modulation circuit, a clock phase modulation method and a computer readable storage medium.

Background

The clock phase modulation circuit is an indispensable circuit in a chip, and in common chip design, when a peripheral chip is butted, a clock phase modulation circuit technology is required to be utilized. For a chip with a higher requirement on Circuit speed, such as an Application Specific Integrated Circuit (ASIC), since different conditions (such as environment, temperature, voltage, etc.) may affect the precision of the clock phase modulation Circuit, the precision of the clock phase modulation Circuit changes, and thus a clock phase modulation Circuit suitable for different conditions is required.

Disclosure of Invention

In view of the above problems, embodiments of the present invention provide a clock phase modulation circuit and a clock phase modulation method, where the clock phase modulation circuit has higher precision and higher flexibility, and can be applied to different conditions, and the problems of low precision and poor flexibility of the clock phase modulation circuit in the prior art are solved.

According to an aspect of an embodiment of the present invention, there is provided a clock phase modulation circuit including a detection circuit, a phase modulation circuit, and a controller. The detection circuit is configured to detect phase modulation parameters corresponding to the chip and output the phase modulation parameters; the phase modulation parameters comprise working parameters of the chip and/or environmental parameters of the environment where the chip is located. The controller is coupled to the output of the detection circuit and configured to: a clock control signal is generated based on the received phase modulation parameters and output. The phase modulation circuit is coupled to an output of the controller and configured to phase modulate a clock input signal and output a clock output signal according to a received clock control signal.

In an optional manner, the clock phasing circuit further comprises a configuration circuit coupled to an input of the controller and configured to: the phase-modulated parameters are compensated.

In an alternative manner, the phase modulation circuit includes M clock delay units coupled in sequence, where M is an integer greater than 1; the clock control signal is used for indicating the M clock delay units, phase modulation is carried out on the clock input signal according to the phase modulation parameters, and a phase-modulated clock signal is obtained.

In an optional manner, a first input terminal of a first clock delay unit of the M clock delay units is configured to receive a clock control signal, a second input terminal of the first clock delay unit is configured to receive a clock input signal, and a third input terminal of the first clock delay unit is configured to receive a preset value; the first output end of the first clock delay unit is used for outputting the phase-modulated clock signal. A first input end of an ith clock delay unit in the M clock delay units is used for receiving a clock control signal, a second input end of the ith clock delay unit is coupled with a second output end of the (i-1) th clock delay unit, and a third input end of the ith clock delay unit is coupled with a third output end of the (i-1) th clock delay unit; the first output end of the ith clock delay unit is coupled with the fourth input end of the (i-1) th clock delay unit; wherein i is an integer greater than 1 and less than or equal to M.

In an alternative form, the clock delay unit includes: the first NAND gate, the second NAND gate, the third NAND gate and the first inverter. The two input ends of the first nand gate are respectively a second input end of the clock delay unit and a third input end of the clock delay unit, and the output end of the first nand gate is a second output end of the clock delay unit. One input end of the second NAND gate is coupled with the output end of the first NAND gate, and the other input end of the second NAND gate is the first input end of the clock delay unit. One input end of the third nand gate is coupled to the output end of the second nand gate, the other input end of the third nand gate is a fourth input end of the clock delay unit, and the output end of the third nand gate is a first output end of the clock delay unit. The input end of the first inverter is coupled to the other input end of the second nand gate, and the output end of the first inverter is a third output end of the clock delay unit.

In an alternative form, the phase modulation circuit further comprises a second inverter and a selector. A first input of the selector is coupled to the first output of the first clock delay unit for receiving the phase-modulated clock signal. A second input of the selector is coupled to an input of the second inverter, the second input of the selector being configured to receive the clock input signal. The third input terminal of the selector is coupled to the output terminal of the second inverter. The selector is used for outputting a clock output signal according to the selection signal, wherein the clock output signal is a phase-modulated clock signal, or a clock input signal, or a signal obtained by inverting the phase of the clock input signal.

In an alternative form, the operating parameters include voltage parameters and/or current parameters; the environmental parameter includes a temperature parameter.

In an alternative approach, the controller is an eFuse controller.

According to another aspect of the embodiments of the present invention, there is provided a clock phasing method, including: acquiring phase modulation parameters corresponding to a chip; the phase modulation parameters comprise working parameters of the chip and/or environmental parameters of the environment where the chip is located; a clock control signal for phase modulating a clock input signal is generated based on the phase modulation parameter.

According to a further aspect of an embodiment of the present invention, there is provided a computer-readable storage medium having at least one executable instruction stored therein, the executable instruction causing a clock modulation circuit to perform the clock phase modulation method in the above-mentioned embodiment.

According to some embodiments of the present invention, a clock phase modulation circuit includes a detection circuit, which can detect phase modulation parameters corresponding to a chip and send the phase modulation parameters to a controller; the controller generates a clock control signal based on the received phase modulation parameters and sends the clock control signal to the phase modulation circuit; the phase modulation circuit modulates the phase of the clock input signal according to the clock control signal and outputs a clock output signal. Because the phase modulation parameters comprise the working parameters of the chip and/or the environmental parameters of the environment where the chip is located, the clock control signal generated according to the phase modulation parameters can phase modulate the clock input signal based on the working scene and the environmental condition of the chip. That is to say, the clock phase modulation circuit can control the phase modulation circuit to perform clock phase modulation according to different conditions (such as environment, temperature, voltage and the like), so that the phase modulation precision of the clock phase modulation circuit can be improved, the flexibility of the clock phase modulation circuit is also improved, the clock phase modulation circuit can be suitable for different conditions, and the application scene of the clock phase modulation circuit is expanded.

The foregoing description is only an overview of the technical solutions of the embodiments of the present invention, and the embodiments of the present invention can be implemented according to the content of the description in order to make the technical means of the embodiments of the present invention more clearly understood, and the detailed description of the present invention is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present invention more clearly understandable.

Drawings

The drawings are only for purposes of illustrating embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a clock phasing circuit provided by the present invention;

FIG. 2 is a schematic diagram of another clock phasing circuit provided by the present invention;

FIG. 3 shows a schematic diagram of a phase modulation circuit provided by the present invention;

FIG. 4 is a schematic diagram of yet another clock phasing circuit provided by the present invention;

fig. 5 shows a flow chart of a clock phase modulation method provided by the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein.

Clock phasing circuits are an integral part of ASIC systems today. In some examples, the clock phase modulation circuit can be implemented by inverting a clock input signal, and the clock phase modulation circuit implemented in this way cannot implement high-precision clock phase modulation. In addition, clock phasing circuits typically include programmable delay cells, since the delay of the same delay cell may differ under different conditions, e.g., the delay of the same delay cell may differ at different process angles (kners), different voltages, or different temperatures. In this case, the clock phase modulation circuit needs to adjust the number of delay units frequently to achieve the same phase shift, and thus, the clock phase modulation circuit also has high flexibility and cannot be applied to different conditions. In other examples, a phase-locked loop-based clock phase modulation circuit can solve the problem of insufficient phase-shifting precision in an analog circuit, but the clock phase modulation circuit implemented in the mode is not generally suitable for a digital circuit system.

To this end, an embodiment of the present invention provides a clock phase modulation circuit, as shown in fig. 1, which may include: phase modulation circuit 10, controller 20 and detection circuit 30. Wherein an output of detection circuit 30 is coupled to an input of controller 20, and an output of controller 20 is coupled to an input of phase modulation circuit 10.

In some examples, clock phasing circuit 100 may be disposed on a Chip, such as an ASIC, a System on Chip (SoC), and so on, which is not limited by this disclosure.

Illustratively, as shown in fig. 1, another input terminal of phase modulation circuit 10 may be coupled to an output terminal of clock source circuit 200, clock source circuit 200 being configured to provide a clock input signal to phase modulation circuit 10, phase modulation circuit 10 phase modulating the clock input signal.

In some examples, clock source circuit 200 may be integrated in clock phasing circuit 100, or clock source circuit 200 may not be provided in clock phasing circuit 100. For example, the clock source circuit 200 may be disposed at another location of the chip where the clock phase modulation circuit 100 is located, independently from the clock phase modulation circuit 100. In the embodiment of the present application, a setting position of the clock source circuit 200 is not limited, and fig. 1 illustrates an example in which the clock source circuit 200 is integrated in the clock phase modulation circuit 100. Illustratively, clock source circuit 200 may be an oscillator circuit.

Since the precision of the clock phase modulation circuit 100 may change under different PVT (Process, voltage) environments, the embodiment of the present invention may detect the PVT environment of the chip by adding the detection circuit 30.

In some embodiments, detection circuit 30 is configured to detect a phase modulation parameter corresponding to the chip and output the phase modulation parameter. The phase modulation parameters comprise working parameters of the chip and/or environmental parameters of the environment where the chip is located.

In some embodiments, the operating parameter comprises a voltage parameter and/or a current parameter of the chip; the environmental parameter includes a temperature parameter.

Specifically, after the detection circuit 30 detects the phase modulation parameter corresponding to the chip, the phase modulation parameter may be sent to the controller 20 periodically or aperiodically. For example, the detection circuit 30 may send the detected phase modulation parameters to the controller 20 every preset time period, or the detection circuit 20 may send the phase modulation parameters after change to the controller 20 when the phase modulation parameters corresponding to the chip change, which is not limited in the present invention.

For example, when the environmental parameter is a Temperature parameter, the detection circuit 30 may be a Temperature monitoring Controller (TDC), the TDC may detect a Temperature of the chip during operation, and when the Temperature of the chip changes, the TDC sends the changed Temperature parameter to the Controller 20, so that the Controller 20 can phase-modulate the clock input signal according to the Temperature adaptability of the chip during operation.

In some embodiments, the controller 20 is configured to: generating a clock control signal based on the received phase modulation parameters and outputting the clock control signal; phase modulation circuit 10 is configured to: according to the received clock control signal, the clock input signal is phase modulated and the clock output signal is output.

In some examples, controller 20 may store the phase modulation parameters after receiving the phase modulation parameters sent from detection circuit 30.

In some embodiments, controller 20 may also include a memory that may store the received phase modulation parameters. Controller 20 generates a clock control signal suitable for phase modulation circuit 10 by invoking phase modulation parameters stored in memory, which is used to control phase modulation circuit 10 to phase modulate a clock input signal according to the clock control signal.

Illustratively, the controller 20 may be an eFuse controller. The eFuse controller may include eFuses, which are one-time programmable memories and may store the phase modulation parameters sent by the detection circuit 30; the eFuse controller processes the phase modulation parameter according to the phase modulation parameter stored in the eFuse to generate the clock control signal corresponding to the phase modulation parameter.

To further increase the flexibility of the clock phase modulation circuit 100, fig. 2 is a schematic diagram of another clock phase modulation circuit provided by the present invention. As shown in fig. 2, clock phasing circuit 100 may further comprise configuration circuit 40, wherein an output of configuration circuit 40 is coupled to another input of controller 20.

In some embodiments, the configuration circuitry 40 is configured to: the phase modulation parameters detected by the detection circuit 30 are compensated.

Specifically, when the detection circuit 30 detects the operating parameter and/or the environmental parameter of the chip, a detection error may occur, that is, a certain error exists between the phase modulation parameter acquired by the detection circuit 30 and the target phase modulation parameter, and the error may affect the phase modulation value of the phase modulation circuit 10. Therefore, the configuration circuit 40 is added to the clock phasing circuit 100 to compensate and correct the detection result of the detection circuit 30 and send the compensation parameter to the controller 20, so that the controller 20 can generate the clock control signal according to the target phasing parameter. The target phase modulation parameter is determined by the phase modulation parameter sent by the detection circuit 30 and the compensation parameter sent by the configuration circuit 40.

In some examples, the compensation parameters sent by configuration circuitry 40 may be obtained through a number of tests. For example, when the detection circuit 30 is a TDC, there may be a certain error between the detected temperature of the TDC and the actual temperature of the chip, and an error value of the temperature may be obtained through a large number of tests and sent to the controller 20 through the configuration circuit 40.

In some embodiments, configuration circuit 40 may also be configured to receive target phasing parameters and to send the received target phasing parameters to controller 20. For example, when the clock phase modulation circuit 100 includes the configuration circuit 40 but does not include the detection circuit 30, a user may input a desired target phase modulation parameter through the configuration circuit 40, where the target phase modulation parameter is used to instruct the controller 20 to generate a target clock control signal, so that the phase modulation circuit 10 performs phase modulation on a target value of a clock input signal according to the target clock control signal to obtain a clock output signal.

Because the clock phase modulation circuit 100 can generate the clock control signal according to the phase modulation parameters of the chip, or according to the phase modulation parameters and the compensation parameters of the chip, or according to the target phase modulation parameters, the clock phase modulation circuit 100 can be applied to different PVT environments, performs self-adaptive phase modulation, and can perform phase modulation according to the requirements of users, and compared with the clock phase modulation circuit in the related art, the flexibility of the clock phase modulation circuit is greatly improved.

Fig. 3 is a schematic diagram of a phase modulation circuit 10 according to the present invention. As shown in fig. 3, phase modulation circuit 10 may include M clock delay units coupled in sequence, where M is an integer greater than 1, and the M clock delay units are clock delay unit 1 (also referred to as the first clock delay unit or the 1 st clock delay unit), clock delay unit 2, … …, and clock delay unit M, respectively.

In some examples, M may be set to 32, or M may also be set to another integer greater than 32 or smaller than 32, and M may be set according to actual requirements, which is not limited in the present invention.

Illustratively, the number M of clock delay units may be determined according to the specific situation of the chip on which the clock phase modulation circuit 100 is located. In some examples, the greater the number of clock delay units in phase modulation circuit 10, the higher the phase modulation accuracy of clock phase modulation circuit 100. For example, if the target phase modulation value to be realized by phase modulation circuit 10 is 4 nanoseconds (ns), when M is 32, phase modulation circuit 10 includes 32 clock delay units, and the phase modulation value of each clock delay unit can reach 125ps. For another example, when M is 64, the phase modulation circuit 10 includes 64 clock delay units, and the phase modulation value of each clock delay unit can reach about 63ps, which is more precise than M being 32.

It should be noted that M clock delay units in phase modulation circuit 10 may indicate that phase modulation circuit 10 may implement phase adjustment of M steps. For example, when M is 32, if the target phase modulation value to be realized by phase modulation circuit 10 is 4 nanoseconds (ns), the phase modulation value that can be achieved by each clock delay unit is 125 picoseconds (ps), and compared with the phase modulation value (e.g., 32 ns) that can be generally realized in the related art, the phase modulation accuracy of clock phase modulation circuit 100 is higher; meanwhile, the phase modulation value of each clock delay unit in the phase modulation circuit 10 is small, so that high-precision phase adjustment can be realized.

In some embodiments, each clock delay unit includes four inputs, a first input I-1, a second input I-2, a third input I-3, and a fourth input I-4, and three outputs, a first output O-1, a second output O-2, and a third output O-3.

Illustratively, the first input terminal I-1 of each clock delay unit is coupled to an output terminal of the controller 20 for receiving a clock control signal transmitted by the controller 20. In some examples, controller 20 may generate the clock control signal based on the phase modulation parameters and the number of clock delay units. Specifically, controller 20 may generate a clock control signal based on the phase modulation parameters and the M clock delay units, which may be an input signal to first input I-1 of each clock delay unit.

In some examples, controller 20 may generate corresponding M-bit clock control signals from M clock delay units and provide 1-bit clock control signal for each clock delay unit; that is, the first input terminal I-1 of the clock delay unit 1 to the first input terminal I-1 of the clock delay unit M may respectively input the clock control signal dly _ ctrl [1] of 1 bit to the clock control signal dly _ ctrl [ M ] of 1 bit.

The second input terminal I-2 of the first clock delay unit may be coupled to the clock source circuit 200, for receiving the clock input signal sent by the clock source circuit 200. A second input terminal I-2 of the clock delay unit I (which may also be referred to as the ith clock delay unit) may be coupled to a second output terminal O-2 of the clock delay unit I-1 (which may also be referred to as the ith clock delay unit) for receiving the signal output by the second output terminal O-2 of the clock delay unit I-1; wherein i is an integer greater than 1 and less than or equal to M.

The third input I-3 of the clock delay unit 1 is configured to receive a predetermined value, which may be a constant, for example, the predetermined value may be a constant 1. The third input terminal I-3 of the clock delay unit I is coupled to the third output terminal O-3 of the clock delay unit I-1 for receiving the signal outputted by the third output terminal O-3 of the clock delay unit I-1.

The fourth input terminal I-4 of the clock delay unit 1 is coupled to the first output terminal O-1 of the clock delay unit 2 for receiving the signal output by the first output terminal O-1 of the clock delay unit 2. The fourth input terminal I-4 of the clock delay unit I-1 is coupled to the first output terminal O-1 of the clock delay unit I for receiving the signal output by the first output terminal O-1 of the clock delay unit I-1.

It should be noted that, the fourth input terminal I-4 of the clock delay unit M may receive a preset value, and the preset value may be the same as the preset value received by the third input terminal I-3 of the clock delay unit 1, for example, all of the preset values are constant 1, or the preset value may be different from the preset value received by the third input terminal I-3 of the clock delay unit 1, which is not limited in the present invention. The second output terminal O-2 and the third output terminal O-3 of the clock delay unit M may output floating (floating), respectively, that is, the second output terminal O-2 and the third output terminal O-3 of the clock delay unit M may not output signals.

In some embodiments, each clock delay unit may include three nand gates and one inverter, as shown in fig. 3, which may be respectively: a first nand gate 111, a second nand gate 112, and a third nand gate 113; the inverter is a first inverter 114. The first nand gate 111, the second nand gate 112, and the third nand gate 112 may be two-input (i.e., having two input ends) nand gates, respectively.

Illustratively, two input ends of the first nand gate 111 in the clock delay unit are a second input end I-2 and a third input end I-3 of the clock delay unit, respectively, or two input ends of the first nand gate 111 in the clock delay unit are coupled to the second input end I-2 and the third input end I-3 of the clock delay unit, respectively, signals input to the second input end I-2 and the third input end I-3 are processed by the first nand gate 111 to obtain a first output signal, and the first output signal is output through an output end of the first nand gate 111.

In some examples, the output of the first nand gate 111 is the second output O-2 of the clock delay unit, or the output of the first nand gate 111 is coupled to the second output O-2 of the clock delay unit, that is, the second output O-2 of the clock delay unit may be used to output the first output signal. In addition, the output of the first nand gate 111 is further coupled to an input of the second nand gate 112, and an input of the second nand gate 112 can receive the signal (i.e. the first output signal) output by the output of the first nand gate 111.

The other input terminal of the second nand gate 112 is the first input terminal I-1 of the clock delay unit, or the other input terminal of the second nand gate 112 is coupled to the first input terminal I-1 of the clock delay unit for receiving the signal input by the first input terminal I-1 of the clock delay unit; the first output signal and the signal input by the first input terminal I-1 are processed by the second nand gate 112 to obtain a second output signal, and the second output signal is output through the output terminal of the second nand gate 112.

An input of the third nand gate 113 is coupled to the output of the second nand gate 112, and is configured to receive the signal (i.e., the second output signal) output by the output of the second nand gate 111; the other input end of the third nand gate 113 is the fourth input end I-4 of the clock delay unit, or the other input end of the third nand gate 113 is coupled to the fourth input end I-4 of the clock delay unit, and is configured to receive the signal input by the fourth input end I-4 of the clock delay unit; the second output signal and the signal input by the fourth input terminal I-4 of the clock delay unit are processed by the third nand gate 113 to obtain a third output signal, and the third output signal is output through the output terminal of the third nand gate 113. The output of the third nand gate 113 is the first output O-1 of the clock delay unit, or the output of the third nand gate 113 is coupled to the first output O-1 of the clock delay unit, that is, the first output O-1 of the clock delay unit can be used to output a third output signal.

Illustratively, the third output signal output by the third nand gate 113 in the clock delay unit 1 is a phase-modulated clock signal generated by the M clock delay units according to the clock control signal.

The input end of the first inverter 114 is coupled to the other input end of the second nand gate 112, or the input end of the first inverter 114 is coupled to the first input end I-1 of the clock delay unit, and is configured to receive the signal input by the first input end I-1 of the clock delay unit, perform inverse processing on the signal input by the first input end I-1 of the clock delay unit to obtain a fourth output signal, and output the fourth output signal through the output end of the first inverter 114. The output terminal of the first inverter 114 is the third output terminal O-3 of the clock delay unit, or the output terminal of the first inverter 114 is coupled to the third output terminal O-3 of the clock delay unit, that is, the third output terminal O-3 of the clock delay unit can be used to output a fourth output signal.

For example, referring to fig. 3, two input terminals of the first nand gate 111 in the clock delay unit 1 respectively receive the signal (e.g., clock input signal clock _ in) input from the second input terminal I-2 and the signal (e.g., preset value 1) input from the third input terminal I-3 in the clock delay unit 1, and perform a nand operation to obtain a first output signal. The first output signal is output via the second output O-2 of the clock delay unit 1 and is also used as an input signal to the second input I-2 of the clock delay unit 2. The second nand gate 112 in the clock delay unit 1 receives the first output signal and the signal (e.g., the clock control signal dly _ ctrl [1 ]) input from the first input terminal I-1 of the clock delay unit 1, and performs a nand operation to obtain a second output signal. The third nand gate 113 in the clock delay unit 1 receives the second output signal and the signal input by the fourth input terminal I-4 of the clock delay unit 1 (i.e. the signal output by the first output terminal O-1 of the Zhong Yanshi unit 2), and performs nand operation to obtain a third output signal, and the third output signal is output as a phase-modulated clock signal through the first output terminal O-1 of the clock delay unit 1. The first inverter 114 of the clock delay unit 1 receives the signal input by the first input terminal I-1 of the clock delay unit 1, and performs an inversion operation to obtain a fourth output signal, which is output through the third output terminal O-3 of the clock delay unit 1, and the fourth output signal is also used as the input signal of the third input terminal I-3 of the clock delay unit 2.

The first input terminal I-1 of the clock delay unit 2 receives an input signal (e.g., the clock control signal dly _ ctrl [2 ]), the second input terminal I-2 of the clock delay unit 2 receives the first output signal output from the second output terminal O-2 of the clock delay unit 1, the third input terminal I-3 of the clock delay unit 2 receives the fourth output signal output from the third output terminal O-3 of the clock delay unit 1, and the fourth input terminal I-4 of the clock delay unit 2 receives the output signal from the first output terminal O-1 of the clock delay unit 3. The first to fourth input terminals of the clock delay unit 3 to the clock delay unit M are similar to the first to fourth input terminals of the second clock delay unit 2, and are not described herein again.

In some embodiments, as shown in fig. 4, phase modulation circuit 10 may further include a selector 50 and a second inverter 60.

Wherein the selector 50 may comprise three input terminals and one output terminal. A first input terminal of the selector 50 is coupled to a first output terminal O-1 of the clock delay unit 1, and is configured to receive the phase-modulated clock signal output by the clock delay unit 1; a second input terminal of the selector 50 is coupled to an input terminal of the second inverter 60, and an input terminal of the second inverter 60 is coupled to the clock source circuit 200, for receiving a clock input signal sent by the clock source circuit 200, that is, the second input terminal of the selector 50 is used for receiving the clock input signal; a third input of the selector 50 is coupled to an output of the second inverter 60 for receiving a signal of the clock input signal inverted by the second inverter 60.

In some embodiments, the selector 50 is configured to: and outputting a clock output signal according to the selection signal, wherein the clock output signal is a phase-modulated clock signal, or a clock input signal after phase inversion. That is, the selection signal may select one of the phase-modulated clock signal, the clock input signal, and the inverted clock input signal as the clock output signal.

Therefore, the clock phase modulation circuit 100 provided in the embodiment of the present invention may select the output clock output signal in an actual situation, for example, when a chip needs to be connected to another peripheral chip, the phase modulation circuit 10 may select the phase-modulated clock signal as the clock output signal to output, so as to further improve the flexibility of the clock phase modulation circuit 100 and expand the application scenarios of the clock phase modulation circuit 100.

In summary, according to the clock phase modulation circuit 100 provided in some embodiments of the present invention, the clock phase modulation circuit 100 includes the detection circuit 30, and the detection circuit 30 is configured to detect a phase modulation parameter corresponding to a chip and send the phase modulation parameter to the controller 20; the controller 20 generates a clock control signal based on the received phase modulation parameter and transmits the clock control signal to the phase modulation circuit 10; the phase modulation circuit 10 phase-modulates a clock input signal according to the clock control signal, and outputs a clock output signal including a phase-modulated clock signal. Since the phase modulation parameters include operating parameters of a chip in which the clock phase modulation circuit 100 is located and/or environmental parameters of an environment in which the clock phase modulation circuit is located, the clock control signal generated according to the phase modulation parameters can phase modulate the clock input signal based on the operating scenario and the environmental condition of the chip. That is to say, the clock phase modulation circuit 100 can control the phase modulation circuit 10 to perform clock phase modulation according to different conditions (such as environment, temperature, voltage, etc.), so that not only the phase modulation accuracy of the clock phase modulation circuit 100 can be improved, but also the flexibility of the clock phase modulation circuit 100 is improved, so that the clock phase modulation circuit 100 can be suitable for different conditions, and the application scenario of the clock phase modulation circuit 100 is expanded.

Fig. 5 is a flowchart of a clock phase modulation method according to an embodiment of the present invention, which may be implemented by a clock phase modulation circuit, for example, the clock phase modulation circuit may be any one of the clock phase modulation circuits 100 in the embodiments described above, as shown in fig. 1, where the clock phase modulation circuit 100 includes a phase modulation circuit 10, a controller 20, and a detection circuit 30. As shown in fig. 5, the clock phasing method may include steps S510 to S520.

Step S510, obtaining phase modulation parameters corresponding to the chip, where the phase modulation parameters include working parameters of the chip and environmental parameters of an environment where the chip is located.

Step S520, according to the phase modulation parameter, a clock control signal for phase modulating the clock input signal is generated.

The clock phase modulation method can generate the clock control signal for phase modulation of the clock input signal by acquiring the phase modulation parameters corresponding to the chip, and the phase modulation parameters comprise working parameters and/or environmental parameters of the chip, so that the clock control signal can perform phase modulation on the clock input signal according to different conditions, the flexibility of clock phase modulation is improved, and the application scene of the clock phase modulation circuit 100 is expanded.

Embodiments of the present invention provide a computer-readable storage medium having stored thereon at least one executable instruction, which when run on a clock phasing circuit, causes the clock phasing circuit to perform a clock phasing method of any of the above-described method embodiments.

The algorithms or displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. In addition, embodiments of the present invention are not directed to any particular programming language.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. Similarly, in the above description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. Where the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. Except that at least some of such features and/or processes or elements are mutually exclusive.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names. The steps in the above embodiments should not be construed as limiting the order of execution unless specified otherwise.

Claims (10)

1. A clock phasing circuit, comprising:

a detection circuit configured to: detecting phase modulation parameters corresponding to the chip and outputting the phase modulation parameters; the phase modulation parameters comprise working parameters of the chip and/or environmental parameters of the environment where the chip is located;

a controller coupled to an output of the detection circuit and configured to: generating a clock control signal based on the received phase modulation parameters and outputting the clock control signal;

the phase modulation circuit coupled with an output of the controller and configured to: and according to the received clock control signal, phase modulation is carried out on a clock input signal, and a clock output signal is output.

2. The clock phase modulation circuit of claim 1, further comprising:

a configuration circuit coupled to an input of the controller and configured to: and compensating the phase modulation parameters.

3. The clock phase modulation circuit of claim 1 wherein the phase modulation circuit comprises M clock delay units coupled in sequence, M being an integer greater than 1;

the clock control signal is used for indicating the M clock delay units, and phase modulation is carried out on the clock input signal according to the phase modulation parameters to obtain a phase-modulated clock signal.

4. The clock phase modulation circuit of claim 3,

a first input end of a first clock delay unit of the M clock delay units is configured to receive the clock control signal, a second input end of the first clock delay unit is configured to receive the clock input signal, and a third input end of the first clock delay unit is configured to receive a preset value; the first output end of the first clock delay unit is used for outputting the phase-modulated clock signal;

a first input of an ith clock delay unit of the M clock delay units is configured to receive the clock control signal, a second input of the ith clock delay unit is coupled to a second output of the i-1 th clock delay unit, and a third input of the ith clock delay unit is coupled to a third output of the i-1 th clock delay unit; the first output end of the ith clock delay unit is coupled with the fourth input end of the (i-1) th clock delay unit; wherein i is an integer greater than 1 and less than or equal to M.

5. The clock phase modulation circuit according to claim 4, wherein the clock delay unit comprises: the first NAND gate, the second NAND gate, the third NAND gate and the first inverter;

two input ends of the first nand gate are respectively a second input end of the clock delay unit and a third input end of the clock delay unit, and an output end of the first nand gate is a second output end of the clock delay unit;

one input end of the second nand gate is coupled to the output end of the first nand gate, and the other input end of the second nand gate is the first input end of the clock delay unit;

one input end of the third nand gate is coupled to the output end of the second nand gate, another input end of the third nand gate is a fourth input end of the clock delay unit, and the output end of the third nand gate is the first output end of the clock delay unit;

the input end of the first inverter is coupled to the other input end of the second nand gate, and the output end of the first inverter is the third output end of the clock delay unit.

6. The clock phase modulation circuit according to claim 4 or 5, wherein the phase modulation circuit further comprises a second inverter and a selector;

a first input terminal of the selector is coupled to a first output terminal of the first clock delay unit, and is configured to receive the phase-modulated clock signal; a second input of the selector is coupled to an input of the second inverter, the input of the second inverter being configured to receive the clock input signal; a third input of the selector is coupled to an output of the second inverter;

the selector configured to: and outputting the clock output signal according to a selection signal, wherein the clock output signal is the phase-modulated clock signal, or the clock input signal after phase inversion.

7. The clock phase modulation circuit of claim 1 wherein the operating parameters comprise voltage parameters and/or current parameters; the environmental parameter includes a temperature parameter.

8. The clock phasing circuit of claim 1, wherein the controller is an eFuse controller.

9. A method for phase modulating a clock, the method comprising:

acquiring phase modulation parameters corresponding to the chip; the phase modulation parameters comprise working parameters of the chip and/or environmental parameters of the environment where the chip is located;

and generating a clock control signal for phase modulation of a clock input signal according to the phase modulation parameter.

10. A computer-readable storage medium having stored therein at least one executable instruction that, when run on a clock phasing circuit, causes the clock phasing circuit to perform operations of the clock phasing method of claim 9.

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