CN115776281A - Power amplifier architecture and circuit board - Google Patents

Power amplifier architecture and circuit board Download PDF

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Publication number
CN115776281A
CN115776281A CN202111040170.9A CN202111040170A CN115776281A CN 115776281 A CN115776281 A CN 115776281A CN 202111040170 A CN202111040170 A CN 202111040170A CN 115776281 A CN115776281 A CN 115776281A
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China
Prior art keywords
power
power amplifier
input
divider
power divider
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CN202111040170.9A
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Chinese (zh)
Inventor
丁冲
秦天银
魏伟伟
张晓毅
余敏德
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ZTE Corp
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ZTE Corp
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Priority to CN202111040170.9A priority Critical patent/CN115776281A/en
Priority to PCT/CN2022/117175 priority patent/WO2023030530A1/en
Publication of CN115776281A publication Critical patent/CN115776281A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The embodiment of the invention relates to the technical field of amplifier circuits, in particular to a power amplifier framework and a circuit board. The power amplifier architecture comprises: the first transmission path comprises a control power amplifier and a first power divider, and the output end of the control power amplifier is connected with the input end of the first power divider; the N second transmission paths include a balanced power amplifier, a second power divider, and a third power divider, where a third input terminal of the third power divider in the N second transmission paths is correspondingly connected to N output terminals of the first power divider, respectively; the power amplifier architecture further includes a combiner with N input terminals, a fourth power divider with N output terminals, and a fifth power divider, where an input terminal of the fifth power divider is used as an input terminal of the power amplifier architecture, and an output terminal of the combiner is used as an output terminal of the power amplifier architecture. The power amplifier architecture provided by the embodiment of the invention gives consideration to high power and large bandwidth.

Description

Power amplifier architecture and circuit board
Technical Field
The embodiment of the application relates to the field of amplifier circuits, in particular to a power amplifier architecture and a circuit board.
Background
As 5G business continues to advance, plus the individual frequency bands of 3G and 4G communications, there are more and more wireless communication bands available to each communications carrier. In order to meet the coverage requirement of a single cell, the number of base stations of a single site is increased more and more, and the operation cost is continuously increased. In order to reduce the operation cost, simplify the deployment process and reduce the deployment difficulty, operators actively promote the co-construction and sharing of the wireless base station, so that the broadband power amplifier architecture in the base station receives more and more attention. To ensure the coverage of the base station, it is generally necessary to ensure that the transmission power is about 2W per 1MHz of the communication spectrum. Thus, the broadband requirement is accompanied by a high power requirement.
At present, a power amplifier module in a base station generally adopts a Doherty power amplifier architecture mode, and generally adopts a Doherty combining mode in order to meet the requirement of high transmitting power, but the introduction of the Doherty combining structure can limit the working bandwidth to a certain extent.
Disclosure of Invention
The present disclosure provides a power amplifier structure and a circuit board. Therefore, the broadband power is effectively improved on the basis of ensuring certain bandwidth, and the broadband is widely applied.
In order to achieve the above object, an embodiment of the present application provides a single-input power amplifier architecture, including a first transmission path, where the first transmission path includes and controls a power amplifier and a first power divider, and an output end of the control power amplifier is connected to an input end of the first power divider; n second transmission paths, wherein each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; third input ends of the third power dividers in the N second transmission paths are respectively and correspondingly connected with N output ends of the first power divider; n is an integer greater than or equal to 1, and has a combiner with N input ends, where the N input ends of the combiner are respectively connected to output ends of the third power dividers in the N second transmission paths; a fourth power divider having N output terminals, where the N output terminals of the fourth power divider are respectively and correspondingly connected to the input terminals of the second power dividers in the N second transmission paths; a first output end of the fifth power divider is connected to the input end of the control power amplifier, and a second output end of the fifth power divider is connected to the input end of the fourth power divider; the power amplifier architecture has an input end, and an input end of the fifth power divider is used as an input end of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
In order to achieve the above object, an embodiment of the present application further provides a dual-input power amplifier architecture, which includes a first transmission path, where the first transmission path includes and controls a power amplifier and a first power divider, and an output end of the control power amplifier is connected to an input end of the first power divider; n second transmission paths, wherein each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; third input ends of the third power dividers in the N second transmission paths are respectively and correspondingly connected with N output ends of the first power divider; n is a combiner having N input ends, where N is an integer greater than or equal to 1, and the N input ends of the combiner are respectively connected to output ends of the third power dividers in the N second transmission paths; a fourth power divider having N output terminals, where the N output terminals of the fourth power divider are respectively and correspondingly connected to the input terminals of the second power dividers in the N second transmission paths; a first output end of the fifth power divider is connected to the input end of the control power amplifier, and a second output end of the fifth power divider is connected to the input end of the fourth power divider; wherein the power amplifier architecture has two inputs, an input of the control power amplifier is one of the two inputs of the power amplifier architecture, and an input of the fourth power divider is the other of the two inputs of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
In order to achieve the above object, an embodiment of the present application further provides a three-input power amplifier architecture, including a first transmission path, where the first transmission path includes and controls a power amplifier and a first power divider, and an output end of the control power amplifier is connected to an input end of the first power divider; n second transmission paths, wherein each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; third input ends of the third power dividers in the N second transmission paths are respectively and correspondingly connected with N output ends of the first power divider; n is an integer greater than or equal to 1, and has a combiner with N input ends, where the N input ends of the combiner are respectively connected to output ends of the third power dividers in the N second transmission paths; a fourth power divider having N output terminals, where the N output terminals of the fourth power divider are respectively and correspondingly connected to the input terminals of the second power dividers in the N second transmission paths; a first output end of the fifth power divider is connected to the input end of the control power amplifier, and a second output end of the fifth power divider is connected to the input end of the fourth power divider; wherein the power amplifier architecture has N +1 input terminals, an input terminal of the control power amplifier serves as one of the N +1 input terminals of the power amplifier architecture, and input terminals of the N second power dividers serve as N input terminals of the N +1 input terminals of the power amplifier architecture, respectively; the output end of the combiner is the output end of the power amplifier architecture.
To achieve the above object, an embodiment of the present application further provides a circuit board, including a power amplifier architecture; the circuit board is applied to the power amplifier architecture of any one of the above.
According to the power amplifier architecture provided by the application, the power divider in the first transmission path and the power divider in the second transmission path decouple the first transmission path and the second transmission path better, so that the impedance of the control power amplifier in the first transmission path is basically not dragged by the balanced power amplifier in the second transmission path, the control power amplifier can be well matched with an impedance matching network in a circuit all the time no matter how the input signal changes, and the limitation to the working bandwidth caused by poor matching of the control power amplifier and the impedance matching network is avoided; and one path of first transmission path can control multiple paths of second transmission paths, so that the high power requirement can be met.
Drawings
Fig. 1 is a diagram of a power amplifier architecture according to one embodiment of the invention;
figure 2 is a graph of CPA output port and BPA output port currents in a power amplifier architecture according to one embodiment of the invention;
figure 3 is a graph of CPA output port and BPA output port voltages in a power amplifier architecture according to one embodiment of the invention;
figure 4 is a CPA and BPA impedance pulling diagram of a power amplifier architecture according to one embodiment of the invention;
FIG. 5 is a CPA and BPA power diagram of a power amplifier architecture according to one embodiment of the invention;
figure 6 is a CPA and BPA efficiency graph of a power amplifier architecture according to one embodiment of the invention;
fig. 7 is an architecture diagram of a dual input power amplifier according to another embodiment of the present invention;
fig. 8 is an architecture diagram of a three input power amplifier in accordance with another embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to without contradiction.
One embodiment of the invention relates to a power amplifier architecture, which is mainly applied to a high-power broadband RRU base station. The power amplifier architecture includes: the first transmission path comprises a control power amplifier and a first power divider, and the output end of the control power amplifier is connected with the input end of the first power divider; each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; a third input end of a third power divider in the N second transmission paths is correspondingly connected with N output ends of the first power divider respectively; wherein N is an integer greater than or equal to 1; the combiner is provided with N input ends, and the N input ends of the combiner are respectively and correspondingly connected with the output ends of the third power dividers in the N second transmission paths; the fourth power divider is provided with N output ends, and the N output ends of the fourth power divider are respectively and correspondingly connected with the input end of the second power divider in the N second transmission paths; a first output end of the fifth power divider is connected with the input end of the control power amplifier, and a second output end of the fifth power divider is connected with the input end of the fourth power divider; the power amplifier architecture is provided with an input end, and the input end of the fifth power divider is used as the input end of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
In one example, N may be 2, see fig. 1. The first transmission path is a branch where a Control Power Amplifier (CPA) is located, and may be referred to as a control path, and the control power amplifier may be an AB-class power amplifier; the second transmission path is a branch where a Balanced Power Amplifier (BPA) is located, and may be referred to as a balanced path, and the balanced pa may be a class C pa. The power divider may be a Quadrature Hybrid Bridge Combiner (QHBC) or another power divider, the first power divider may be a QHBC1, the second power divider may be a QHBC2, the third power divider may be a QHBC3, the fourth power divider may be a QHBC4, the fifth power divider may be a QHBC5, and the combiner may be a QHBC6, where an input end of the QHBC5 is an input end of a power amplifier architecture and an output end of the combiner QHBC6 is an output end of the power amplifier architecture.
The power amplifier architecture comprises a control circuit and two groups of balance circuits, signals are input to the QHBC5 through the radio frequency input port Pin, the QHBC5 divides the signals into two circuits, one circuit is fed into the control circuit, and the other circuit is fed into the balance circuits.
The control path specifically includes: CPA, QHBC1, a limiter (Ampli-limiter), a phase adjuster which may be a phase compensation line (Offset line) for modulating the phase of the input signal, and a Load resistor Load, wherein the amplitude-limiter modulates the amplitude of the input signal. The input end and the Offset line of the CPA are connected with the Ampli-limiter, and the output end of the CPA is connected with the input end of the QHBC 1. The signal is output from a first output end of the QHBC5, is subjected to phase and amplitude modulation, amplified after being subjected to CPA working in an AB type state and output through the QHBC 1.
The first group of balanced paths specifically comprises 2 BPA, and a second power divider QHBC2-1; a third power divider QHBC3-1; the second group of balanced paths specifically comprise 2 BPA, a second power divider QHBC2-2 and a third power divider QHBC3-2; the Load resistance Load is several. The signal is output to the QHBC4 from the second output end of the QHBC5, the QHBC4 divides the signal into two paths, one path of the signal is input to the QHBC2-1, the signal is distributed by the QHBC2-1 and then enters the balanced power amplifier, and the signal is output by the QHBC3-1; the other path is input into a QHBC2-2, and the signal enters another group of balanced power amplifiers after being distributed by the QHBC2-2 and then is output by the QHBC3-2.
It should be noted that the first output terminal of the QHBC1 of the control path is connected to the third input terminal of the QHBC3-2 of the second group of balanced paths, and the second output terminal of the QHBC1 is connected to the third input terminal of the QHBC3-1 of the first group of balanced paths, so that the control path CPA can control the two groups of balanced paths BPA, and finally output from the combining QHBC 6.
Optionally, the first transmission path may further include a phase adjuster and/or a limiter; the phase regulator is connected with the first output end of the fifth power divider and the input end of the control power amplifier; the limiter is connected between the first output terminal of the fifth power divider and the input terminal of the control power amplifier, that is, a phase adjuster and/or a limiter may be arranged between the output terminal of the control circuit QHBC5 and the input terminal of the CPA in any permutation and combination, the phase adjuster is used for modulating the phase of the signal, and the limiter is used for controlling the amplitude of the signal.
Optionally, the first transmission path includes a phase compensation line and a limiter, the phase compensation line is connected between the first output terminal of the fifth power divider and the input terminal of the limiter, and the output terminal of the limiter is connected to the input terminal of the control power amplifier, that is, the phase compensation line is one of the phase adjusters for adjusting the phase, and is used together with the limiter between the output terminal of the control circuit QHBC5 and the input terminal of the CPA.
Optionally, the second output terminal of the fifth power divider is connected to the input terminal of the fourth power divider through the phase adjuster. That is, the phase adjuster can be disposed between the second output terminal of QHBC5 and the input terminal of QHBC4 to adjust the phase, and the same effect can be achieved.
Optionally, each output end of the fourth power divider is connected to the input end of the second power divider in the corresponding second transmission path through the phase adjuster. That is, the phase adjusters are placed between the output terminal of QHBC4 and the input terminal of QHBC2-1 in one set, and between the other output terminal of QHBC4 and the input terminal of QHBC2-2 in one set, and adjust the phases of the two sets of BPA, respectively, to achieve the same effect.
Optionally, the phase adjuster may be further disposed between the four output ends of the second power divider and the BPA input end, that is, one set is disposed between the two output ends of the QHBC2-1 and the BPA corresponding thereto, and the other set is disposed between the two output ends of the QHBC2-2 and the BPA corresponding thereto, so as to adjust the phases of the four BPA, thereby achieving the same effect.
According to the power amplifier architecture provided by the application, the power dividers in the control circuit and the balance circuit better decouple the two power amplifiers, so that the impedance of the control power amplifier in the control circuit is basically not pulled by the balance power amplifier in the balance circuit, the control power amplifier can be well matched with an impedance matching network in the circuit all the time no matter how the input signal changes, and the limitation to the working bandwidth caused by poor matching of the control power amplifier and the impedance matching network is avoided; and one control circuit can control a plurality of balancing circuits, and the control power amplifier in the control circuit forms impedance traction to the balancing power amplifier in the balancing circuit, so that the high power requirement can be met.
In the above power amplifier architecture, in a specific implementation, as shown in fig. 1, a signal is divided into two paths by the QHBC5 through the radio frequency input port Pin. When the input signal is a small signal, the control circuit starts to work, the CPA voltage current is in an AB type state, and the signal is amplified after passing through the CPA working in the AB type state and is output after passing through the QHBC 1. Meanwhile, under the condition of small signals, the voltage and the current of the two groups of balanced power amplifiers are in a C-type state, the impedance of the two groups of balanced power amplifiers is infinite, and the four BPA are in a turn-off state, so that the two groups of balanced circuits equivalently do not work.
When the input signal is continuously increased to a power state, the control circuit and the two groups of balance circuits start to work together. Along with the further increase of the input power, the current of the control circuit CPA reaches the maximum value, the CPA enters a saturation state, and the working efficiency is reduced. In order to avoid the CPA input power from further increasing to enter an oversaturated state, the amplitude limiter starts to work to limit the amplitude of the input CPA signal, so that the signal input to the control circuit power amplifier is ensured to be lower than a certain preset value, the CPA is prevented from working in the oversaturated state, and the reliability and the stability of the CPA are improved. In order to avoid the further increase of the CPA input power and enter the oversaturated state, the amplitude limiter starts to work, the amplitude of the input CPA signal is limited, the condition that the signal input to the control circuit power amplifier is lower than a certain preset value is ensured, the CPA is prevented from working in the oversaturated state, and therefore the reliability of the CPA is improved. In a high-power state, two groups of balanced power amplifiers start to work, namely 4 BPA are turned on. The BPA signal is divided into two paths by QHBC4, then respectively fed into two groups of balanced power amplifiers, and is output to two groups of power dividers QHBC3-1 and QHBC3-2 through BPA. Two output ends of the QHBC1 of the control path respectively act on input ends of two groups of balance paths QHBC3-1 and QHBC3-2, and the slope of the phase of the S parameter in the working frequency band is changed by changing the length of the offset line of the control path, so that the load traction of 4 BPA in the two groups of balance paths is realized.
In an example, if an 8dB back-off broadband high-power amplifier is implemented, a ratio of currents required to be output by a CPA and BPA power amplifier tube is calculated to be 2.06, and an ideal current source model analysis is performed on each port of a power divider connected to any one group of BPA output ends on a balanced path, for example, the power divider connected to an output port is QHBC3-1, so that a current diagram as shown in fig. 2 is obtained, a horizontal axis represents voltage, a horizontal axis represents a value of the voltage after the voltage value is normalized, and a vertical axis represents current. As shown in fig. 2, before the normalized voltage is 0.4, the CPA current is gradually increased, and the control circuit starts to work; the BPA current is 0, the impedance is infinite, and four BPAs are in the off state. The normalized voltage is 0.4,cpa current to maximum 0.6,4 BPA switches on and the two sets of balanced power amplifiers start to operate. As shown in fig. 3, voltages at the CPA output port and the BPA output port in the power amplifier architecture are gradually increased before the normalized voltage reaches 0.4, and after the normalized voltage reaches 0.4, the CPA voltage is stable and unchanged, and the BPA voltage is gradually increased. As shown in fig. 4, after the CPA current reaches 0.6, the control circuit changes the length of offset line, so as to change the slope of the phase of the S parameter in the operating frequency band, thereby implementing load traction on 4 BPAs. At the lower of the broadband high-power work of 8dB backspacing, the impedance value of the CPA is constant at 50 ohms, the CPA impedance draws the BPA impedance, and the impedance of the BPA gradually decreases along with the increase of the normalized voltage. After the signals are acted by the power amplifiers in the control circuit and the balance circuit and then output in a combined way, the power diagrams of the CPA and the BPA are shown in figure 5, and after the CPA forms impedance traction on the BPA, the output power is continuously improved. The graph of efficiency of CPA and BPA is shown in FIG. 6, when the normalized voltage reaches 0.4, the efficiency reaches nearly 80% at most, CPA and BPA work simultaneously, and CPA forms impedance traction to BPA, so that the efficiency rises back to nearly 80% again. According to the power amplifier, under the high-power state, the power amplifier is controlled in the control circuit to form impedance traction on the balance power amplifier in the balance circuit, and the high-power requirement is met on the basis of ensuring the bandwidth.
Another embodiment of the present invention relates to a power tapping and amplifying architecture, and the following description specifically describes implementation details by taking a dual-input power amplifier architecture as an example, and the following description is only provided for facilitating understanding of the implementation details and is not necessary to implement the present invention, and the dual-input power amplifier architecture includes: the first transmission path comprises a control power amplifier and a first power divider, and the output end of the control power amplifier is connected with the input end of the first power divider; each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; a third input end of a third power divider in the N second transmission paths is correspondingly connected with N output ends of the first power divider respectively; wherein N is an integer greater than or equal to 1; the combiner is provided with N input ends, and the N input ends of the combiner are respectively and correspondingly connected with the output ends of the third power dividers in the N second transmission paths; the fourth power divider is provided with N output ends, and the N output ends of the fourth power divider are respectively and correspondingly connected with the input end of the second power divider in the N second transmission paths; the power amplifier architecture is provided with two input ends, the input end of the power amplifier is controlled to be one of the two input ends of the power amplifier architecture, and the input end of the fourth power divider is used as the other one of the two input ends of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
In an example, N may be 2, referring to fig. 7, the power amplifier architecture includes a control circuit and two groups of balance circuits, the control circuit controls the power amplifier to control the balance circuits to balance the power amplifier, and similar to the power amplifier architecture of the previous embodiment, which is not repeated here for avoiding repetition. Different from the first embodiment of the present application, the power amplifier architecture of the present embodiment has two input ends, wherein a first part of signals is fed into the control circuit through a radio frequency input port Pin1, amplified after passing through CPA operating in class AB state, and output through QHBC 1; the second part of signals are fed into a balance path through another radio frequency input port Pin2, the QHBC4 divides the signals into two paths, one path acts on QHBC2-1, BPA and QHBC3-1, and the other path acts on QHBC2-2, BPA and QHBC3-2.
The dual-input power amplifier structure removes a phase regulator and an amplitude limiter in a control circuit in the control circuit, the functions of the two modules can be realized by carrying out amplitude modulation and phase modulation in a digital domain, and the power amplifier can be controlled more accurately. After double input is adopted, one power divider with an input end omitted, namely QHBC5, is omitted, the architecture is simplified, the circuit cost is reduced, and meanwhile, compared with a single-input power amplifier architecture, the power divider is reduced, the gain of the architecture is improved, and therefore the architecture performance is further improved.
In another embodiment of the present invention, the power amplifier may also be a three-input power amplifier, which specifically includes: the first transmission path comprises a control power amplifier and a first power divider, and the output end of the control power amplifier is connected with the input end of the first power divider; each second transmission path comprises two balanced power amplifiers, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; a third input end of a third power divider in the N second transmission paths is correspondingly connected with N output ends of the first power divider respectively; wherein N is an integer greater than or equal to 1; the combiner is provided with N input ends, and the N input ends of the combiner are respectively and correspondingly connected with the output ends of the third power dividers in the N second transmission paths; the power amplifier architecture is provided with N +1 input ends, the input end of the power amplifier is controlled to be used as one input end of the N +1 input ends of the power amplifier architecture, and the input ends of the N second power dividers are respectively used as N input ends of the N +1 input ends of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
Similar to the power amplifier structure of the previous example, N may be 2, and referring to fig. 8, the power amplifier structure includes a control circuit and two balancing circuits, the control circuit controls the power amplifier to control the balancing circuits to balance the power amplifier, and the structural relationship between the control circuit and the balancing circuits is not repeated here for avoiding repetition. Different from the above example, the power amplifier architecture of the present embodiment has three input ends, wherein, a signal is fed into the control circuit through the first rf input port Pin1, amplified after passing through the CPA working in the AB state, and output through the QHBC 1; the signal is fed into a group of balance circuits through a second radio frequency input port Pin2 to act on QHBC2-1, BPA and QHBC3-1, and the signal is fed into another group of balance circuits through a third radio frequency input port Pin3 to act on QHBC2-2, BPA and QHBC3-2. And the control path and the balance path signals are finally output from the combiner QHBC 6.
The three-input power amplifier simplifies the architecture layout and reduces the circuit cost. And meanwhile, two groups of power dividers are further omitted, namely the QHBC4 and the QHBC5 are omitted, and compared with a single-input power amplifier and a double-input power amplifier, the three-input power amplifier structure further improves the gain of the structure and the performance of the structure.
Another embodiment of the invention relates to a circuit board comprising a power amplifier architecture; the power amplifier architecture includes a single input power amplifier architecture, a dual input power amplifier architecture, and a three input power amplifier architecture.
It will be appreciated that this embodiment may be implemented in conjunction with the method embodiments described above. The related technical details and technical effects mentioned in the above embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of practicing the invention, and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention in practice.

Claims (14)

1. A power amplifier architecture, comprising:
the power divider comprises a first transmission path, a second transmission path and a third transmission path, wherein the first transmission path comprises a control power amplifier and a first power divider, and an output end of the control power amplifier is connected to an input end of the first power divider;
n second transmission paths, wherein each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; third input ends of the third power dividers in the N second transmission paths are respectively and correspondingly connected to N output ends of the first power divider; wherein N is an integer greater than or equal to 1;
the combiner is provided with N input ends, and the N input ends of the combiner are respectively and correspondingly connected with the output ends of the third power dividers in the N second transmission paths;
a fourth power divider having N output terminals, where the N output terminals of the fourth power divider are respectively and correspondingly connected to the input terminals of the second power dividers in the N second transmission paths;
a first output end of the fifth power divider is connected to the input end of the control power amplifier, and a second output end of the fifth power divider is connected to the input end of the fourth power divider;
wherein the power amplifier architecture has an input terminal, and an input terminal of the fifth power divider is used as an input terminal of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
2. The power amplifier architecture of claim 1, wherein the first transmission path further comprises: a phase adjuster and/or limiter;
the phase adjuster is connected to the first output end of the fifth power divider and the input end of the control power amplifier;
the limiter is connected between the first output end of the fifth power divider and the input end of the control power amplifier.
3. The power amplifier architecture of claim 2, wherein the first transmission path comprises a phase compensation line and a limiter;
the phase compensation line is connected between the first output end of the fifth power divider and the input end of the amplitude limiter, and the output end of the amplitude limiter is connected to the input end of the control power amplifier.
4. The power amplifier architecture of claim 1, wherein the control power amplifier is a class AB power amplifier and the balanced power amplifier is a class C power amplifier.
5. The power amplifier architecture of claim 1, wherein the second output of the fifth power divider is connected to the input of the fourth power divider through a phase adjuster.
6. The power amplifier architecture of claim 1, wherein each output of the fourth power divider is connected to an input of the second power divider in the corresponding second transmission path through the phase adjuster.
7. The power amplifier architecture of any of claims 1-6, wherein the value of N is 2.
8. A power amplifier architecture, comprising:
the power divider comprises a first transmission path, a second transmission path and a third transmission path, wherein the first transmission path comprises a control power amplifier and a first power divider, and an output end of the control power amplifier is connected to an input end of the first power divider;
n second transmission paths, wherein each second transmission path comprises a balanced power amplifier, a second power divider and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; third input ends of the third power dividers in the N second transmission paths are respectively and correspondingly connected to N output ends of the first power divider; wherein N is an integer greater than or equal to 1;
the combiner is provided with N input ends, and the N input ends of the combiner are respectively and correspondingly connected with the output ends of the third power dividers in the N second transmission paths;
a fourth power divider having N output terminals, where the N output terminals of the fourth power divider are respectively connected to the input terminals of the second power dividers in the N second transmission paths;
wherein the power amplifier architecture has two inputs, an input of the control power amplifier is one of the two inputs of the power amplifier architecture, and an input of the fourth power divider is the other of the two inputs of the power amplifier architecture; the output end of the combiner is the output end of the power amplifier architecture.
9. The power amplifier architecture of claim 8, wherein the control power amplifier is a class AB power amplifier and the control power amplifier is a balanced power amplifier and a class C power amplifier.
10. The power amplifier architecture of claim 8 or 9, wherein the value of N is 2.
11. A power amplifier architecture, comprising:
the power divider comprises a first transmission path, a second transmission path and a third transmission path, wherein the first transmission path comprises a control power amplifier and a first power divider, and an output end of the control power amplifier is connected to an input end of the first power divider;
each of the N second transmission paths includes two balanced power amplifiers, a second power divider, and a third power divider; the input ends of the two balanced power amplifiers are respectively and correspondingly connected with the two output ends of the second power divider, and the output ends of the two balanced power amplifiers are respectively and correspondingly connected with the first input end and the second input end of the third power divider; third input ends of the third power dividers in the N second transmission paths are respectively and correspondingly connected with N output ends of the first power divider; wherein N is an integer greater than or equal to 1;
the combiner is provided with N input ends, and the N input ends of the combiner are respectively and correspondingly connected with the output ends of the third power dividers in the N second transmission paths;
wherein the power amplifier architecture has N +1 input terminals, an input terminal of the control power amplifier serves as one of the N +1 input terminals of the power amplifier architecture, and input terminals of the N second power dividers serve as N input terminals of the N +1 input terminals of the power amplifier architecture, respectively; the output end of the combiner is the output end of the power amplifier architecture.
12. The power amplifier architecture of claim 11, wherein the control power amplifier is a class AB power amplifier and the control power amplifier is a balanced power amplifier is a class C power amplifier.
13. The power amplifier architecture of claim 11 or 12, wherein the value of N is 2.
14. A circuit board, comprising: a power amplifier architecture; the power amplifier architecture is the power amplifier architecture of any one of claims 1 to 7, or the power amplifier architecture of any one of claims 8 to 10, or the power amplifier architecture of any one of claims 11 to 13.
CN202111040170.9A 2021-09-06 2021-09-06 Power amplifier architecture and circuit board Pending CN115776281A (en)

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