CN115774975A

CN115774975A - LOD effect model optimization method and integrated circuit manufacturing method

Info

Publication number: CN115774975A
Application number: CN202310092683.7A
Authority: CN
Inventors: 刘晓兰; 江丰顺
Original assignee: Guangzhou Yuexin Semiconductor Technology Co Ltd
Current assignee: Yuexin Semiconductor Technology Co ltd
Priority date: 2023-02-10
Filing date: 2023-02-10
Publication date: 2023-03-10
Anticipated expiration: 2043-02-10
Also published as: CN115774975B

Abstract

The application relates to an optimization method of an LOD effect model and a manufacturing method of an integrated circuit. The method comprises the steps of constructing a structure of a transistor device to be tested; the transistor device under test comprises a first transistor device; obtaining a first model parameter of a basic current-voltage model based on the first transistor device; adjusting the first model parameter based on the layout parameter of the first transistor device to obtain a second model parameter; and applying the second model parameter to an LOD effect model to obtain an optimized LOD effect model. By the method, two transistor devices with the same layout parameter can be eliminated, and the problem that the measured data and the simulation data of the LOD model cannot be completely fitted due to the difference of the test data extracted by the basic current-voltage model and the LOD effect model is solved, so that the influence of the LOD effect on the transistor devices is more accurately extracted.

Description

Optimization method of LOD effect model and manufacturing method of integrated circuit

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to an optimization method for an LOD effect model and a manufacturing method for an integrated circuit.

Background

The LOD (Length of Diffusion) is the effect of the variation of the electrical characteristics of the transistor device caused by the variation of the spacing between the gate and the Shallow Trench Isolation (STI) in the direction of the extension of the channel, and when two transistor devices have the same gate Length and width, the effect of the difference of the current caused by the difference of the lengths of the Diffusion regions is the LOD stress effect. The LOD stress effect mainly affects the saturated source-drain current (Idsat) and threshold voltage (Vth) of the device, and can be described by the following two Layout (Layout) parameters: SA and SB, where SA is the transistor device gate to source (Active Area) edge spacing and SB is the transistor device gate to drain (Active Area) edge spacing.

In order to test the influence Of STI stress on a transistor device, it is common in the semiconductor industry to establish a basic current-voltage model and an LOD (Length Of Diffusion) effect model Of the transistor device for simulation tests. And the LOD effect model simulates the designed transistor device according to the LOD effect test data on the basis of the extracted basic current-voltage model to obtain a simulation result.

In the prior art, the layout for extracting the basic current-voltage model and the layout for extracting the LOD effect model are separately designed, and when the two are used for testing the electrical performance of the transistor device, because the position, environment, test condition and test bench of a test point (testkey) are not consistent, the difference exists between the measured data of two transistor devices with completely the same layout parameters in the basic current-voltage model and the LOD effect model, so that the problem that the simulation data and the measured data of the LOD effect model cannot be completely fitted occurs.

Disclosure of Invention

Therefore, it is necessary to provide an optimization method of an LOD effect model and a manufacturing method of an integrated circuit for solving the problem that simulation data and actual measurement data of the LOD effect model cannot be completely fitted due to the difference between actual measurement data of two transistor devices with completely the same layout parameters in the basic current-voltage model and the LOD effect model, which is caused by the inconsistency of the positions, environments, test conditions and test tables of test points in the prior art.

In a first aspect, the present application provides a method for optimizing an LOD effect model, the method comprising:

constructing a structure of a transistor device to be tested; the transistor device to be tested comprises a first transistor device;

obtaining a first model parameter of a basic current-voltage model based on the first transistor device;

adjusting the first model parameter based on the layout parameter of the first transistor device to obtain a second model parameter;

and applying the second model parameter to the LOD effect model to obtain the optimized LOD effect model.

In one embodiment, the number of the first transistor devices is multiple, the size of each first transistor device is variable, and the distance SA from the grid electrode to the edge of the active region is a constant value;

wherein the dimensions include a channel length and a channel width.

In one embodiment, the obtaining the first model parameter of the basic current-voltage model based on the first transistor device includes:

and simulating each first transistor device by adopting the basic current-voltage model, and taking a simulation result as a first model parameter of the basic current-voltage model.

In one embodiment, the adjusting the first model parameter based on the layout parameter of the first transistor device to obtain the second model parameter includes:

establishing a proportional function of the first model parameter and the layout parameter, and combining the proportional functions to obtain a distance function model; wherein the layout parameters include a size and SA of the first transistor device, and the first model parameters include a threshold voltage, an effective mobility, and a saturation velocity;

adding the distance function model into a formula of the basic current-voltage model;

and simulating the first transistor device by adopting a formula added into the distance function model, and taking a simulation result as a second model parameter of the basic current-voltage model.

In one embodiment, the transistor device under test includes a plurality of second transistor devices, the size of each of the second transistor devices is a fixed value, and SA is a variable.

In one embodiment, the applying the second model parameters to the LOD effect model comprises:

when the SA of the second transistor device is changed to be equal to the SA of the first transistor device, second model parameters corresponding to the size of the first transistor device being equal to the size of the second transistor device are taken and applied to the LOD effect model.

In one embodiment, the method for optimizing the LOD effect model further includes:

simulating the second transistor device by using the optimized LOD effect model to obtain a simulation curve;

and adjusting the model parameters of the distance function model and the optimized LOD effect model according to the simulation curve and a pre-stored reference relation curve to obtain a final LOD effect model.

In one embodiment, the reference relation curve is obtained by measuring electrical performance data of each second transistor device in advance;

the reference relationship curve includes: the SA-Vth relation curve and the SA-Idsat relation curve;

wherein Vth is a threshold voltage; idsat is the saturated drain-source current.

In one embodiment, the adjusting the model parameters of the optimized LOD effect model according to the simulation curve and a pre-stored reference relationship curve to obtain a final LOD effect model includes:

comparing the simulated curve with the reference relationship curve;

and adjusting the model parameters of the distance function model and the optimized LOD effect model according to the comparison result until the simulation curve is matched with the reference relation curve to obtain a final LOD effect model.

In a second aspect, the present application further provides a method of manufacturing an integrated circuit, the method of manufacturing optimizing an LOD effect model using the method of any one of the first aspects, and manufacturing an integrated circuit using a simulation structure of the optimized LOD effect model.

The optimization method of the LOD effect model and the manufacturing method of the integrated circuit have at least the following advantages:

according to the method and the device, the first model parameter extracted from the basic current-voltage model is adjusted to be the second model parameter based on layout parameter change, and the second simulation parameter is applied to the LOD effect model to obtain the optimized LOD effect model. The optimized LOD effect model is adopted to simulate the transistor device to be tested, two transistor devices with the same layout parameters can be eliminated, and the problem that the measured data and the simulation data of the LOD model cannot be completely fitted due to the fact that the difference exists between the test data extracted by the basic current-voltage model and the test data extracted by the LOD effect model is solved, so that the influence of the LOD effect on the transistor devices is more accurately extracted.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention.

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic flow chart diagram illustrating a method for optimizing a LOD effect model in one embodiment;

FIG. 2 is a physical layout of a typical transistor device in one embodiment;

FIG. 3 is a schematic flow chart diagram illustrating a method for optimizing the LOD effect model in another embodiment;

FIG. 4 is a schematic flow chart illustrating the process of obtaining second model parameters in one embodiment;

FIG. 5 is a schematic diagram of a relationship between a simulation curve and measured data in one embodiment;

FIG. 6 is a schematic diagram showing the relationship between simulation curves and measured data in another embodiment;

FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

Some exemplary embodiments of the invention have been described for illustrative purposes, and it is to be understood that the invention may be practiced otherwise than as specifically described.

Referring to fig. 1, in one possible embodiment, the present application provides a method for optimizing an LOD effect model, including:

step S102, a structure of a transistor device to be tested is established, wherein the transistor device to be tested comprises a first transistor device.

Specifically, modeling and simulation of an integrated circuit have become indispensable means in the process of designing and manufacturing the integrated circuit, and after a designer constructs a structure of a transistor device, the designer can simulate the constructed transistor device by using a basic current-voltage model to obtain simulation data of the transistor device, and generate characteristic curves such as an IDVD curve and an IDVG curve based on the simulation data; or simulating the constructed transistor device by adopting an LOD effect model to obtain simulation data of the transistor device, and generating a stress-related curve based on the simulation data, such as an SA-Vth relationship curve and an SA-Idsat relationship curve, wherein Vth is threshold voltage; idsat is the saturated drain-source current. It should be understood that, while simulating the designed transistor device, a small number of transistor devices with different layout parameters may be produced, and the produced transistor devices may be tested to obtain actual test data, and based on the actual test data, a test curve may be generated and compared with an output characteristic curve obtained by simulation or a curve related to stress to verify the simulation model. Layout parameters of the transistor device include a channel length L, a channel width W, SA, SB, and a length LOD of an Oxide Definition (OD).

Referring to fig. 2, a physical layout of a typical transistor device is schematically shown in fig. 2, and layout parameters L, W, SA, SB, and LOD are shown.

Further, for different simulation models, layout parameters of transistor devices for testing are different, for example, for the basic current-voltage model, a plurality of structures with variable sizes and constant values of SA should be constructed, where the sizes include a channel length L and a channel width W; for the LOD effect model, a plurality of structures with constant size and variable SA should be constructed, so that, for convenience of description, the transistor device to be tested in this embodiment includes a first transistor device and a second transistor device, where the number of the first transistor devices is plural, the size of each first transistor device is variable, and SA is constant; the number of the second transistor devices is also plural, and the size of each second transistor device is constant, and SA is variable.

It should be noted that the transistor devices include an N transistor device and a P transistor device, and each transistor device may be a single gate or a multi-gate. For convenience of description, a single-gate, N-type transistor is used for modeling in this embodiment.

Step S104, based on the first transistor device, obtains a first model parameter of the basic current-voltage model.

Specifically, the layout parameters of the transistor device depend on the physical layout of the transistor device, and the process parameters of the transistor device depend on the process conditions of the transistor device. Specifically, in this embodiment, by designing the physical layout and process conditions of the first transistor devices, the layout parameters and the process parameters of each first transistor device can be determined, and the layout parameters and the process parameters are input into the basic current-voltage model, so that the first transistor devices can be simulated to obtain first model parameters; the first model parameters include a threshold voltage (VTH 0 initial), an effective mobility (μ effo), and a saturation velocity Vsattempo.

And S106, adjusting the first model parameter based on the layout parameter of the first transistor device to obtain a second model parameter.

Specifically, the first model parameters corresponding to each set of layout parameters may be obtained by testing a plurality of different sets of layout parameters of the first transistor device, such as a first set of layout parameters (L1, W1, SA1= SB 1) and a second set of layout parameters (L2, W2, SA1= SB 1), and it should be understood that the values of the first model parameters corresponding to each set of layout parameters should be a set of fixed values. When the LOD effect model is used for simulating the stress effect of the second transistor device, a plurality of different sets of layout parameters of the second transistor device are set, for example, a first set of layout parameters (L2, W2, SA1= SB 1) and a second set of layout parameters (L2, W2, SA2= SB 2), and for a model point of the layout parameters (L2, W2, SA1= SB 1), the LOD effect model simulates by using a first model parameter corresponding to the layout parameter in the basic current-voltage model. Therefore, the embodiment of the present application adjusts the first model parameter based on the layout parameter of the first transistor device, so that the first model parameter becomes a variable related to the layout parameter for use in the LOD effect model simulation.

It should be understood that the second model parameters include threshold voltage, effective mobility, and saturation velocity.

And S108, applying the second model parameter to the LOD effect model to obtain the optimized LOD effect model.

Specifically, the simulation is carried out by generally establishing an effect SPICE model in the field of semiconductors, wherein the SPICE model and a stress-related general LOD effect model comprise the following structures: for the mobility model and for the threshold voltage model:

(1) Correlation formula for mobility model

(2) Correlation formula for threshold voltage model

Wherein, in the above formula relating mobility to threshold voltage:

μ _eff effective mobility;

ρ _μeff is the rate of change of μ eff relative to the effective mobility μ effo;

kstres _ μ 0 is a mobility correlation coefficient for a composite level of different lengths, widths, and temperatures;

L _drawn the length of a channel of the layout is taken as the length of the channel;

W _drawn the width of a channel of the layout;

kstress _ vth0 is a threshold voltage correlation coefficient of different length and width integrated levels;

μ _effo the effective mobility extracted for the basic current-voltage model;

KU0, LKU0, WKU0, PKU0, TKU0, LLODKU0 and WLODKU0 are model parameters related to mobility change in an LOD effect model;

inv _ sa and Inv _ sb are stress parameters, and SAref and SBref are reference distance values set according to a process;

vsattemp is the saturation velocity;

vsattempo is the saturation velocity extracted by the basic current-voltage model;

KVSAT is a model parameter related to saturation speed change in an LOD effect model;

TNOM is room temperature, typically 25 ℃;

temperature is the test Temperature;

VTH0 is the threshold voltage;

VTH0original is the threshold voltage extracted for the basic current-voltage model;

inv _ saref and Inv _ sbref are stress reference values;

KVTH0, LKVTH0, W KVTH0, P KVTH0, LLODKVTH, WLOD KVTH, STETA0, LODETA0 are model parameters related to threshold voltage shift in LOD effect model;

XL is a channel length offset caused by process factors;

XW is the channel width offset caused by process factors;

WLOD is stress effect width parameter;

and loading the second model parameters obtained in the step 106 and the LO D effect model formula into simulation software for simulation to form an optimized LOD effect model.

According to the optimization method of the LOD effect model, the first model parameter extracted from the basic current-voltage model is adjusted to be the second model parameter based on layout parameter change, and the second simulation parameter is applied to the LOD effect model, so that the optimized LOD effect model is obtained. The optimized LOD effect model is adopted to simulate the transistor device to be tested, so that two transistor devices with the same layout parameters can be eliminated, and the problem that the measured data and the simulated data of the LOD model cannot be completely fitted due to the difference of the test data extracted by the basic current-voltage model and the LOD effect model is solved, so that the influence of the LOD effect on the transistor devices can be more accurately extracted.

Referring to fig. 3, in a possible embodiment, the method for optimizing a LOD effect model according to the embodiment of the present application further includes:

and S302, simulating the second transistor device by using the optimized LOD effect model to obtain a simulation curve.

And S304, adjusting model parameters of the optimized LOD effect model according to the simulation curve and a prestored reference relation curve to obtain a final LOD effect model.

Specifically, a pre-stored reference relation curve is generated based on measured data of a second transistor device, a batch of transistor devices with fixed sizes and variable SA are produced according to layout parameters of the second transistor device, electrical performance test is carried out on each transistor device to obtain electrical performance data of each transistor device, and then the reference relation curve is generated according to the electrical performance data, wherein the reference relation curve comprises: and the SA-Vth relation curve and the SA-Idsat relation curve, wherein Vth is threshold voltage, and Idsat is saturated drain-source current.

After obtaining the optimized LOD effect model, simulating the second transistor device by using the optimized LOD effect model to obtain an initial simulation curve, comparing the initial simulation curve with the reference relation curve, and adjusting model parameters of the optimized LOD effect model according to the comparison result, wherein the mode of adjusting the model parameters is various, for example, setting an initial value according to an empirical value, or taking a median value of multiple test results as the initial value, and adjusting the initial value within a set threshold value according to the comparison result until the simulation curve is matched with the reference relation curve to obtain a final LOD effect model.

According to the optimization method of the LOD effect model, on the basis of the optimized LOD effect model, the model parameters are further adjusted according to the pre-stored reference relation curve, so that the simulation result is closer to the actually measured data, and the extraction precision of the LOD effect model is further improved.

The following describes in detail the method for optimizing the LOD effect model provided in the embodiments of the present application.

Referring to fig. 4, in step S106, the first model parameter is adjusted based on the layout parameter of the first transistor device to obtain a second model parameter, which includes

Step S402, establishing a proportional function of the first model parameter and the layout parameter, and combining the proportional functions to obtain a distance function model.

Step S404, adding the distance function model into the formula of the basic current-voltage model.

Step S406, a formula of adding a distance function model is adopted to simulate the first transistor device, and a simulation result is used as a second model parameter of the basic current-voltage model.

Specifically, the first model parameters comprise threshold voltage, effective mobility and saturation velocity, the layout parameters comprise the size and SA of the first transistor device, wherein the size comprises channel length and channel width, and the layout parameters of the first transistor device are a plurality of groups of parameters with the size as a variable and the SA as a constant value; specifically in this embodiment, SA for the first transistor device is set to SA = SB =5e-6m.

In one possible embodiment, the distance function model includes:

wherein dvth0_ lod is a threshold voltage correction parameter related to SA;

dlvth0_ lod, dwvth0_ lod, and dpvth0_ lod are size-related parameters;

sa is the distance from the grid electrode of each transistor device to the edge of the active region;

lef is the channel length of each transistor device;

wef is the channel width of each transistor device;

nf is the number of sub-gates in each transistor device;

mr is the number of parallel transistor devices;

du0_ lod is a mobility correction parameter related to the SA;

dlu0_ lod, dwu0_ lod and dpu0_ lod are size-related parameters;

dvsat _ lod is the saturation velocity correction parameter associated with SA.

In the formula of the basic current-voltage model, the above distance function model is added, and it should be understood that the formula added to the distance function model is a formula related to the threshold voltage, the mobility and the saturation velocity, and the remaining existing parameters in the basic current-voltage model formula, such as KU0, LKU0, WKU0, PKU0 and the like, which are referred to in step S108, together form a new formula. And simulating the first transistor device by adopting the new formula, and taking the obtained simulation result as a second model parameter.

It should be noted that, in practical application, the first model parameter or the second model parameter called in the LOD effect model may be determined according to simulation needs, and only one flag bit needs to be added to the calling program.

And after the second model parameter is obtained, the second model parameter and the current LOD effect model parameter form an optimized LOD effect model parameter, the optimized LOD effect model parameter and the second model parameter are loaded into simulation software together, the transistor device to be tested is simulated to obtain an initial simulation curve, further, on the basis of the initial simulation curve, model fitting is carried out on the actual measurement data by adjusting the distance function model and the model parameter of the optimized LOD effect model, and when the simulation curve is matched with the actual measurement data, a final LOD effect model is obtained.

Referring to fig. 5 and 6, the abscissa of fig. 5 and 6 is SA of the transistor device, the ordinate of fig. 5 is the threshold voltage of the transistor device, and the ordinate of fig. 6 is the saturated drain-source current of the transistor device. The model curve 11 in fig. 5 and the model curve 12 in fig. 6 are LOD effect models extracted by using LOD parameters in the prior art, respectively, and it can be seen that there is a difference between the simulation curve and the measured data in fig. 5 and 6, no matter how the existing model parameters are adjusted, the simulation curve and the measured data cannot be completely fitted, the fitting is more difficult as the SA is larger, and the existing parameters have little effect on the threshold voltage and the saturation drain-source current of the model point set in the basic model where SA (SB) =5e-6m.

The following steps of fitting are described in conjunction with the graphs of fig. 5 and 6:

the threshold voltage LOD effect model fitting method comprises the following steps:

referring to FIG. 5, first, the threshold voltage correction parameter associated with SA is adjusted

The values, and the size-related parameters dlvth0_ lod, dwvth0_ lod, and dpvth0_ lod are adjusted so that the threshold voltage model point of SA =5e-6m is matched with the measured data, and at this time, the model curve with SA smaller than 5e-6m is also moved, but is not completely fitted with the corresponding measured data, as shown in the model curve 21.

Secondly, threshold voltage offset parameters KVTH0, LKVTH0, W KVTH0, P KVTH0, LLODKVTH, WLOD KVTH, STETA0, LODETA0 and the like related to the LOD effect in the universal LOD effect model architecture are adjusted, so that a model curve with SA smaller than 5e-6m is fitted with measured data, as shown by a model curve 31.

The fitting method of the saturated drain-source current LOD effect model is as follows:

referring to fig. 6, first, the mobility correction parameter du0_ lod related to SA is adjusted, and the size-related parameters dlu0_ lod, dwu0_ lod, dpu0_ lod and saturation velocity correction parameter dvsat _ lod are adjusted, so that the saturated drain-source current model point of SA =5e-6m is matched with the measured data, and the model curve with SA smaller than 5e-6m is shifted, but is not completely fitted with the corresponding measured data, as shown in the model curve 22.

Secondly, mobility and saturation velocity offset parameters KU0, LKU0, WKU0, PKU0, TKU0, LLODKU0, WLODKU0 and the like related to the LOD effect in the universal LOD effect model architecture are adjusted, so that a model curve with SA smaller than 5e-6m is fitted with the measured data, as shown by a model curve 32.

Therefore, by adopting the optimized LOD effect model in the embodiment of the application, the simulation curve, especially for the condition of large SA, and the measured data can be well fitted, and the extraction precision of the LOD effect model is greatly improved.

According to the optimization method of the LOD effect model, the first model parameter extracted from the basic current-voltage model is adjusted to be the second model parameter based on layout parameter change, and the second simulation parameter is applied to the LOD effect model, so that the optimized LOD effect model is obtained. The optimized LOD effect model is adopted to simulate the transistor device to be tested, so that the problem that the measured data and the simulation data of the LOD model cannot be completely fitted due to the fact that two transistor devices with the same layout parameters have differences in the test data extracted by the basic current-voltage model and the LOD effect model can be solved. Furthermore, the method and the device adjust the model parameters on the basis of the optimized LOD effect model according to a prestored reference relation curve so that the simulation result is closer to the actually measured data, and therefore the influence of the LOD effect on the transistor device is more accurately extracted.

Based on the same inventive concept, the embodiment of the application also provides a manufacturing method of an integrated circuit, which is characterized in that the LOD effect model is optimized by adopting the optimization method of the LOD effect model disclosed in the embodiment, and the integrated circuit is manufactured by adopting the simulation structure of the optimized LOD effect model.

Further, in a feasible embodiment, the embodiment of the present application further simulates the second transistor device by using the optimized LOD effect model to obtain a simulation curve, adjusts model parameters of the distance function model and the optimized LOD effect model according to the simulation curve and a pre-stored reference relationship curve to obtain a final LOD effect model, and manufactures the integrated circuit by using a simulation structure of the final LOD effect model.

According to the manufacturing method of the integrated circuit, the designed transistor device is simulated by adopting the LOD effect model with higher extraction precision, the simulation result is closer to the actually measured data, the influence of the LOD effect on the designed transistor device can be accurately calculated, and a designer can conveniently manufacture the integrated circuit with better performance.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

In one possible embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 7. The computer device includes a processor, a memory, an Input/Output interface (I/O for short), and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer equipment is used for storing the measured data and the simulation data of the basic current-voltage model and the LOD effect model. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for connecting and communicating with an external terminal through a network. The computer program is executed by a processor to implement a method of optimizing a model of LOD effects and a method of manufacturing an integrated circuit.

It will be appreciated by those skilled in the art that the configuration shown in fig. 7 is a block diagram of only a portion of the configuration associated with the present application, and is not intended to limit the computing device to which the present application may be applied, and that a particular computing device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

In a possible embodiment, a computer device is provided, comprising a memory in which a computer program is stored and a processor which, when executing the computer program, implements the steps in the embodiments of the method for optimization of a LOD effect model and a method for manufacturing an integrated circuit as described above.

In a possible embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned embodiments of the method for optimizing a model of LOD effects and a method for manufacturing an integrated circuit.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in the embodiments provided herein can include at least one of non-volatile and volatile memory. The nonvolatile Memory may include a Read-Only Memory (ROM), a magnetic tape, a floppy disk, a flash Memory, an optical Memory, a high-density embedded nonvolatile Memory, a resistive Random Access Memory (ReRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), a Phase Change Memory (PCM), a graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, the RAM may take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the various embodiments provided herein may be, without limitation, general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, or the like.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for optimizing an LOD effect model, the method comprising:

constructing a structure of a transistor device to be tested; the transistor device under test comprises a first transistor device;

and applying the second model parameter to an LOD effect model to obtain an optimized LOD effect model.

2. The optimization method according to claim 1, wherein the number of the first transistor devices is plural, the size of each first transistor device is variable, and a gate-to-active region edge distance SA is constant;

wherein the dimensions include a channel length and a channel width.

3. The optimization method of claim 2, wherein said deriving a first model parameter of a base current-voltage model based on said first transistor device comprises:

4. The optimization method according to claim 2, characterized in that: adjusting the first model parameter based on the layout parameter of the first transistor device to obtain a second model parameter, including:

establishing a proportional function of the first model parameter and the layout parameter, and combining the proportional functions to obtain a distance function model;

the layout parameters comprise the size and SA of a first transistor device, and the first model parameters comprise a threshold voltage, effective mobility and saturation velocity;

5. The optimization method according to claim 4, wherein the transistor device under test comprises a plurality of second transistor devices, the size of each second transistor device is a fixed value, and SA is a variable.

6. The optimization method of claim 5, wherein applying the second model parameters to the LOD effect model comprises:

7. The optimization method of claim 5, further comprising:

8. The optimization method according to claim 7, wherein the reference relationship curve is obtained by previously measuring electrical performance data of each second transistor device;

the reference relationship curve includes: a SA-Vth relation curve and a SA-Idsat relation curve;

9. The optimization method of claim 8, wherein the adjusting the model parameters of the optimized LOD effect model according to the simulation curve and a pre-stored reference relationship curve to obtain a final LOD effect model comprises:

comparing the simulated curve with the reference relationship curve;

10. A method of manufacturing an integrated circuit, characterized by optimizing a LOD effect model using the method of any of claims 1-9, and manufacturing the integrated circuit using the simulation structure of the optimized LOD effect model.