CN115769358A - Element alignment chamber and method of manufacturing display device using the same - Google Patents
Element alignment chamber and method of manufacturing display device using the same Download PDFInfo
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- CN115769358A CN115769358A CN202180047560.0A CN202180047560A CN115769358A CN 115769358 A CN115769358 A CN 115769358A CN 202180047560 A CN202180047560 A CN 202180047560A CN 115769358 A CN115769358 A CN 115769358A
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The present invention relates to an element alignment chamber and a method of manufacturing a display device using the same. The component alignment chamber according to an embodiment includes: a chamber; a stage disposed within the chamber; a substrate disposed on the stage and including an active area in which the light emitting element is aligned and a non-active area surrounding the active area and including a pad part; a detection unit disposed on the stage and applying an alignment signal to a pad part of the substrate; and a cooling unit including a cooling water passage overlapping the pad portion between the pad portion and the stage of the substrate and a cooling supply portion provided outside the chamber and supplying cooling water to the cooling water passage.
Description
Technical Field
The present invention relates to an element alignment chamber and a method of manufacturing a display device using the same.
Background
With the development of multimedia technology, the importance of display devices is increasing. Therefore, various types of Display devices such as an Organic Light Emitting Display device (Organic Light Emitting Display), a liquid crystal Display device (LCD), and the like have been used.
As a device for displaying an image of a display device, a display panel such as an organic light emitting display panel or a liquid crystal display panel is included. Among them, the Light Emitting display panel may include a Light Emitting element, for example, in the case of a Light Emitting Diode (LED), there are an Organic Light Emitting Diode (OLED) using an organic substance as a fluorescent substance, an inorganic Light Emitting Diode using an inorganic substance as a fluorescent substance, and the like.
Disclosure of Invention
Technical problem
An object of the present invention is to provide an element alignment chamber capable of preventing a burn-in (burn) defect by cooling heat generated from a pad portion of a substrate when a probe signal is applied, and a method of manufacturing a display device using the same.
Technical problems of the present invention are not limited to the above technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.
Solving means
The component alignment chamber according to an embodiment to solve the above technical problem may include: a chamber; a stage disposed within the chamber; a substrate disposed on the stage and including an active area in which a light emitting element is aligned and a non-active area surrounding the active area and including a pad part; a detection unit disposed on the stage and applying an alignment signal to the pad part of the substrate; and a cooling unit including a cooling water passage overlapping the pad portion between the pad portion and the stage of the substrate and a cooling supply portion provided outside the chamber and supplying cooling water to the cooling water passage.
The cooling water passage may extend in parallel with an extending direction of the pad portion of the substrate.
At least a portion of the cooling water passage may overlap the pad portion of the substrate.
The cooling water passage may have a width greater than or equal to a width of the pad part of the substrate.
The pad portion of the substrate may completely overlap the cooling water passage.
The detection unit may include: a detection support disposed on the stage; and a probe pad disposed at one end of the probe support, and the cooling water passage may extend in parallel with an extending direction of the probe pad.
At least a portion of the cooling water passage may overlap the probe pad.
The stage may include a plurality of proximity pins on an upper surface thereof for supporting the substrate, and the cooling water passage may be disposed between the proximity pins.
The chamber may include a plurality of chamber holes through which the cooling water passage passes.
The stage may include a plurality of stage holes through which the cooling water passage passes.
The cooling supply part may be disposed below the chamber, and the plurality of chamber holes may be disposed at a lower surface of the chamber and overlap the plurality of stage holes.
The cooling supply part may include: a first cooling supply and a second cooling supply; and a first cooling water passage connected to the first cooling supply portion and a second cooling water passage connected to the second cooling supply portion, and the first cooling water passage and the second cooling water passage may respectively pass through the chamber hole and the stage hole and be in point contact with the pad portion of the substrate.
The cooling supply part may be disposed above the chamber, and the plurality of chamber holes are disposed at both side surfaces of the chamber.
The cooling unit may include: a first cooling water passage connected to one side of the cooling supply part; and a second cooling water passage connected to the other side of the cooling supply part, and the first cooling water passage and the second cooling water passage may each extend to a side surface and an upper surface of the chamber through the chamber hole.
Further, the method of manufacturing a display device according to the embodiment may include: preparing a substrate; a step of preparing a component alignment chamber, the component alignment chamber comprising: a chamber; a stage disposed within the chamber; a substrate disposed on the stage and including an active area in which a light emitting element is aligned and a non-active area surrounding the active area and including a pad part; a detection unit disposed on the stage and applying an alignment signal to the pad part of the substrate; and a cooling unit including a cooling water passage overlapping the pad portion between the pad portion and the stage of the substrate and a cooling supply portion provided outside the chamber and supplying cooling water to the cooling water passage; a step of placing the substrate on the stage of the component alignment chamber; a step of operating the cooling unit to bring the detecting unit into contact with the pad portion of the substrate and apply an electric signal; a step of coating a light emitting element ink on the substrate and aligning the light emitting elements; and a step of forming a plurality of insulating layers and a plurality of electrodes on the substrate.
The table may include a plurality of proximity pins, wherein the substrate is supported by the plurality of proximity pins.
By the operation of the cooling unit, cooling water supplied from the cooling supply portion may be circulated in the cooling water passage to cool the pad portion of the substrate.
The step of preparing the substrate may include: forming a first bank and a second bank which are juxtaposed to each other on the substrate, forming a first alignment electrode overlapping the first bank and a second alignment electrode overlapping the second bank, and forming a first insulating layer on the first alignment electrode and the second alignment electrode.
The probing unit may include a probing supporter and a probing pad disposed at one end of the probing supporter, and an electric field may be generated between the first and second alignment electrodes by contacting the probing pad to the pad portion of the substrate and applying an electric signal.
In the step of aligning the light emitting elements, the light emitting elements may be aligned by an electric field generated between the first alignment electrode and the second alignment electrode, and after the step of aligning the light emitting elements, a solvent of the light emitting element ink may be dried.
Other embodiments are specifically contemplated by and are encompassed by the detailed description and the accompanying drawings.
Advantageous effects
According to the element alignment chamber of the embodiment, it is possible to prevent the pad portion from generating burn marks by preventing the temperature of the pad portion of the substrate in contact with the detection unit from rising.
In addition, according to the method of manufacturing the display device of the embodiment, the productivity of the display device may be improved by preventing the generation of the burn mark at the pad portion of the substrate.
Effects according to the embodiments are not limited to the above, and more effects are included in the present specification.
Drawings
Fig. 1 is a schematic plan view of a display device according to an embodiment.
Fig. 2 is a plan view illustrating a pixel of the display device according to the embodiment.
Fig. 3 is a sectional view taken along line Q1-Q1', line Q2-Q2', and line Q3-Q3' of fig. 2.
Fig. 4 is a perspective view schematically illustrating a light emitting element according to an embodiment.
Fig. 5 is a schematic diagram of a light emitting element according to another embodiment.
Fig. 6 is a perspective view illustrating an element alignment chamber according to an embodiment.
Fig. 7 is a side view of the component alignment chamber as viewed from a second direction according to an embodiment.
Fig. 8 is a side view of the component alignment chamber as viewed from a first direction according to an embodiment.
Fig. 9 is a plan view illustrating a stage of a component alignment chamber according to an embodiment.
Fig. 10 is a plan view illustrating an element alignment chamber according to an embodiment.
Fig. 11 to 14 are plan views illustrating various structures of a cooling water passage and a pad portion of a substrate according to an embodiment.
Fig. 15 and 16 are side views showing an element alignment chamber according to another embodiment.
Fig. 17 is a flowchart illustrating a method of manufacturing a display device according to an embodiment.
Fig. 18 is a cross-sectional view illustrating a part of a process of manufacturing a display device according to an embodiment.
Fig. 19 is a side view illustrating an element alignment chamber according to an embodiment.
Fig. 20 is a cross-sectional view illustrating a part of a process of manufacturing a display device according to an embodiment.
Fig. 21 is a side view illustrating an element alignment chamber according to an embodiment.
Fig. 22 to 24 are sectional views illustrating a part of a process of manufacturing a display device according to an embodiment.
Detailed Description
Advantages and features of the present invention and methods of accomplishing the same will become apparent from the following detailed description of the embodiments when considered in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed hereinafter, but may be implemented in various different forms, and the embodiments are provided only for completeness of disclosure and to inform the scope of the invention to a person of ordinary skill in the art to which the present invention pertains, and the present invention is limited only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same constituent elements.
When an element or layer is referred to as being "on" or "over" another element or layer, it includes not only the case where the element or layer is directly on the another element or layer, but also the case where the another element or layer is interposed therebetween. In contrast, when an element is referred to as being "directly above" or "directly over," it means that there is no intervening element or layer present.
Although the terms first, second, etc. may be used to describe various elements, components and/or sections, it should be apparent that these elements, components and/or sections are not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, within the technical idea of the present invention, it is obvious that a first element, a first constituent element, or a first portion mentioned hereinafter may also be a second element, a second constituent element, or a second portion.
The various features of the various embodiments of the present invention may be partially or fully combined or combined with each other, may be technically interlocked and driven with each other, and the various embodiments may be implemented independently of each other or may be implemented in association with each other.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic plan view of a display device according to an embodiment.
Referring to fig. 1, a display device 10 displays a moving image or a still image. Display device 10 may refer to any electronic device that provides a display screen. For example, the display device 10 may include a television, a notebook computer, a monitor, an advertisement board, the internet of things, a mobile phone, a smart phone, a tablet Personal Computer (PC), an electronic clock, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic organizer, an electronic book, a Portable Multimedia Player (PMP), a navigator, a game machine, a digital camera, a camcorder, etc., which provide a display screen.
The display device 10 includes a display panel that provides a display screen. Examples of the display panel may include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, and the like. Hereinafter, the case of applying the inorganic light emitting diode display panel is exemplified as an example of the display panel, but the present invention is not limited thereto, and other display panels may be applied as long as the same technical idea can be applied.
The shape of the display device 10 may be changed in various ways. For example, the display device 10 may have a shape of a transverse rectangle, a longitudinal rectangle, a square, a rectangle with rounded corners (dome points), other polygons, a circle, or the like. The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. In fig. 1, a display device 10 having a laterally rectangular shape and a display area DPA are shown.
The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area where an image may be displayed, and the non-display area NDA may be an area where no image is displayed. The display area DPA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DPA may occupy substantially the center of the display device 10.
The display area DPA may include a plurality of pixels PX. A plurality of pixels PX may be arranged in a matrix direction. The shape of each pixel PX may be a rectangle or a square in a plane, but is not limited thereto, and may be a diamond shape in which each side thereof is inclined with respect to a direction. Each pixel PX may be alternately arranged in a stripe or Pentile form. In addition, each pixel PX may include one or more light emitting elements that emit light having a specific wavelength band to display a specific color.
The non-display area NDA may be disposed around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may constitute a bezel of the display device 10. The wiring or the circuit driving part included in the display device 10 may be disposed in the non-display area NDA, or an external device may be mounted in the non-display area NDA.
Fig. 2 is a plan view illustrating a pixel of the display device according to the embodiment.
Referring to fig. 2, each of the plurality of pixels PX may include a plurality of subpixels PXn (n is an integer of 1 to 3). For example, a pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first subpixel PX1 may emit light of a first color, the second subpixel PX2 may emit light of a second color, and the third subpixel PX3 may emit light of a third color. For example, the first color may be blue, the second color may be green, and the third color may be red. However, it is not limited thereto, and each sub-pixel PXn may emit light of the same color. Further, in fig. 2, the pixel PX is illustrated as including three subpixels PXn, but is not limited thereto, and the pixel PX may include a greater number of subpixels PXn.
Each sub-pixel PXn of the display apparatus 10 may include a light-emitting region EMA and a non-light-emitting region (not shown). The light-emitting region EMA may be a region where the light-emitting element 30 is provided to emit light having a specific wavelength band, and the non-light-emitting region may be a region where the light-emitting element 30 is not provided and light emitted from the light-emitting element 30 does not reach without emitting light. The light-emitting region EMA may include a region where the light-emitting element 30 is disposed, and may include a region adjacent to the light-emitting element 30 and thus light emitted from the light-emitting element 30 is emitted.
However, not limited thereto, the light-emitting region EMA may also include a region from which light emitted from the light-emitting element 30 is reflected or refracted by another member to be emitted therefrom. The light emitting element 30 may be disposed in each subpixel PXn, and a light emitting region may be formed by including a region where the light emitting element 30 is disposed and a region adjacent to the light emitting element 30.
The light emitting region EMA overlaps the respective electrodes 21, 22, and may be provided with contact electrodes CNE1, CNE2 that contact one side and the other side of the light emitting element 30. The contact electrodes CNE1 and CNE2 may be connected to the electrodes 21 and 22 through the opening OP, respectively. The structures of the electrodes 21 and 22 and the contact electrodes CNE1 and CNE2 will be described in detail below.
In addition, each subpixel PXn may include a cutting area CBA disposed in the non-light emitting area. The cutting region CBA may be disposed at one side in the second direction DR2 of the light emitting region EMA. The cutting region CBA may be disposed between the light-emitting regions EMA of the subpixels PXn adjacent to each other in the second direction DR 2. The plurality of light emitting areas EMA and the cutting areas CBA may be arranged in the display area DPA of the display device 10. For example, the plurality of light emitting areas EMA and the cutting areas CBA may be each repeatedly arranged in the first direction DR1, and the light emitting areas EMA and the cutting areas CBA may be alternately arranged in the second direction DR 2. In addition, the cutting regions CBA may be spaced apart in the first direction DR1 by a pitch smaller than that of the light emitting regions EMA in the first direction DR 1. The second bank BNL2 may be disposed between the cutting region CBA and the light emitting area EMA, and a spacing between the cutting region CBA and the light emitting area EMA may vary according to a width of the second bank BNL 2. Since the light emitting element 30 is not provided in the cut region CBA, light is not emitted, but a part of the electrodes 21, 22 provided in the subpixel PXn may be provided in the cut region CBA. The electrodes 21, 22 provided in each sub-pixel PXn may be provided to be separated from each other in the cutting area CBA.
Fig. 3 is a sectional view taken along line Q1-Q1', line Q2-Q2', and line Q3-Q3' of fig. 2. Fig. 3 shows a cross section across both ends of the light emitting element 30 provided in the first sub-pixel PX1 of fig. 2.
Referring to fig. 2 and 3, the display device 10 may include a substrate 11, a semiconductor layer disposed on the substrate 11, a plurality of conductive layers, and a plurality of insulating layers. The semiconductor layer, the conductive layer, and the insulating layer may constitute a circuit layer and a light-emitting element layer of the display device 10, respectively.
Specifically, the substrate 11 may be an insulating substrate. The substrate 11 may be formed of an insulating material such as glass, quartz, or polymer resin. Further, the substrate 11 may be a rigid substrate, but may be a flexible substrate that can be bent, folded, rolled, or the like.
The light-shielding layer BML may be disposed on the substrate 11. The light-shielding layer BML is provided to overlap the active layer ACT1 of the first transistor T1 of the display device 10. The light-shielding layer BML1 includes a material for blocking light, thereby preventing light from being incident to the active layer ACT1 of the first transistor T1. For example, the light blocking layer BML may be formed of an opaque metal material that blocks light transmission. However, not limited thereto, in some cases, the light-shielding layer BML may be omitted.
The buffer layer 12 may be disposed on the entire surface of the substrate 11 (including the light-shielding layer BML). The buffer layer 12 may be formed on the substrate 11 to protect the first transistor T1 of the pixel PX from moisture penetrating through the substrate 11 that is easily penetrated by moisture, and the buffer layer 12 may perform a surface planarization function. The buffer layer 12 may be composed of a plurality of inorganic layers alternately stacked. For example, the buffer layer 12 may be formed as a multi-layer in which inorganic layers including at least any one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy) are alternately stacked.
The semiconductor layer is disposed on the buffer layer 12. The semiconductor layer may include the active layer ACT1 of the first transistor T1. They may be disposed to partially overlap with the gate electrode G1 of the first gate conductive layer, which will be described below.
In addition, although only the first transistor T1 among the transistors included in the subpixel PXn of the display device 10 is illustrated in the drawings, it is not limited thereto. The display device 10 may include a larger number of transistors. For example, in each subpixel PXn, one or more transistors may be further included on the basis of the first transistor T1, and thus the display apparatus 10 may also include two or three transistors.
The semiconductor layer may include polycrystalline silicon, single crystalline silicon, an oxide semiconductor, or the like. When the semiconductor layer includes an oxide semiconductor, each active layer ACT1 may include a plurality of conductive regions ACTa, ACTb and a channel region ACTc between the conductive regions ACTa, ACTb. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Oxide (IGO), indium Zinc Tin Oxide (IZTO), indium Gallium Tin Oxide (IGTO), indium Gallium Zinc Tin Oxide (IGZTO), or the like.
In another embodiment, the semiconductor layer may also comprise polysilicon. The polycrystalline silicon may be formed by crystallizing amorphous silicon, and in this case, the conductive regions of the active layer ACT1 may be doped regions doped with impurities, respectively.
The first gate insulating layer 13 is disposed on the semiconductor layer and the buffer layer 12. The first gate insulating layer 13 may be disposed on the buffer layer 12 (including the semiconductor layer). The first gate insulating layer 13 may function as a gate insulating layer of each transistor. The first gate insulating layer 13 may be formed as an inorganic layer including an inorganic material, for example, silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy), or as a structure stacked by the above inorganic material.
The first gate conductive layer is disposed on the first gate insulating layer 13. The first gate conductive layer may include a gate electrode G1 of the first transistor T1 and a first capacitance electrode CSE1 of the storage capacitor. The gate electrode G1 may be disposed to overlap the channel region ACTc of the active layer ACT1 in the thickness direction. The first capacitance electrode CSE1 may be provided to overlap with a second capacitance electrode CSE2 to be described later in the thickness direction. In one embodiment, the first capacitor electrode CSE1 may be integrally connected to the gate electrode G1. The first capacitive electrode CSE1 may be disposed to overlap the second capacitive electrode CSE2 in a thickness direction, and a storage capacitor may be formed between the first capacitive electrode CSE1 and the second capacitive electrode CSE2.
The first gate conductive layer may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.
The first interlayer insulating layer 15 may be disposed on the first gate conductive layer. The first interlayer insulating layer 15 may function as an insulating film between the first gate conductive layer and other layers provided on the first gate conductive layer. In addition, the first interlayer insulating layer 15 may be disposed to cover the first gate conductive layer to protect the first gate conductive layer. The first interlayer insulating layer 15 may be formed as an inorganic layer including an inorganic material, for example, silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy), or as a structure stacked by the above inorganic material.
The first data conductive layer may be disposed on the first interlayer insulating layer 15. The first data conductive layer may include the first source electrode S1, the first drain electrode D1, the data line DTL, and the second capacitance electrode CSE2 of the first transistor T1.
The first source electrode S1 and the first drain electrode D1 of the first transistor T1 may contact the conductive regions ACTa, ACTb of the active layer ACT1 through contact holes penetrating the second interlayer insulating layer 17 and the first gate insulating layer 13, respectively. In addition, the first source electrode S1 of the first transistor T1 may be electrically connected to the light-shielding layer BML through another contact hole.
The data line DTL may apply a data signal to other transistors (not shown) included in the display device 10. Although not shown in the drawings, the data line DTL may be connected to a source electrode and a drain electrode of another transistor to transfer a signal applied from the data line DTL.
The second capacitance electrode CSE2 is disposed to overlap the first capacitance electrode CSE1 in the thickness direction. In an embodiment, the second capacitor electrode CSE2 may be integrally connected to the first source electrode S1.
The first data conductive layer may be formed as a single layer or a multi-layer formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.
The second interlayer insulating layer 17 is disposed on the first data conductive layer. The second interlayer insulating layer 17 may function as an insulating film between the first data conductive layer and another layer disposed on the first data conductive layer. In addition, the second interlayer insulating layer 17 may function to cover the first data conductive layer and protect the first data conductive layer. The second interlayer insulating layer 17 may be formed as an inorganic layer including an inorganic material, for example, silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy), or may be formed in a stacked structure thereof.
The second data conductive layer may be disposed on the second interlayer insulating layer 17. The second data conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high potential voltage (or a first power supply voltage) supplied to the first transistor T1 may be applied to the first voltage line VL1, and a low potential voltage (or a second power supply voltage) supplied to the second alignment electrode 22 may be applied to the second voltage line VL2. In addition, in the manufacturing process of the display device 10, the second voltage lines VL2 may also be applied with an alignment signal required for aligning the light emitting elements 30.
The first conductive pattern CDP may be connected to the second capacitor electrode CSE2 through a contact hole formed in the second interlayer insulating layer 17. The second capacitor electrode CSE2 may be integrally formed with the first source electrode S1 of the first transistor T1, and the first conductive pattern CDP may be electrically connected with the first source electrode S1. The first conductive pattern CDP may also contact the first alignment electrode 21 to be described later, and the first transistor T1 may transfer the first power voltage applied from the first voltage line VL1 to the first alignment electrode 21 through the first conductive pattern CDP. In addition, in the drawings, the second data conductive layer is illustrated to include one second voltage line VL2 and one first voltage line VL1, but is not limited thereto. The second data conductive layer may include a greater number of first voltage lines VL1 and second voltage lines VL2.
The second data conductive layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, it is not limited thereto.
The first planarization layer 19 is disposed on the second data conductive layer. The first planarization layer 19 may include an organic insulating material (e.g., an organic material such as Polyimide (PI)) to perform a surface planarization function.
The plurality of first banks BNL1, the plurality of electrodes 21 and 22, the light emitting element 30, the plurality of contact electrodes CNE1 and CNE2, and the second bank BNL2 are provided on the first planarizing layer 19. Further, a plurality of insulating layers PAS1, PAS2, PAS3, and PAS4 may be disposed on the first planarizing layer 19.
The plurality of first banks BNL1 may be disposed directly on the first planarization layer 19. The plurality of first banks BNL1 may have a shape extending in the second direction DR2 in each sub-pixel PXn, but may not extend to the sub-pixel PXn adjacent in the second direction DR2, and may be disposed in the emission area EMA. Further, the plurality of first banks BNL1 may be disposed to be spaced apart from each other in the first direction DR1, and the light emitting element 30 may be disposed between the plurality of first banks BNL1. A plurality of first banks BNL1 may be disposed in each subpixel PXn to form a linear pattern in the display area DPA of the display device 10. Although two first banks BNL1 are shown in the drawings, it is not limited thereto. Depending on the number of electrodes 21, 22, a greater number of first banks BNL1 can be provided.
The first bank BNL1 may have a structure in which at least a portion of the first bank BNL1 protrudes from the upper surface of the first planarization layer 19. The protruding portion of the first bank BNL1 may have an inclined side surface, and light emitted from the light emitting element 30 may be reflected by the electrodes 21, 22 disposed on the first bank BNL1 to be emitted in the upper direction of the first planarization layer 19. The first bank BNL1 can also function as a reflective partition for reflecting light emitted from the light emitting element 30 in an upward direction while providing an area for disposing the light emitting element 30. The side surface of the first bank BNL1 may be inclined in a linear shape, but is not limited thereto, and the first bank BNL1 may also have a semicircular or semi-elliptical shape having a curvature on an outer surface. The first bank BNL1 may include an organic insulating material such as Polyimide (PI), but is not limited thereto.
A plurality of electrodes 21, 22 are disposed on the first bank BNL1 and the first planarization layer 19. The plurality of electrodes 21, 22 may include a first alignment electrode 21 and a second alignment electrode 22. The first and second alignment electrodes 21 and 22 may extend in the second direction DR2 and may be disposed to be spaced apart from each other in the first direction DR 1.
The first and second alignment electrodes 21 and 22 extend in the second direction DR2 in the subpixels PXn, respectively, and may be separated from the other electrodes 21 and 22 in the cutting area CBA. For example, the cut region CBA may be disposed between the light-emitting regions EMA of the subpixels PXn adjacent to each other in the second direction DR2, and the first and second alignment electrodes 21 and 22 may be separated from the other first and second alignment electrodes 21 and 22 disposed in the subpixels PXn adjacent to each other in the second direction DR2 in the cut region CBA. However, without being limited thereto, some of the electrodes 21, 22 may also be not separated for each sub-pixel PXn, but may be disposed to extend beyond the sub-pixels PXn adjacent in the second direction DR2, or only any one of the first alignment electrode 21 and the second alignment electrode 22 may be disposed to be separated.
The first alignment electrode 21 may be electrically connected to the first transistor T1 through a first contact hole CT1, and the second alignment electrode 22 may be electrically connected to the second voltage line VL2 through a second contact hole CT 2. For example, the first alignment electrode 21 may contact the first conductive pattern CDP through the first contact hole CT1 penetrating the first planarization layer 19 in a portion of the second bank BNL2 extending in the first direction DR 1. The second alignment electrode 22 may also contact the second voltage line VL2 through a second contact hole CT2 penetrating the first planarization layer 19 in a portion of the second bank BNL2 extending in the first direction DR 1. However, it is not limited thereto. In another embodiment, the first and second contact holes CT1 and CT2 may also be disposed in the light emitting area EMA surrounded by the second bank BNL2 so as not to overlap the second bank BNL 2.
In the drawing, a case where one first alignment electrode 21 and one second alignment electrode 22 are provided in each subpixel PXn is shown, but not limited thereto, the number of the first alignment electrode 21 and the second alignment electrode 22 provided in each subpixel PXn may be increased. Further, the first and second alignment electrodes 21 and 22 provided in each subpixel PXn may not necessarily have a shape extending in one direction, and the first and second alignment electrodes 21 and 22 may be provided in various structures. For example, the first and second alignment electrodes 21 and 22 may have a partially bent or bent shape, or either one of the first and second alignment electrodes 21 and 22 may be disposed to surround the other electrode.
The first and second alignment electrodes 21 and 22 may each be disposed directly on the first bank BNL1. The first and second alignment electrodes 21 and 22 may each be formed to have a width greater than that of the first bank BNL1. For example, the first alignment electrode 21 and the second alignment electrode 22 may each be disposed to cover the outer surface of the first bank BNL1. The first and second alignment electrodes 21 and 22 may be respectively disposed on the side surfaces of the first bank BNL1, and the pitch between the first and second alignment electrodes 21 and 22 may be smaller than the pitch between the first bank BNL1. Further, at least a portion of the first and second alignment electrodes 21 and 22 may be directly disposed on the first planarization layer 19 such that the first and second alignment electrodes 21 and 22 are disposed on the same plane. However, it is not limited thereto. According to circumstances, the width of each of the electrodes 21 and 22 may be smaller than the width of the first bank BNL1. However, each of the electrodes 21, 22 may be disposed to cover at least one side surface of the first bank BNL1 to reflect light emitted from the light emitting element 30.
Each of the electrodes 21, 22 may include a conductive material having a high reflectivity. For example, each of the electrodes 21, 22 may include a material having a high reflectivity, a metal such as silver (Ag), copper (Cu), aluminum (Al), or the like, or may be an alloy including such as aluminum (Al), nickel (Ni), lanthanum (La), or the like. Each of the electrodes 21, 22 may reflect light emitted from the light emitting element 30 and propagated to the side surface of the first bank BNL1 toward the upper direction of each of the sub-pixels PXn.
However, the electrodes 21 and 22 may include a transparent conductive material. For example, each of the electrodes 21, 22 may include a material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Tin Zinc Oxide (ITZO), or the like. In some embodiments, each of the electrodes 21 and 22 may be formed in a structure in which one or more layers of a transparent conductive substance and a metal layer having a high reflectance are stacked, or may be formed in a single layer including these. For example, each of the electrodes 21, 22 may have a stacked structure of ITO/silver (Ag)/ITO, ITO/Ag/IZO, ITO/Ag/ITZO/IZO, or the like.
In addition, the plurality of electrodes 21, 22 may be electrically connected to the light emitting element 30, and a predetermined voltage may be applied to cause the light emitting element 30 to emit light. The plurality of electrodes 21, 22 may be electrically connected to the light emitting element 30 through the contact electrodes CNE1, CNE2, and an electrical signal applied to the electrodes 21, 22 may be transmitted to the light emitting element 30 through the contact electrodes CNE1, CNE2.
Either one of the first and second alignment electrodes 21 and 22 may be electrically connected to an anode electrode of the light emitting element 30, and the other may be electrically connected to a cathode electrode of the light emitting element 30. However, it is not limited thereto, and the opposite case is also possible.
In addition, each of the electrodes 21 and 22 may also be used to form an electric field in the sub-pixel PXn to align the light emitting element 30. The light emitting element 30 may be disposed between the first and second alignment electrodes 21 and 22 by an electric field formed on the first and second alignment electrodes 21 and 22. The light emitting elements 30 of the display device 10 may be ejected onto the electrodes 21, 22 by an inkjet printing process. When ink including the light emitting element 30 is ejected onto the electrodes 21, 22, an alignment signal is applied to the electrodes 21, 22 to generate an electric field. The light emitting elements 30 dispersed in the ink may be subjected to dielectrophoretic force by an electric field generated on the electrodes 21, 22, and may be aligned on the electrodes 21, 22.
The first insulating layer PAS1 is disposed on the first planarizing layer 19. The first insulating layer PAS1 may be disposed to cover the first bank BNL1 and the first and second alignment electrodes 21 and 22. The first insulating layer PAS1 may protect the first and second alignment electrodes 21 and 22 while insulating the first and second alignment electrodes 21 and 22 from each other. Further, the light emitting element 30 provided on the first insulating layer PAS1 can be prevented from being damaged by direct contact with other members.
In one embodiment, the first insulating layer PAS1 may include an opening OP partially exposing the first and second alignment electrodes 21 and 22. Each opening OP may partially expose a portion of the electrodes 21, 22 disposed on the upper surface of the first bank BNL1. A portion of the contact electrodes CNE1, CNE2 may be in contact with the respective electrodes 21, 22 exposed through the opening OP.
The first insulating layer PAS1 may be formed with a step such that a portion of the upper surface thereof is recessed between the first and second alignment electrodes 21 and 22. For example, since the first insulating layer PAS1 is disposed to cover the first and second alignment electrodes 21 and 22, the upper surface of the first insulating layer PAS1 may form a step according to the shape of the electrodes 21 and 22 disposed under the first insulating layer PAS1. However, it is not limited thereto.
The second bank BNL2 may be disposed on the first insulating layer PAS1. The second bank BNL2 may include portions extending in the first and second directions DR1 and DR2, and be disposed in a lattice pattern on the entire surface of the display region DPA. The second bank BNL2 may be disposed on a boundary between the subpixels PXn so as to distinguish adjacent subpixels PXn.
Further, the second bank BNL2 may be disposed to surround the light emitting area EMA and the cutting area CBA disposed for each sub-pixel PXn to distinguish the light emitting area EMA and the cutting area CBA from each other. The first and second alignment electrodes 21 and 22 may extend in the second direction DR2 and be disposed to cross a portion of the second bank BNL2 extending in the first direction DR 1. As for the portion of the second bank BNL2 extending in the second direction DR2, the width of the portion disposed between the light emitting areas EMA is greater than the width of the portion disposed between the cutting areas CBA. Therefore, the pitch between the cutting regions CBA may be smaller than the pitch between the light emitting regions EMA.
The height of the second bank BNL2 may be greater than the height of the first bank BNL1. The second bank BNL2 may prevent a phenomenon that ink overflows to adjacent subpixels PXn during an inkjet printing process in a process of manufacturing the display device 10, thereby separating inks in which different light emitting elements 30 are dispersed for different subpixels PXn so that they are not mixed with each other. Similar to the first bank BNL1, the second bank BNL2 may include Polyimide (PI), but is not limited thereto.
The light emitting element 30 may be disposed on the first insulating layer PAS1. The plurality of light emitting elements 30 may be arranged spaced apart from each other along the second direction DR2 in which the electrodes 21, 22 extend, and may be aligned substantially parallel to each other. The light emitting element 30 may have a shape extending in a direction, and the extending direction of the electrodes 21, 22 may be substantially perpendicular to the extending direction of the light emitting element 30. However, not limited thereto, the light emitting element 30 may not be perpendicular to the extending direction of the electrodes 21, 22 but may be obliquely disposed.
The light emitting element 30 disposed in each subpixel PXn may include a light emitting layer ("36" in fig. 4) including different materials to emit light having different wavelength bands to the outside. Accordingly, the first, second, and third sub-pixels PX1, PX2, and PX3 may emit light of the first, second, and third colors, respectively. However, without being limited thereto, each sub-pixel PXn may also include the same type of light emitting element 30 to emit substantially the same color light.
Between the first banks BNL1, both ends of the light emitting element 30 may be disposed on the respective electrodes 21, 22. The light emitting element 30 may extend longer than the interval between the first and second alignment electrodes 21 and 22, and both ends of the light emitting element 30 may be disposed on the first and second alignment electrodes 21 and 22, respectively. For example, the light emitting element 30 may be disposed such that one end of the light emitting element 30 is positioned on the first alignment electrode 21 and the other end of the light emitting element 30 is positioned on the second alignment electrode 22.
The light emitting element 30 may include a plurality of layers disposed in parallel with the upper surface of the substrate 11 or the first planarizing layer 19. The light emitting element 30 may be disposed such that a direction in which the light emitting element 30 extends is parallel to the upper surface of the first planarization layer 19, and the plurality of semiconductor layers included in the light emitting element 30 may be sequentially disposed in a direction parallel to the upper surface of the first planarization layer 19. However, not limited thereto, when the light emitting element 30 has a different structure, a plurality of semiconductor layers may be disposed perpendicular to the upper surface of the first planarizing layer 19.
Both ends of the light emitting element 30 may be in contact with the contact electrodes CNE1, CNE2, respectively. For example, in the light emitting element 30, a part of the semiconductor layer may be exposed without forming an insulating film (see "38" of fig. 4) on an end surface in a direction in which it extends, and the exposed semiconductor layer may contact the contact electrodes CNE1, CNE2. However, without being limited thereto, at least a partial region of the insulating film 38 of the light emitting element 30 may be removed so that side surfaces of both ends of the semiconductor layer may be partially exposed. The exposed side surfaces of the semiconductor layer may also directly contact the contact electrodes CNE1, CNE2.
The second insulating layer PAS2 may be partially disposed on the light emitting element 30. For example, the second insulating layer PAS2 is disposed on the light emitting element 30 with a width smaller than the length of the light emitting element 30 to surround the light emitting element 30 while exposing both ends of the light emitting element 30. In the manufacturing process of the display device 10, the second insulating layer PAS2 may be disposed to cover the light emitting element 30, the electrodes 21, 22, and the first insulating layer PAS1, and then the second insulating layer PAS2 may be removed to expose both ends of the light emitting element 30. The second insulating layer PAS2 may be disposed on the first insulating layer PAS1 to extend in the second direction DR2 in a plan view, thereby forming a line-shaped or island-shaped pattern in each subpixel PXn. The second insulating layer PAS2 may fix the light emitting element 30 while protecting the light emitting element 30 in the manufacturing process of the display device 10.
A plurality of contact electrodes CNE1, CNE2 and a third insulating layer PAS3 may be disposed on the second insulating layer PAS 2.
The plurality of contact electrodes CNE1, CNE2 may be provided on the respective electrodes 21, 22 in a shape extending in one direction. The contact electrodes CNE1, CNE2 may include a first contact electrode CNE1 disposed on the first alignment electrode 21 and a second contact electrode CNE2 disposed on the second alignment electrode 22. The respective contact electrodes CNE1, CNE2 may be disposed to be spaced apart from and face each other. For example, the first and second contact electrodes CNE1 and CNE2 are disposed on the first and second alignment electrodes 21 and 22, respectively, and spaced apart from each other in the first direction DR 1. Each of the contact electrodes CNE1, CNE2 may form a stripe pattern in the light emitting area EMA of each sub-pixel PXn.
The plurality of contact electrodes CNE1, CNE2 may be in contact with the light emitting element 30, respectively. The first contact electrode CNE1 may contact one end of the light emitting element 30, and the second contact electrode CNE2 may contact the other end of the light emitting element 30. In the light emitting element 30, the semiconductor layer may be exposed at both end surfaces of the extending direction of the light emitting element 30, and the respective contact electrodes CNE1, CNE2 may be in contact with the semiconductor layer of the light emitting element 30 and electrically connected to the semiconductor layer. The sides of the contact electrodes CNE1, CNE2 that are in contact with both ends of the light emitting element 30 may be disposed on the second insulating layer PAS 2. Further, the first contact electrode CNE1 is in contact with the first alignment electrode 21 through the opening portion OP exposing a portion of the upper surface of the first alignment electrode 21, and the second contact electrode CNE2 is in contact with the second alignment electrode 22 through the opening portion OP exposing a portion of the upper surface of the second alignment electrode 22.
The width of each contact electrode CNE1, CNE2 measured in a direction may be smaller than the width of each electrode 21, 22 measured in the direction, respectively. The contact electrodes CNE1, CNE2 may be disposed to contact one end and the other end of the light emitting element 30, respectively, while covering a portion of the upper surfaces of the first and second alignment electrodes 21, 22. However, it is not limited thereto, and it may be arranged that the width of the contact electrodes CNE1, CNE2 is made larger than the width of the electrodes 21, 22 so as to cover both side edges of the electrodes 21, 22.
The contact electrodes CNE1, CNE2 may include a transparent conductive substance. For example, ITO, IZO, ITZO, aluminum (Al), and the like may be included. Light emitted from the light emitting element 30 may be transmitted through the contact electrodes CNE1, CNE2 and then may travel toward the electrodes 21, 22. However, it is not limited thereto.
In the drawings, it is illustrated that two contact electrodes CNE1, CNE2 are provided in one subpixel PXn, but not limited thereto. The number of the respective contact electrodes CNE1, CNE2 may vary depending on the number of the electrodes 21, 22 provided in each sub-pixel PXn.
The third insulating layer PAS3 is provided to cover the first contact electrode CNE1. The third insulating layer PAS3 may cover a side (including the first contact electrode CNE 1) where the first contact electrode CNE1 is provided with reference to the second insulating layer PAS 2. For example, the third insulating layer PAS3 may be disposed to cover the first contact electrode CNE1 and the first insulating layer PAS1 disposed on the first alignment electrode 21. Such arrangement may be achieved by a process of removing a portion of the insulating material layer to form the second contact electrode CNE2 after disposing the insulating material layer constituting the third insulating layer PAS3 on the entire light emitting area EMA. In the above process, the insulating material layer constituting the third insulating layer PAS3 may be removed together with the insulating material layer constituting the second insulating layer PAS2, and one side of the third insulating layer PAS3 may be aligned with one side of the second insulating layer PAS 2. One side of the second contact electrode CNE2 may be disposed on the third insulating layer PAS3, and may be insulated from the first contact electrode CNE1 by the third insulating layer PAS3.
The fourth insulating layer PAS4 may be disposed on the entire display area DPA of the substrate 11. The fourth insulating layer PAS4 may function to protect a member disposed on the substrate 11 from an external environment. However, the fourth insulating layer PAS4 may be omitted.
Each of the first, second, third, and fourth insulating layers PAS1, PAS2, PAS3, and PAS4 may include an inorganic insulating material or an organic insulating material. For example, an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al 2O 3), aluminum nitride (AlN), or the like may be included. Alternatively, acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, benzocyclobutene resin, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate resin, polycarbonate, polymethyl methacrylate-polycarbonate synthetic resin, or the like may be included as the organic insulating material. However, it is not limited thereto.
Fig. 4 is a perspective view schematically illustrating a light emitting element according to an embodiment.
Referring to fig. 4, the light emitting element 30 may be a light emitting diode, and in particular, the light emitting element 30 may be an inorganic light emitting diode having a micro-scale or nano-scale size and formed of an inorganic material. When an electric field in a specific direction is formed between two electrodes ("21" and "22" of fig. 3) facing each other, the inorganic light emitting diode may be aligned between the two electrodes ("21" and "22" of fig. 3) having polarities. The light emitting element 30 may be aligned between the electrodes 21, 22 by an electric field formed on the two electrodes ("21" and "22" of fig. 3).
The light emitting element 30 according to the embodiment may have a shape extending in a direction. The light emitting element 30 may have a cylindrical shape, a rod shape, a wire shape, a tube shape, or the like. However, the shape of the light emitting element 30 is not limited thereto, and the light emitting element 30 may have various shapes, for example, a polygonal column shape of a cube, a rectangular parallelepiped, a hexagonal prism, or the like, or a shape extending in a direction and an outer surface portion thereof is inclined, or the like. A plurality of semiconductors included in the light emitting element 30 to be described later may have a structure that is sequentially disposed or stacked in the one direction.
The light emitting element 30 may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). An electrical signal applied from an external power source may be transmitted to the semiconductor layer, thereby causing the semiconductor layer to emit light having a specific wavelength band.
As shown in fig. 4, the light emitting element 30 may include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.
The first semiconductor layer 31 may be an n-type semiconductor. When the light emitting element 30 emits light having a blue wavelength band, the first semiconductor layer 31 may include a semiconductor material having a composition ratio of AlxGayIn (1-x-y) N (where 0. Ltoreq. X.ltoreq.1, 0. Ltoreq. Y.ltoreq.1, 0. Ltoreq. X + y. Ltoreq.1). For example, any one or more of n-type AlGaInN, gaN, alGaN, inGaN, alN, and InN may be doped. The first semiconductor layer 31 may be doped with an n-type dopant, and the n-type dopant may be Si, ge, sn, or the like. For example, the first semiconductor layer 31 may be n-GaN doped with n-type Si. The length of the first semiconductor layer 31 may be in the range of 1.5 μm to 5 μm, but is not limited thereto.
The second semiconductor layer 32 is provided on a light-emitting layer 36 to be described later. The second semiconductor layer 32 may be a p-type semiconductor, and when the light emitting element 30 emits light in a blue or green wavelength band, the second semiconductor layer 32 may include a semiconductor material having a composition ratio of AlxGayIn (1-x-y) N (where 0. Ltoreq. X.ltoreq.1, 0. Ltoreq. Y.ltoreq.1, 0. Ltoreq. X + y. Ltoreq.1). For example, any one or more of p-doped AlGaInN, gaN, alGaN, inGaN, alN, and InN may be included. The second semiconductor layer 32 may be doped with a p-type dopant, and the p-type dopant may be Mg, zn, ca, se, ba, etc. For example, the second semiconductor layer 32 may be p-GaN doped with p-type Mg. The length of the second semiconductor layer 32 may be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.
In addition, in the drawings, it is illustrated that the first semiconductor layer 31 and the second semiconductor layer 32 are formed as one layer, but not limited thereto. The first and second semiconductor layers 31 and 32 may further include more layers, for example, a cladding layer or a tensile strain barrier lowering (TSBR) layer, depending on the material of the light emitting layer 36.
The light emitting layer 36 is provided between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material having a single quantum well structure or a multiple quantum well structure. When the light emitting layer 36 includes a material having a multiple quantum well structure, a structure in which a plurality of layers are alternately stacked by quantum layers and well layers may also be used. The light emitting layer 36 may emit light by combination of electron-hole pairs according to an electrical signal applied through the first and second semiconductor layers 31 and 32. When the light emitting layer 36 emits light in a blue wavelength band, the light emitting layer 36 may include AlGaN, alGaInN, or the like. In particular, when the light emitting layer 36 has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layers may include AlGaN or AlGaInN, and the well layers may include a material such as GaN or AlInN. For example, when the light emitting layer 36 includes AlGaInN as a quantum layer and AlInN as a well layer, as described above, the light emitting layer 36 may emit blue light having a central wavelength band in the range of 450nm to 495 nm.
However, without being limited thereto, the light emitting layer 36 may also have a structure in which a semiconductor material having a high band gap energy and a semiconductor material having a low band gap energy are alternately stacked, or may include group III to group V semiconductor materials according to a wavelength band of emitted light. The light emitted from the light-emitting layer 36 is not limited to light of a blue wavelength band, and light of a red wavelength band and a green wavelength band may also be emitted as the case may be. The length of the light emitting layer 36 may be in the range of 0.05 μm to 0.10 μm, but is not limited thereto.
In addition, light emitted from the light emitting layer 36 may be emitted not only from the outer surface in the longitudinal direction of the light emitting element 30 but also from both side surfaces of the light emitting element 30. The directivity of light emitted from the light-emitting layer 36 is not limited to one direction.
Fig. 5 is a schematic diagram of a light emitting element according to another embodiment.
Referring to fig. 5, the light emitting element 30 'according to another embodiment may further include a third semiconductor layer 33' disposed between the first semiconductor layer 31 'and the light emitting layer 36', a fourth semiconductor layer 34 'and a fifth semiconductor layer 35' disposed between the light emitting layer 36 'and the second semiconductor layer 32'. The light emitting element 30' of fig. 5 is different from the embodiment of fig. 4 in that a plurality of semiconductor layers 33', 34', and 35' and electrode layers 37a ' and 37b ' are further provided, and the light emitting layer 36' contains different elements. Hereinafter, duplicate description will be omitted, and differences will be mainly described.
In the light emitting element 30 of fig. 4, the light emitting layer 36 may include nitrogen (N) and emit blue or green light. On the other hand, the light-emitting element 30 'of fig. 5 is a semiconductor in which each of the light-emitting layer 36' and other semiconductor layers includes at least phosphorus (P). The light emitting element 30' according to the embodiment may emit red light having a central wavelength band in a range of 620nm to 750 nm. However, the central wavelength band of red light is not limited to the above range, and should be understood to include all wavelength bands that can be recognized as red in the art.
Specifically, the first semiconductor layer 31' may be an n-type semiconductor layer, and may include a semiconductor material having a composition ratio of InxAlyGa (1-x-y) P (where 0. Ltoreq. X.ltoreq.1, 0. Ltoreq. Y.ltoreq.1, 0. Ltoreq. X + y. Ltoreq.1). The first semiconductor layer 31' may include any one or more of InAlGaP, gaP, alGaP, inGaP, alP, and InP doped with n-type. For example, the first semiconductor layer 31' may be n-AlGaInP doped with n-type Si.
The second semiconductor layer 32' may be a P-type semiconductor layer and may include a semiconductor material having a composition ratio of InxAlyGa (1-x-y) P (where 0. Ltoreq. X.ltoreq.1, 0. Ltoreq. Y.ltoreq.1, 0. Ltoreq. X + y. Ltoreq.1). The second semiconductor layer 32' may include any one or more of InAlGaP, gaP, algainp, inGaP, alP, and InP doped p-type. For example, the second semiconductor layer 32' may be p-GaP doped with p-type Mg.
The light emitting layer 36' may be disposed between the first semiconductor layer 31' and the second semiconductor layer 32 '. The light emitting layer 36' may include a material having a single quantum well structure or a multiple quantum well structure to emit light having a specific wavelength band. When the light emitting layer 36' has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layers may include a material such as AlGaP or AlInGaP, and the well layers may include a material such as GaP or AlInP. For example, the light emitting layer 36' may include AlGaInP as a quantum layer and AlInP as a well layer to emit red light having a central wavelength band of 620nm to 750 nm.
The light emitting element 30 'of fig. 5 may include a cladding layer disposed adjacent to the light emitting layer 36'. As shown, the third and fourth semiconductor layers 33' and 34' disposed between the first and second semiconductor layers 31' and 32' may be cladding layers above and below the light emitting layer 36 '.
The third semiconductor layer 33' may be disposed between the first semiconductor layer 31' and the light emitting layer 36 '. Similar to the first semiconductor layer 31', the third semiconductor layer 33' may be an n-type semiconductor, and the third semiconductor layer 33' may include a semiconductor material having a composition ratio of InxAlyGa (1-x-y) P (where 0. Ltoreq. X.ltoreq.1, 0. Ltoreq. Y.ltoreq.1, 0. Ltoreq. X + y. Ltoreq.1). For example, the first semiconductor layer 31 'may be n-AlGaInP, and the third semiconductor layer 33' may be n-AlInP. However, it is not limited thereto.
The fourth semiconductor layer 34' may be disposed between the light emitting layer 36' and the second semiconductor layer 32 '. Similar to the second semiconductor layer 32', the fourth semiconductor layer 34' may be an n-type semiconductor, and the fourth semiconductor layer 34' may include a semiconductor material having a composition ratio of InxAlyGa (1-x-y) P (where 0. Ltoreq. X.ltoreq.1, 0. Ltoreq. Y.ltoreq.1, 0. Ltoreq. X + y. Ltoreq.1). For example, the second semiconductor layer 32 'may be p-GaP and the fourth semiconductor layer 34' may be p-AlInP.
The fifth semiconductor layer 35' may be disposed between the fourth semiconductor layer 34' and the second semiconductor layer 32 '. The fifth semiconductor layer 35' may be a p-type doped semiconductor, similar to the second and fourth semiconductor layers 32' and 34 '. In some embodiments, the fifth semiconductor layer 35' may function to reduce a lattice constant difference between the fourth semiconductor layer 34' and the second semiconductor layer 32 '. The fifth semiconductor layer 35' may be a tensile stress barrier lowering (TSBR) layer. For example, the fifth semiconductor layer 35' may include p-GaInP, p-AlInP, p-AlGaInP, etc., but is not limited thereto. In addition, the lengths of the third, fourth, and fifth semiconductor layers 33', 34', and 35' may be in the range of 0.08 to 0.25 μm, but are not limited thereto.
The first electrode layer 37a 'and the second electrode layer 37b' may be disposed on the first semiconductor layer 31 'and the second semiconductor layer 32', respectively. The first electrode layer 37a 'may be disposed on a lower surface of the first semiconductor layer 31', and the second electrode layer 37b 'may be disposed on an upper surface of the second semiconductor layer 32'. However, without being limited thereto, at least any one of the first electrode layer 37a 'and the second electrode layer 37b' may be omitted. For example, in the light emitting element 30', the first electrode layer 37a ' may not be provided on the lower surface of the first semiconductor layer 31', but only one second electrode layer 37b ' may be provided on the upper surface of the second semiconductor layer 32 '.
In addition, referring again to fig. 3, the electrode layer 37 may be an ohmic contact electrode. However, it is not limited thereto, and may also be a Schottky (Schottky) contact electrode. The light emitting element 30 may comprise at least one electrode layer 37. In fig. 4, the light emitting element 30 is shown to include one electrode layer 37, but is not limited thereto. According to circumstances, the light emitting element 30 may include a larger number of electrode layers 37 or omit the electrode layers 37. The description of the light emitting element 30 can be equally applied even if the number of the electrode layers 37 is changed or the light emitting element 30 includes other structures.
When the light emitting element 30 is electrically connected to an electrode or a contact electrode in the display device 10 according to the embodiment, the electrode layer 37 may reduce resistance between the light emitting element 30 and the electrode or the contact electrode. The electrode layer 37 may include a metal having conductivity. For example, the electrode layer 37 may include at least any one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and Indium Tin Zinc Oxide (ITZO). Furthermore, the electrode layer 37 may also comprise a doped n-type or p-type semiconductor material. The electrode layer 37 may include the same material or a different material, but is not limited thereto.
The insulating film 38 is provided so as to surround the outer surfaces of the plurality of semiconductor layers and the electrode layer. For example, the insulating film 38 may be provided so as to surround at least the outer surface of the light emitting layer 36, and may extend in the direction in which the light emitting element 30 extends. The insulating film 38 may function to protect the above members. The insulating film 38 may be formed to surround the side surfaces of the above members, and may be formed to expose both ends of the light emitting element 30 in the length direction.
In the drawings, it is illustrated that the insulating film 38 is formed to extend in the length direction of the light emitting element 30 to cover the side surfaces of the first semiconductor layer 31 to the electrode layer 37, but is not limited thereto. The insulating film 38 may cover only a part of the outer surface of the semiconductor layer (including the light emitting layer 36), or may cover only a part of the outer surface of the electrode layer 37, thereby partially exposing the outer surface of the electrode layer 37. Further, the insulating film 38 may be formed to have a circular upper surface in cross section in a region adjacent to at least one end portion of the light emitting element 30.
The thickness of the insulating film 38 may be in the range of 10nm to 1.0 μm, but is not limited thereto. Preferably, the thickness of the insulating film 38 may be about 40 nm.
The insulating film 38 may include a material having an insulating property, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (Al 2O 3), or the like. Therefore, an electrical short that may occur when the light emitting layer 36 is in direct contact with an electrode that transmits an electrical signal to the light emitting element 30 can be prevented. Further, since the insulating film 38 protects the outer surface including the light emitting layer 36 and the light emitting element 30, a decrease in light emission efficiency can be prevented.
Further, the outer surface of the insulating film 38 may be surface-treated. The light emitting elements 30 may be ejected and aligned on the electrodes in a state of being dispersed in a predetermined ink. At this time, the surface of the insulating film 38 may be treated to have hydrophobicity or hydrophilicity so that the light emitting elements 30 do not aggregate with adjacent light emitting elements 30 in the ink but remain dispersed in the ink. For example, the outer surface of the insulating film 38 may be surface-treated with stearic acid, 2, 3-naphthalenedicarboxylic acid, or the like.
The length h of the light emitting element 30 may be in the range of 1 μm to 10 μm, or 2 μm to 6 μm, preferably 3 μm to 5 μm. Further, the diameter of the light emitting element 30 may be in the range of 30nm to 700nm, and the aspect ratio of the light emitting element 30 may be in the range of 1.2 to 100. However, not limited thereto, the plurality of light emitting elements 30 included in the display device 10 may have different diameters according to the difference in composition of the light emitting layer 36. Preferably, the diameter of the light emitting element 30 may be in the range of about 500 nm.
The shape and material of the light emitting element 30 are not limited to fig. 4 and 5. In some embodiments, the light emitting element 30 may also include a greater number of layers or may have a different shape.
The light emitting element 30 is coated on the substrate by a solution process such as ink-jet, and the light emitting element 30 is aligned on the electrode by an applied electric field. In order to apply an electric field, the pad portion of the substrate is brought into contact with the probe device, but a high temperature may be generated at the pad portion in contact with the probe device, thereby causing a burn-in (burn). Hereinafter, an element alignment chamber capable of preventing the generation of burn marks during the contact of a probe device with a pad portion of a substrate to apply an electric field will be described.
Fig. 6 is a perspective view illustrating an element alignment chamber according to an embodiment. Fig. 7 is a side view of the component alignment chamber as viewed from a second direction according to an embodiment. Fig. 8 is a side view of the component alignment chamber as viewed from a first direction according to an embodiment. Fig. 9 is a plan view illustrating a stage of a component alignment chamber according to an embodiment. Fig. 10 is a plan view illustrating an element alignment chamber according to an embodiment. Fig. 11 to 14 are plan views illustrating various structures of a pad portion of a substrate and a cooling water passage according to an embodiment.
In the drawing, a first direction D1, a second direction D2 and a third direction D3 are defined. The first direction D1 and the second direction D2 are located on one plane and are orthogonal to each other, and the third direction D3 is a direction perpendicular to each of the first direction D1 and the second direction D2.
Fig. 6, 7, and 8 are exemplary views for explaining the structure of the component alignment chamber 100 according to the embodiment, and the structure and arrangement of the component alignment chamber 100 are not limited to fig. 6, 7, and 8. The element alignment chamber 100 may include more components and may also be formed in a different structure than the structures of fig. 6, 7, and 8.
Referring to fig. 6, 7 and 8, the component alignment chamber 100 according to an embodiment may include a chamber 120, a stage 140 disposed within the chamber 120, a substrate 200 disposed on the stage 140, a detection unit 300 disposed on the stage 140, and a cooling unit 400. The device alignment chamber 100 may align the light emitting devices.
The chamber 120 is used to dispose a portion of the stage 140, the substrate 200, the detection unit 300, and the cooling unit 400 therein, thereby providing an environment in which process conditions such as temperature, pressure, and the like can be adjusted. In one embodiment, the chamber 120 may adjust a temperature condition from a room temperature to about 150 ℃ to perform a process for aligning and drying the light emitting elements, etc. The chamber 120 may be formed in a box shape having a horizontal length extending in the first direction D1, a horizontal width extending in the second direction D2, and a vertical height extending in the third direction D3. For example, the chamber 120 may be formed in a substantially rectangular parallelepiped shape, but is not limited thereto. The chamber 120 is closed on four sides so that the process conditions within the chamber 120 can be maintained.
The stage 140 may be disposed within the chamber 120. The stage 140 may place the substrate 200 thereon, so that the substrate 200 may be supported to perform alignment of the light emitting elements and a drying process of the light emitting element ink on the substrate 200. The stage 140 may have a substantially rectangular shape, and may have a shape similar to the planar shape of the substrate 200. However, the overall planar shape of the stage 140 may vary according to the planar shape of the substrate 200. For example, when the planar shape of the substrate 200 is rectangular, as shown in the drawing, the planar shape of the stage 140 may be rectangular, and when the planar shape of the substrate 200 is circular, the planar shape of the stage 140 may also be circular.
Referring to fig. 9, the stage 140 may include a plurality of proximity pins 160, a plurality of lift pins 170, a plurality of temperature sensors 180, a plurality of suction ports 190, and a first cooling hole PH1 on an upper surface for placing the substrate 200.
The proximity pins 160 function to support the substrate 200 during processing and may space the substrate 200 from the surface of the stage 140. The proximity pins 160 may form an air layer between the substrate 200 and the stage 140, thereby improving uniformity of the substrate 200 through the air layer. The height of the proximity pin 160 may be in the range of 0.5mm to 3 mm. The plurality of proximity pins 160 may uniformly support the substrate 200 such that the substrate 200 does not sag. The number of proximity pins 160 is not particularly limited as long as a part of the substrate 200 can be kept horizontal without sagging.
When the substrate 200 is transferred onto the stage 140 by the robot arm, the lift pins 170 may be raised above the upper surface of the stage 140 to support the substrate 200, and then lowered to place the substrate 200 on the proximity pins 160. The height of the lift pins 170 may be higher than the height of the proximity pins 160 so that the substrate 200 may be easily transferred. The lift pins 170 place the substrate 200 on the proximity pins 160 and then completely descend inside the stage 140 so as not to protrude from the upper surface of the stage 140. The lift pins 170 may be provided in plurality to support the substrate 200. The number of lift pins 170 may be less than the number of proximity pins 160. Unlike the proximity pins 160, the lift pins 170 function to place the substrate 200 on the proximity pins 160, and thus a large number of lift pins 170 may not be required to accurately maintain the level of the substrate 200.
The temperature sensors 180, 182 may sense the temperature within the chamber 120 to monitor the temperature in the process. The temperature sensors 180, 182 may include a first temperature sensor 180 disposed at the center of the stage 140 and a second temperature sensor 182 other than the first temperature sensor 180. The first temperature sensor 180 is disposed to overlap a central portion of the substrate 200 to sense a temperature of the central portion of the substrate 200. The second temperature sensor 182 is disposed to overlap with the edge of the substrate 200 and is disposed adjacent to a cooling water passage ("420" and "430" of fig. 6), which will be described later, to sense the temperature of the pad portion of the substrate 200.
The suction port 190 may function to suck and discharge odor generated when the solvent is dried in the drying process of the light emitting element ink. The suction port 190 is provided around the edge of the stage 140 and is provided in plurality to effectively suck and discharge the smells in the chamber 120 to the outside.
The first cooling holes PH1 may be holes in which cooling water passages ("420" and "430" in fig. 6) protrude and extend from the upper surface of the stage 140. The first cooling holes PH1 may be provided at the edge of the stage 140, and a plurality of the first cooling holes PH1 may be provided according to the number of cooling water passages ("420" and "430" in fig. 6). The first cooling hole PH1 will be described in detail below.
The substrate 200 may be disposed on the stage 140 and may be placed on the proximity pins 160. The substrate 200 may include an active area AA in which the light emitting elements are disposed and a non-active area NAA surrounding the active area AA.
Referring to fig. 10, the non-effective region NAA may include first and second pad parts PD1 and PD2. The first and second pad parts PD1 and PD2 are used to apply a signal for aligning the light emitting element, and may be pad parts formed with pad electrodes connected to alignment electrodes ("21" and "22" of fig. 2) provided in the effective area AA.
The first pad part PD1 may be disposed in the non-effective area NAA adjacent to one side of the effective area AA, and may extend in the second direction D2. The second pad part PD2 may be disposed in the non-effective area NAA adjacent to the other side of the effective area AA and extend in the second direction D2. The first pad part PD1 and the second pad part PD2 may each contact a probe unit 300, 350, which will be described later, to receive a signal for aligning the light emitting elements from the probe unit 300, 350. In an embodiment, two pad portions PD1, PD2 are shown and described to be arranged, but only one pad portion may be provided in the non-effective area NAA, or four pad portions may be provided in the non-effective areas NAA adjacent to the four sides of the effective area AA, respectively.
Referring again to fig. 6, 7 and 8, the detection units 300 and 350 may be disposed on the stage 140 to form an electric field on the substrate 200 disposed on the stage 140. The detection units 300 and 350 each extend in the second direction D2, and may extend by a length shorter than that of one side of the substrate 200. However, the size and shape of each of the detection units 300, 350 may vary according to the substrate 200.
Each of the probing units 300, 350 may include a probing support 310 and a probing pad 330 disposed at one end of the probing support 310. The probe support 310 may move the probe units 300, 350. The detection support 310 may move the detection units 300, 350 in horizontal and vertical directions (e.g., a first direction D1 as a horizontal direction and a third direction D3 as a vertical direction). The sensing units 300 and 350 may be connected to the substrate 200 or separated from the substrate 200 by the driving of the sensing supporter 310. For example, in the step of applying a signal to the substrate 200, the probe support 310 is driven to connect the probe units 300 and 350 to the substrate 200, and in the other steps, the probe support 310 is driven again to separate the probe units 300 and 350 from the substrate 200.
The probing pad 330 may transfer an electrical signal to the substrate 200. The probe pads 330 are connected to the substrate 200 to transmit an electrical signal to the substrate 200, thereby forming an electric field on the substrate 200. As an example, the probe pads 330 are in contact with the pad portions PD1, PD2 of the substrate 200, respectively, and form an electric field on the substrate 200 by applying and transferring an electric signal to the alignment electrodes 21, 22 formed in the effective area AA of the substrate 200. For example, the probe pad 330 may include a plurality of probe pins to transmit an electrical signal to the pad portions PD1, PD2 of the substrate 200.
In an embodiment, the detection units 300, 350 may include a first detection unit 300 disposed at one side of the stage 140 and a second detection unit 350 disposed at the other side of the stage 140. However, the number of the sensing units 300, 350 is not particularly limited and may be different according to the number of the pad parts PD1, PD2 of the substrate 200. In the drawing, although the case where the substrate 200 has two pad portions PD1, PD2 so that two detection units 300, 350 are provided is illustrated, four detection units may be provided in the case where the substrate 200 has four pad portions PD1, PD2, PD3, and PD4 as illustrated in fig. 14.
The structure of the detection units 300, 350 according to the embodiment is not limited thereto. Although the detection support 310, which is shown as the detection unit 300, 350, is provided on the stage 140 in the drawings, the detection unit 300, 350 may be provided as a separate device according to circumstances. For example, the detection units 300, 350 may also be provided on separate supports within the chamber 120.
In addition, after the process of aligning the light emitting elements, the temperature inside the chamber 120 may be brought to 100 ℃ or more to dry the light emitting element ink. In the above-described drying process, an electric signal is continuously applied from the sensing units 300, 350 to the pad portions PD1, PD2 of the substrate 200, but a high temperature may be generated due to contact resistance between the sensing units 300, 350 and the pad portions PD1, PD2 of the substrate 200, so that burn marks may be induced.
In an embodiment, a cooling unit 400 may be further included to prevent the temperature of the pad portions PD1, PD2 of the substrate 200 in the element alignment chamber 100 from excessively increasing.
The cooling unit 400 may function to reduce heat generated from the pad portions PD1, PD2 of the substrate 200, and the cooling unit 400 may include a cooling supply portion 410 for supplying and recovering cooling water (PCW; process cooling water) and cooling water passages 420, 430 through which the cooling water moves.
The cooling supply part 410 may be disposed outside the chamber 120. As an example, the cooling supply part 410 may be disposed at a lower side of the chamber 120, but is not limited thereto, and may be disposed at any position outside the chamber 120. The cooling supply unit 410 may supply cooling water to the cooling water passages 420 and 430 and recover the cooling water, and may include a pump (pump), for example. In some embodiments, a coolant other than cooling water may be used, and is not particularly limited as long as it is in a liquid form.
The cooling water passages 420, 430 may extend from the cooling supply part 410 and be disposed on an upper surface of the stage 140. Specifically, the cooling water passages 420 and 430 may be inserted into the chamber 120 through a chamber hole PH2 formed at one side of the chamber 120 and extend to the upper surface of the stage 140 through a stage hole PH1 formed at one side of the stage 140. In addition, the cooling water passages 420 and 430 may pass through the upper surface of the stage 140 and pass through the stage 140 through a stage hole PH1 formed at the other side of the stage 140, and be connected again to the cooling supply part 410 through a chamber hole PH2 formed at the other side of the chamber 120.
The cooling water passages 420 and 430 may be provided in at least one, and in one embodiment, may include a first cooling water passage 420 and a second cooling water passage 430. The first cooling water passage 420 may be inserted into the chamber 120 through a chamber hole PH2 formed at one side of the chamber 120, extend in the third direction D3 through a stage hole PH1 formed at one side of the stage 140, and extend in the second direction D2 along the upper surface of the stage 140. In addition, the first cooling water passage 420 may extend in the third direction D3 through a stage hole PH1 formed at the other side of the stage 140 and extend to the outside of the chamber 120 through a chamber hole PH2 to be connected to the cooling supply part 410. The second cooling water passage 430 is inserted into the chamber 120 through a chamber hole PH2 formed at the other side of the chamber 120, extends in the third direction D3 through a stage hole PH1 formed at the other side of the stage 140, and extends in the second direction D2 along the upper surface of the stage 140. In addition, the second cooling water passage 430 may extend in the third direction D3 through a stage hole PH1 formed at the other side of the stage 140 and extend to the outside of the chamber 120 through a chamber hole PH2 to be connected to the cooling supply part 410.
The cooling water of the cooling unit 400 is supplied from the cooling supply portion 410 to the first cooling water passage 420 and the second cooling water passage 430. Also, the cooling water supplied to the first and second cooling water passages 420 and 430 passes through the stage 140 in the chamber 120 along the first and second cooling water passages 420 and 430, and is recovered to the cooling supply part 410.
Referring to fig. 7 and 10, in an embodiment, the cooling water passages 420, 430 are disposed between the substrate 200 and the stage 140, and may be in contact with the lower surface of the substrate 200 and the upper surface of the stage 140. The cooling water channels 420, 430 may be overlapped with the pad parts PD1, PD2 provided in the non-effective area NAA of the substrate 200 and with the detection units 300, 350.
Specifically, the first cooling water channel 420 may overlap the first pad part PD1 disposed in the non-effective region NAA of the substrate 200 and extend in parallel along the extending direction (i.e., the second direction D2) of the first pad part PD 1. The width of the first cooling water channel 420 may be greater than or equal to the width of the first pad portion PD1 to effectively reduce the temperature of the first pad portion PD 1. The width of the first cooling water channel 420 is not limited thereto, and the width of the first cooling water channel 420 may also be smaller than the width of the first pad portion PD1 according to circumstances.
As shown in fig. 10, in the case where the width of the first cooling water channel 420 is greater than the width of the first pad portion PD1, the first pad portion PD1 may also completely overlap the first cooling water channel 420. In some embodiments, as shown in fig. 11, the first cooling water channel 420 may also only partially overlap with the first pad part PD1 of the substrate 200. In addition, as shown in fig. 12, in another embodiment, when the width of the first cooling water channel 420 is the same as the width of the first pad portion PD1, the first pad portion PD1 and the first cooling water channel 420 may also be completely overlapped. However, not limited thereto, even if the width of the first cooling water channel 420 is the same as the width of the first pad portion PD1, the first pad portion PD1 and the first cooling water channel 420 may only partially overlap.
Further, the second cooling water channel 430 may overlap the second pad part PD2 disposed in the non-effective area NAA of the substrate 200 and extend in parallel along the extending direction (i.e., the second direction D2) of the second pad part PD2. The width of the second cooling water passage 430 may be greater than or equal to the width of the second pad portion PD2 to effectively reduce the temperature of the second pad portion PD2. The width of the second cooling water passage 430 is not limited thereto, and may be smaller than the width of the second pad portion PD1 according to circumstances.
As shown in fig. 10, when the width of the second cooling water passage 430 is greater than the width of the second pad portion PD2, the second pad portion PD2 may also completely overlap the second cooling water passage 430. In some embodiments, as shown in fig. 11, the second cooling water passage 430 may also only partially overlap the second pad portion PD2 of the substrate 200. In addition, as shown in fig. 12, in another embodiment, when the width of the second cooling water channel 430 is the same as the width of the second pad portion PD2, the second pad portion PD2 and the second cooling water channel 430 may also completely overlap. However, not limited thereto, even if the width of the second cooling water passage 430 is the same as the width of the second pad portion PD2, the second pad portion PD2 and the second cooling water passage 430 may only partially overlap.
In an embodiment, the cooling water channels 420, 430 may be disposed adjacent to a plurality of proximity pins 160 disposed on the upper surface of the stage 140. Specifically, as shown in fig. 7, one side and the other side of the base plate 200 may be in contact with and supported by the proximity pins 160 respectively disposed at the outermost sides. Since the pad portions PD1, PD2 of the substrate 200 are disposed at the edge of the substrate 200, the pad portions PD1, PD2 may be disposed adjacent to the proximity pins 160 disposed at the outermost side. Therefore, the cooling water passages 420, 430 for reducing the temperature of the pad portions PD1, PD2 of the substrate 200 may be disposed adjacent to the proximity pins 160 disposed at the outermost side. The cooling water passages 420, 430 may be disposed between the proximity pins 160 and may be spaced apart from the proximity pins 160 by a predetermined distance, but is not limited thereto, and they may contact each other.
Referring to fig. 13, the substrate 200 may include first and second pad parts PD1 and PD2 disposed at edges adjacent to a long side extending in the first direction D1 in the non-effective area NAA. In order to reduce the temperature of the first and second pad portions PD1 and PD2, the first and second cooling water channels 420 and 430 may overlap the first and second pad portions PD1 and PD2 and extend in the first direction D1. In addition, as shown in fig. 14, the substrate 200 may also include first, second, third and fourth pad parts PD1, PD2, PD3 and PD4 respectively disposed at edges adjacent to four sides of the non-effective area NAA. In this case, the cooling unit 400 is provided with one first cooling water passage 420, and the first cooling water passage 420 may have a rectangular planar shape to entirely overlap the first to fourth pad portions PD1 to PD4.
Fig. 15 and 16 are side views showing an element alignment chamber according to another embodiment.
In the above-described embodiment of fig. 8, the cooling supply part 410 is disposed below the chamber 120, and the cooling water passages 420, 430 extend below the chamber 120 through the chamber hole PH2 formed at the lower surface of the chamber 120 to be connected to the cooling supply part 410. The embodiment of fig. 15 differs in that: the cooling supply part 410 is disposed above the chamber 120, and the cooling water passage 420 extends along the side and upper surfaces of the chamber 120 to be connected to the cooling supply part 410.
Referring to fig. 15, the cooling supply part 410 may be disposed above the chamber 120. The chamber holes PH2 may be respectively disposed at both sides of the chamber 120 opposite to each other. The first cooling water passage 420 may extend from one side of the cooling supply part 410, along the upper and side surfaces of the chamber 120 to the stage 140 through the chamber hole PH 2. In addition, the first cooling water passage 420 may pass through the stage 140 and extend along the other side and the upper surface of the chamber 120 through the chamber hole PH2 of the other side of the chamber 120 to be connected to the cooling supply part 410.
In the element alignment chamber 100 having the above-described structure, as the length of the first cooling water passage 420 provided outside the chamber 120 increases, the cooling water in the first cooling water passage 420 can be effectively cooled. Therefore, the cooling efficiency of the pad portions PD1, PD2 of the substrate 200 disposed in the element alignment chamber 100 can be improved.
Referring to fig. 16, the cooling unit 400 may include a plurality of cooling supplies 410, 450. The cooling supply parts 410 and 450 may include a first cooling supply part 410 disposed at one side below the chamber 120 and a second cooling supply part 450 disposed at the other side. The first cooling water passage 420 may be connected to the first cooling supply part 410, and the second cooling water passage 430 may be connected to the second cooling supply part 450.
In the present embodiment, the first cooling water passage 420 and the second cooling water passage 430 extend into the chamber 120 through a chamber hole PH2 provided in a lower surface of the chamber 120, and protrude from an upper surface of the stage 140 through a stage hole PH1 of the stage 140, respectively. Unlike the previous embodiment, the first and second cooling water passages 420 and 430 are in contact with the substrate 200 at the upper surface of the stage 140, but do not extend in the second direction D2. That is, in the foregoing embodiment, the first cooling water channel 420 and the second cooling water channel 430 are overlapped with the pad portions PD1, PD2 of the substrate 200 in a line shape, and unlike this, in the present embodiment, the first cooling water channel 420 and the second cooling water channel 430 may be overlapped with and point-contacted with the pad portions PD1, PD2 of the substrate 200. Therefore, in the present embodiment, a region in which a large amount of heat is generated in each of the pad portions PD1, PD2 of the substrate 200 can be selectively cooled.
Hereinafter, a method of manufacturing a display device using the element alignment chamber 100 will be described.
Fig. 17 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Fig. 18 is a cross-sectional view illustrating a part of a process of manufacturing a display device according to an embodiment. Fig. 19 is a side view illustrating an element alignment chamber according to an embodiment. Fig. 20 is a cross-sectional view illustrating a part of a process of manufacturing a display device according to an embodiment. Fig. 21 is a side view illustrating an element alignment chamber according to an embodiment. Fig. 22 to 24 are sectional views illustrating a part of a process of manufacturing a display device according to an embodiment.
Referring to fig. 17, a method of manufacturing a display device according to an embodiment may include the steps of: preparing a substrate (S100); placing a substrate on a stage (S200); operating the cooling unit and bringing the detecting unit into contact with the pad portion of the substrate and applying an electric field (S300); applying a light emitting element ink on a substrate and aligning the light emitting elements (S400); and forming an insulating layer and an electrode on the substrate (S500). Hereinafter, a method of manufacturing the display device will be described with reference to fig. 17.
Referring to fig. 18, a substrate 200 is prepared (S100). Although not shown in the drawings, the substrate 200 may include a plurality of sub-pixels SP including circuit elements formed of a plurality of conductive layers and a plurality of insulating layers. Hereinafter, for convenience of description, the substrate 200 including these elements will be described.
Then, a plurality of first banks BNL1 spaced apart from each other are formed on the substrate 200. The first bank BNL1 may have a shape protruding from the upper surface of the substrate 200. This is explained above.
Then, the first alignment electrode layer 21 'and the second electrode layer 22' are formed on the first bank BNL1. The first alignment electrode layer 21 'and the second electrode layer 22' extend in the second direction D2. In the manufacturing process of the display device 10, the first alignment electrode layer 21 'and the second electrode layer 22' may extend in the second direction D2, and may also be disposed in other sub-pixels PXn. After the light emitting element 30 is disposed in a subsequent process, a breaking process of separating the first alignment electrode layer 21 'and the second electrode layer 22' in the cut region CBA of each sub-pixel PXn may be performed, thereby forming the first alignment electrode 21 and the second alignment electrode 22, respectively. Then, a first insulating layer PAS1 is formed on the substrate 200 including the first and second alignment electrodes 21 and 22.
Next, referring to fig. 19, the substrate 200 is transferred and mounted on the stage 140 of the component alignment chamber 100 by the robot arm (S200). Specifically, when the substrate 200 is aligned with the stage 140, the lift pins ("170" in fig. 9) rise above the upper surface of the stage 140 so that the substrate 200 is placed on the lift pins. Next, the robot arm releases the substrate 200, and the lift pins are lowered, thereby placing the substrate 200 on the proximity pins 160.
Next, referring to fig. 20, the cooling unit 400 is operated to supply cooling water to the cooling water passages 420, 430, thereby circulating the cooling water. In addition, the probing units 300 and 350 respectively disposed on the stage 140 move to both sides of the substrate 200 and bring the probing pads 330 into contact with the pad portions PD1 and PD2 of the substrate 200, respectively. Next, an electric signal is supplied from the probe pad 330 to the pad portions PD1, PD2 of the substrate 200, and a current flows through the first alignment electrode 21 and the second alignment electrode 22 of the substrate 200. When a current flows through the first and second alignment electrodes 21 and 22, an electric Field, i.e., an electric Field (E-Field), may be generated between the first and second alignment electrodes 21 and 22 (S300). In an exemplary embodiment, the electrical signal may be an alternating voltage, and the alternating voltage may have a voltage of ± (10-50) V and a frequency of 10kHz to 1 MHz. When an alternating voltage is applied to the first and second alignment electrodes 21 and 22, an electric field may be generated between the first and second alignment electrodes 21 and 22.
In one embodiment, the temperature increase in the pad portions PD1, PD2 of the substrate 200 may be mitigated by using the cooling unit 400, thereby expanding the voltage and frequency ranges of the above-described electrical signals.
Next, referring to fig. 21 to 23, the light emitting elements are aligned by coating light emitting element ink on the substrate 200 (S400). Specifically, the light emitting element ink 90 in which the light emitting elements 30 are dispersed is ejected onto the substrate 200 by an inkjet printing method. The light emitting element 30 may be oriented in a direction by an electric field, and may be disposed on the substrate 200. In some embodiments, the dielectrophoretic force is transferred by an electric field generated above the substrate 200, so that the light-emitting element 30 can be disposed between the first alignment electrode 21 and the second alignment electrode 22.
In the light emitting element ink 90, the orientation direction of the light emitting elements 30 having a shape extending in one direction may be changed according to the direction of the electric field. According to an embodiment, the light emitting element 30 may be aligned such that a direction in which it extends is directed toward the direction of the electric field. When an electric field parallel to the upper surface of the substrate 200 is generated on the substrate 200, the light emitting elements 30 may be aligned such that the extending direction of the light emitting elements 30 is parallel to the substrate 200, and thus the light emitting elements 30 may be disposed between the first alignment electrode 21 and the second alignment electrode 22.
Next, the solvent 91 of the light emitting element ink 90 ejected onto the substrate 200 is removed. In the process of removing the solvent 91, heat or infrared rays may be irradiated onto the substrate 200. By removing the solvent 91 from the light emitting element ink 90 ejected onto the substrate 200, the movement of the light emitting element 30 can be prevented, and the light emitting element 30 can be placed on the first alignment electrode 21 and the second alignment electrode 22.
In addition, in the present embodiment, the electric field is first generated on the substrate 200 by the detecting units 300, 350 and then the light emitting element ink 90 is ejected, but is not limited thereto, and the electric field may be generated after the light emitting element ink 90 is ejected, or both operations may be performed simultaneously.
Next, referring to fig. 24, the second insulating layer PAS2 is formed in a pattern shape on at least a portion of the light emitting element 30, and opening portions OP exposing the first alignment electrode 21 and the second alignment electrode 22, respectively, are formed in the first insulating layer PAS1. Next, the first contact electrode CNE1 connected to the first alignment electrode 21 is formed on the first insulating layer PAS1 and the second insulating layer PAS2, and the third insulating layer PAS3 is formed on the substrate 200. Further, a second contact electrode CNE2 connected to the second alignment electrode 22 is formed on the first insulating layer PAS1 and the second insulating layer PAS2, and a fourth insulating layer PAS4 is formed on the substrate 200, thereby manufacturing a display device.
While the embodiments of the present invention have been described with reference to the drawings, it will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments described above are therefore to be considered in all respects as illustrative and not restrictive.
Claims (20)
1. A component alignment chamber, comprising:
a chamber;
a stage disposed within the chamber;
a substrate disposed on the stage and including an active area in which a light emitting element is aligned and a non-active area surrounding the active area and including a pad part;
a detection unit disposed on the stage and applying an alignment signal to the pad part of the substrate; and
a cooling unit including a cooling water passage overlapping the pad portion between the pad portion and the stage of the substrate, and a cooling supply portion provided outside the chamber and supplying cooling water to the cooling water passage.
2. The component alignment chamber of claim 1,
the cooling water passage extends in parallel with an extending direction of the pad portion of the substrate.
3. The component alignment chamber of claim 2,
at least a portion of the cooling water passage overlaps with the pad portion of the substrate.
4. The component alignment chamber of claim 2,
the width of the cooling water channel is greater than or equal to the width of the pad portion of the substrate.
5. The component alignment chamber of claim 2,
the pad portion of the substrate completely overlaps the cooling water passage.
6. The component alignment chamber of claim 1,
the detection unit includes: a detection support disposed on the stage; and a probe pad provided at one end of the probe support, an
The cooling water passage extends in parallel with an extending direction of the probe pad.
7. The component alignment chamber of claim 6,
at least a portion of the cooling water passage overlaps the probe pad.
8. The component alignment chamber of claim 1,
the stage includes a plurality of proximity pins on an upper surface thereof for supporting the substrate, an
The cooling water passage is provided between the proximity pins.
9. The component alignment chamber of claim 1,
the chamber includes a plurality of chamber holes through which the cooling water passages pass.
10. The component alignment chamber of claim 9,
the stage includes a plurality of stage holes through which the cooling water passage passes.
11. The component alignment chamber of claim 10,
the cooling supply portion is disposed below the chamber, an
The plurality of chamber holes are provided on a lower surface of the chamber and overlap the plurality of stage holes.
12. The component alignment chamber of claim 10,
the cooling supply portion includes: a first cooling supply and a second cooling supply; and a first cooling water passage connected to the first cooling supply part and a second cooling water passage connected to the second cooling supply part, and
the first cooling water passage and the second cooling water passage each pass through the chamber hole and the stage hole and are in point contact with the pad portion of the substrate.
13. The component alignment chamber of claim 10,
the cooling supply portion is disposed above the chamber, and the plurality of chamber holes are disposed at both side surfaces of the chamber.
14. The component alignment chamber of claim 10,
the cooling unit includes: a first cooling water passage connected to one side of the cooling supply part; and a second cooling water passage connected to the other side of the cooling supply part, an
The first cooling water passage and the second cooling water passage each extend to a side surface and an upper surface of the chamber through the chamber hole.
15. A method of manufacturing a display device, comprising:
preparing a substrate;
a step of preparing a component alignment chamber, the component alignment chamber comprising: a chamber; a stage disposed within the chamber; a substrate to be disposed on the stage and including an active area in which a light emitting element is aligned and a non-active area surrounding the active area and including a pad part; a detection unit disposed on the stage and applying an alignment signal to the pad part of the substrate; and a cooling unit including a cooling water passage overlapping the pad portion between the pad portion and the stage of the substrate and a cooling supply portion provided outside the chamber and supplying cooling water to the cooling water passage;
a step of placing the substrate on the stage of the component alignment chamber;
a step of operating the cooling unit to bring the detecting unit into contact with the pad portion of the substrate and apply an electric signal;
a step of coating a light emitting element ink on the substrate and aligning the light emitting elements; and
a step of forming a plurality of insulating layers and a plurality of electrodes on the substrate.
16. The method of manufacturing a display device according to claim 15,
the stage includes a plurality of proximity pins, wherein the substrate is supported by the plurality of proximity pins.
17. The method of manufacturing a display device according to claim 15,
circulating cooling water supplied from the cooling supply part in the cooling water passage by operation of the cooling unit to cool the pad part of the substrate.
18. The method of manufacturing a display device according to claim 15, wherein the step of preparing the substrate comprises:
forming a first bank and a second bank which are juxtaposed to each other on the substrate, forming a first alignment electrode overlapping the first bank and a second alignment electrode overlapping the second bank, and forming a first insulating layer on the first alignment electrode and the second alignment electrode.
19. The method of manufacturing a display device according to claim 18,
the probing unit includes a probing support and a probing pad disposed at one end of the probing support, an
An electric field is generated between the first and second alignment electrodes by contacting a probe pad to the pad portion of the substrate and applying an electric signal.
20. The method of manufacturing a display device according to claim 19,
in the step of aligning the light emitting elements, the light emitting elements are aligned by an electric field generated between the first alignment electrode and the second alignment electrode, and
after the step of aligning the light emitting elements, the solvent of the light emitting element ink is dried.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020200082741A KR20220005666A (en) | 2020-07-06 | 2020-07-06 | Element alignment chamber and method for manufacturing display device using the same. |
| KR10-2020-0082741 | 2020-07-06 | ||
| PCT/KR2021/005555 WO2022010080A1 (en) | 2020-07-06 | 2021-05-03 | Element alignment chamber and method for manufacturing display device by using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115769358A true CN115769358A (en) | 2023-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180047560.0A Pending CN115769358A (en) | 2020-07-06 | 2021-05-03 | Element alignment chamber and method of manufacturing display device using the same |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR20220005666A (en) |
| CN (1) | CN115769358A (en) |
| WO (1) | WO2022010080A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200409072Y1 (en) * | 2005-11-15 | 2006-02-20 | 노기래 | cooling apparatus of suscepter for semiconductor and liquid circuit displayLCD panel manufacturing device |
| US8222574B2 (en) * | 2007-01-15 | 2012-07-17 | Applied Materials, Inc. | Temperature measurement and control of wafer support in thermal processing chamber |
| JP2016025205A (en) * | 2014-07-18 | 2016-02-08 | スタンレー電気株式会社 | Method of manufacturing semiconductor optical device |
| KR102517393B1 (en) * | 2018-04-18 | 2023-04-03 | 삼성디스플레이 주식회사 | Display device and method for fabricating the same |
| KR102559818B1 (en) * | 2018-09-21 | 2023-07-26 | 삼성디스플레이 주식회사 | Method for arranging light emitting device and method for manufacturing display device including the same |
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2020
- 2020-07-06 KR KR1020200082741A patent/KR20220005666A/en active Search and Examination
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2021
- 2021-05-03 WO PCT/KR2021/005555 patent/WO2022010080A1/en active Application Filing
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| KR20220005666A (en) | 2022-01-14 |
| WO2022010080A1 (en) | 2022-01-13 |
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