CN115765787A - Method for rapidly capturing low-signal-to-noise-ratio large-dynamic short message signal - Google Patents
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Abstract
A method for quickly capturing the dynamic short message signal with low S/N ratio includes such steps as down-converting the sampled IF signal to baseband, accumulating the baseband signals, decreasing the speed of baseband signals, sequentially storing the data in buffer area, writing local pseudo code in the buffer area with same width, and correcting the speed of local pseudo code according to the central frequency point of each frequency interval. After the data storage is finished, reading is started, the read data is multiplied by the code pieces correspondingly, parallel de-spread and orthogonal frequency conversion are realized, and the data are divided into different frequency intervals; performing ping-pong cache on the partitioned data by using two storage areas, and then performing high-speed FFT operation; after all code phases are searched in the current frequency interval, the frequency interval is converted to continue searching; and if all the frequency intervals are searched, judging whether the acquisition is successful or not. The occupied storage space of the invention is reduced to 1/98 of that of the traditional method, the number of parallel correlation paths is reduced to 1/6, the number of FFT cores used is reduced to 1/4 of that of the traditional method, and the capture time is controlled to be 40ms.
Description
Technical Field
The invention belongs to the field of communication, and relates to a method for quickly capturing a low-signal-to-noise-ratio large-dynamic short message signal.
Background
The direct sequence spread spectrum communication system has the advantages of strong anti-interference capability, low intercepted probability, strong anti-multipath capability, code division multiple access and the like, and is more and more widely applied to military and civil communication. The system is widely applied in the field of aerospace measurement and control, and effectively combines remote control and remote measurement and distance and speed measurement. In order to further improve the concealment of the signals, reduce the snoopability of the signals and improve the number of service users, a short message burst spread spectrum communication mode is adopted, and a receiving end is required to complete the acquisition, tracking, demodulation, decoding and information analysis of the spread spectrum signals in a very short time.
In the traditional method for capturing spread spectrum signals, to complete the rapid capture of short message signals, large device resources are required, and the method cannot adapt to the satellite environment with limited device resources. Some of the publications available at present relate to a method for capturing a burst spread spectrum signal with a low snr, for example, "FFT-based burst spread spectrum signal compatible fast capture algorithm" (chen sub-bin) proposes an improved FFT-based burst spread spectrum signal compatible fast capture algorithm, which can achieve fast capture of a burst spread spectrum signal, but the algorithm structure is complex, uses a plurality of FFT operation units, occupies a large amount of device resources, and is not suitable for an environment with limited device resources. A low-complexity quick synchronization method (Wang TianXiong) under burst spread spectrum communication utilizes differential accumulation to quickly capture spread spectrum signals, and is a capture algorithm based on a matched filter.
Disclosure of Invention
The technology of the invention solves the problems that: the method overcomes the defects of the prior art, provides a rapid capturing method of a low signal-to-noise ratio large dynamic short message signal, reduces the occupied storage space to 1/98 of the traditional method, reduces the number of parallel correlation paths to 1/6, reduces the number of FFT cores to 1/4 of the traditional method, and controls the capturing time to be 40ms.
The technical solution of the invention is as follows:
a method for rapidly capturing a low signal-to-noise ratio large dynamic short message signal comprises the following steps:
(1) Carrying out orthogonal down-conversion on the AD sampled data, and moving the data to a baseband from an intermediate frequency;
(2) Accumulating and reducing the speed of the data after down-conversion;
(3) Delaying the accumulated data with reduced speed for m x k times, generating m x k data, sequentially storing the m x k data into the same address of a cache region RAM1, writing one data in one clock cycle, reading the m x k data corresponding to one address in the RAM1 at one time during reading, namely converting the accumulated data with reduced speed from serial to parallel;
(4) Dividing frequency intervals according to the Doppler range and the signal-to-noise ratio, and correcting the local pseudo code rate according to the central frequency point of each frequency interval;
(5) Making the initial values of i and j equal to 1;
(6) Reading m x k data in one address of the RAM1 and m x k chips in a corresponding address of the RAM2 in each clock cycle at the ith code phase, multiplying the data by the chips correspondingly to realize parallel despreading, dividing m x k despreading results obtained in the same clock cycle into k groups, and performing parallel accumulation on m despreading results in each group to obtain k groups of accumulated results;
(7) Carrying out orthogonal frequency conversion on the de-spread and accumulated data by using a central frequency point of a jth frequency interval, and dividing intervals for the accumulated results after the orthogonal frequency conversion of all clock periods under the current code phase;
(8) Performing ping-pong cache on the data after the partition by using two storage areas, wherein one of the two storage areas is in a writing state, and the other storage area is in a reading state;
(9) After data storage is finished, calling a pipelined FFT core to perform FFT operation, and when the phase of the local pseudo code is aligned with the data after AD sampling in the step (1), the peak position of the FFT frequency spectrum is Doppler frequency offset;
(10) Judging whether I is equal to I, wherein I is the total number of the code phases, if not, sliding one code phase, namely adding 1 to the value of I, and executing the steps (6) - (9), wherein the sliding of the code phases is realized by changing the initial reading address of the RAM 2; if yes, entering the step (11);
(11) Judging whether J is equal to J, wherein J is the total number of frequency intervals, if not, adding 1 to the value of J, and enabling i =1, and executing the steps (6) - (10); if yes, entering step (12);
(12) If the peak value of the FFT frequency spectrum is larger than a preset threshold, judging that the acquisition is successful, and starting a tracking module; and (4) if the peak value of the FFT frequency spectrum is smaller than a preset threshold, judging that the acquisition fails, and returning to the step (1) to restart the acquisition.
Preferably, in the step (2), assuming that the global clock is clk, the accumulated and slowed down data rate is clk/N, and N is the accumulated point number.
Preferably, in the step (3), the depth D of the buffer RAM1 is set e Is composed of
The width is m x k, N is the number of accumulated points, and R is the accumulated data rate.
Preferably, in the step (4), the radio frequency is assumed to be F s Pseudo code rate of f c Doppler frequency range of-f d ～f d The accumulation time of the acquisition operation is 1/R, and the number J of the minimum frequency intervals is
R is the accumulated data rate; assuming that the center frequency point of the frequency interval is f q Then the modified pseudo code rate is
Preferably, the sampling rate of the local pseudo code is the same as the accumulated reduced data rate, clk/N.
Preferably, the pseudo code storage space has a depth of
Wherein f is c At the pseudo code rate, H is the pseudo code period.
Preferably, in the step (8), the storage depth of one storage area is D/k, and D is the number of FFT operation points.
Preferably, D = R a /R，R a The data rate after despreading and accumulation in step (5) and R is the accumulated data rate in step (3).
Preferably, in the step (9), a pipelined FFT core is called to perform the high-speed FFT operation using k times of the global clock.
Preferably, the capture time = data buffer time + capture operation time;
wherein,
r is the accumulated data rate, f c Is the pseudo code rate, H is the pseudo code period;
if the sliding precision of the pseudo code phase is 1/t chips during the capturing, the time of one round of capturing operation in each frequency interval is
The acquisition time required for J frequency intervals of serial search is
In each clock cycle, D is the number of FFT operation points.
The invention has the beneficial effects that:
the invention provides a novel high-efficiency capturing framework based on multi-level data cache, and a method for rapidly capturing a low signal-to-noise ratio large dynamic short message signal is realized through level-by-level cache. Dividing frequency intervals according to the requirements of Doppler dynamic and signal-to-noise ratio, and correcting the pseudo code rate by using the central frequency point of each interval to realize the quick capture of the short message signal with low signal-to-noise ratio and large dynamic. The acquisition architecture is flexible, and the acquisition of short message signals under different signal-to-noise ratios and Doppler frequency offsets can be adapted by changing parameters. Under the same requirements of signal-to-noise ratio, doppler dynamics and acquisition time, by adopting the method provided by the invention, the storage space occupied by the algorithm is reduced to 1/98 of that of the traditional method, the number of parallel correlation paths is reduced to 1/6, the number of FFT cores used is reduced to 1/4 of that of the traditional method, and the acquisition time is controlled to be 40ms.
Drawings
FIG. 1 is a capture flow diagram;
FIG. 2 is a flow chart of acquisition control;
fig. 3 is a flowchart of a conventional acquisition method.
Detailed Description
As shown in FIG. 1, on the basis of partial correlation FFT algorithm, zero intermediate frequency signals are accumulated and stored after being reduced in speed, and serial sampling points are converted into parallel processing, so that device resources can be saved while rapid capture is ensured; in order to ensure that the sliding of the local pseudo code relative to a received signal in one accumulation time of capture operation under the condition of low signal-to-noise ratio and large Doppler frequency offset does not exceed half a chip, the Doppler is divided into a plurality of intervals, and the rate of the local pseudo code is corrected by using a central frequency point of each interval; in order to match the data throughput of the RAM3 and save FFT computation resources, a high-power clock is used to perform FFT computation, and the doppler position and code phase are quickly obtained.
Example (b):
(1) Down conversion: and carrying out quadrature down-conversion on the AD sampled data, and moving the data from the intermediate frequency to a baseband.
(2) Accumulating and reducing the speed: and accumulating the signals after the down conversion, wherein the accumulation aims to reduce the subsequent data storage amount, namely the size of the storage resource occupied by the RAM1 is reduced. The number of accumulation points N needs to be determined according to the spreading code rate of the input signal, and in order to reduce signal loss, the accumulated data rate needs to be 3-4 times of the pseudo code rate. Assuming the global clock is clk, the accumulated data rate is clk/N.
(3) Data storage: and sequentially storing the accumulated data subjected to speed reduction into a cache region, wherein the data cache region is an RAM1 by comparing with a figure 1. When the data is written in the cache region, delaying the data after the speed reduction by m × k times, generating m × k data and storing the m × k data into the same address of the RAM1, and writing one data in one clock period. When reading, m × k data corresponding to a certain address in the RAM1 are read out at one time, which is equivalent to converting the accumulated speed-reduced data from serial to parallel processing.
Width m x k and depth D of buffer e And determining according to the acquisition time, the Doppler frequency offset and the carrier-to-noise ratio requirement of the received signal. To obtain specific values of the width and depth of the buffer, first, it is necessary to determine an accumulated data rate R of capture operation, assuming that a carrier-to-noise ratio of a received signal is CNR (the carrier-to-noise ratio corresponds to a received signal level), a signal-to-noise ratio after the capture operation is SNR, and R =10 can be obtained by calculation (CNR-SNR) . In general, when the SNR after the acquisition operation is 20dB or more, the acquisition probability can be 99%. Then the depth of the data buffer D e Is composed of
(4) Local pseudo code generation and storage: under the condition of low signal-to-noise ratio, a longer accumulation time is needed to reach a certain capture probability; therefore, when the doppler frequency offset is large, under the action of code doppler, if the local pseudo code rate participating in the correlation operation is the nominal code rate, the relative sliding between the local pseudo code and the received signal in the acquisition operation accumulation time exceeds half a chip, resulting in acquisition failure. Therefore, before the local pseudo code is generated, different frequency intervals need to be divided according to the Doppler range and the signal-to-noise ratio, and the local pseudo code rate needs to be corrected according to the central frequency point of each frequency interval.
Suppose the RF frequency is F s Pseudo code rate of f c Doppler frequency range of-f d ～f d The accumulation time of the capturing operation is 1/R, the code phase slip in the capturing accumulation time is less than half a chip, and the number J of minimum frequency intervals is
Assuming that the center frequency point of the frequency interval is f q Then the modified pseudo code rate is
The Doppler frequency range which can be captured by the method is not limited to-100 kHz, and can be expanded according to actual needs.
Referring to fig. 1, the local pseudo code is generated and then stored in the buffer RAM2, and the width of the storage interval is the same as that of the storage data. Namely, the local pseudo code with the sampling rate of clk/N is delayed by m × k times, m × k chips are generated and stored in the same address of the RAM2, and one chip is written in one clock period. When the pseudo code is read, m x k chips corresponding to a certain address in the RAM2 are read out at one time, which is equivalent to converting the local pseudo code from serial to parallel processing.
The local code phase is required to slide during capturing operation, the sliding code phase is realized by changing the initial reading address of the RAM2, compared with the stored data, the local pseudo code needs to store more data amount corresponding to one code period, and the sampling rate of the local pseudo code is the same as the data rate after accumulating and reducing the speed, namely clk/N. Suppose the pseudo code rate is f c If the period of the pseudo code is H, the depth of the pseudo code storage space is
(5) Parallel despreading and parallel accumulation: after signal de-spreading, accumulation is needed again to reduce the number of FFT operation points. In the invention, because the signal-to-noise ratio of the received signal is low, the frequency interval is divided during capturing, and different frequency intervals are searched in series in order to save device resources. In order to guarantee fast acquisition within 40ms, parallel despreading of m x k data is required, and re-accumulation is also performed in parallel. Parallel accumulated data rate R a Determined by the doppler shift, the data rate is typically required to be 3-4 times the maximum doppler shift. The accumulated number m can be obtained by calculation,
as can be seen from steps (3) and (4) and fig. 1, after the data and pseudo code storage is completed, m × k data and chips in one address are read out in one clock cycle, the data and the chips are multiplied correspondingly to implement parallel despreading, then m despreading results in the same clock cycle are accumulated in parallel, and k accumulation results can be obtained in each clock cycle.
(6) Dividing a frequency interval: and (4) according to the frequency interval number obtained in the step (4), carrying out orthogonal frequency conversion on the despread and accumulated signals by using a central frequency point of the jth interval, wherein the central frequency point corresponds to the pseudo code rate correction quantity in the step (4) one by one. In order to save resources, the frequency interval division is performed in series, that is, after the code phase corresponding to one frequency interval is searched, the next frequency interval is replaced. The initial value of j is 1.
(7) And (3) data storage after partition: after the frequency interval is divided, k sampling points exist in one clock cycle, and the k sampling points need to be simultaneously written into an address of the data cache region RAM3 after being juxtaposed. Because the subsequent FFT operation occupies larger device resources, in order to realize the multiplexing of FFT operation resources, only one FFT module is used for completing all operations, when data is read, a k-time clock of a global clock is used, and the subsequent FFT operation also uses the high-time clock. Because a buffer RAM3 is arranged between the two clock domains for data isolation, the requirement of cross-clock domain processing is met.
In order to save capture time, two storage areas are used for ping-pong buffer of partitioned data, one is in a write state, and the other is in a read state. One address of the storage area stores k accumulation results, the storage depth is D/k, D is the number of FFT operation points, the FFT operation points are determined by the signal-to-noise ratio and the Doppler frequency offset, and the FFT operation points can be determined by the parameter R in the step (3) and the parameter R in the step (5) a Calculated to yield D = R a /R。
(8) FFT operation: and after the data storage is finished, calling a pipelined FFT core, and using a k-time clock of the global clock to carry out operation so as to realize FFT multiplexing. When the phase of the local pseudo code is aligned with the data after AD sampling, the peak position of the FFT frequency spectrum is the Doppler frequency offset.
(9) And (3) judging a capture result: the acquisition decision module controls the whole acquisition process, and the acquisition control flow chart is shown in fig. 2. After the acquisition is started, respectively caching data and the local pseudo code according to the step (3) and the step (4), performing parallel de-spreading and accumulation after the caching of the data and the local pseudo code is finished, then dividing a frequency interval according to the step (6), performing data caching and high-speed FFT (fast Fourier transform) operation according to the step (7) and the step (8), judging whether all frequency intervals are searched or not after all code phases are searched, if not, adding 1 to the value of j, and transforming the frequency intervals to repeat the steps to continuously search all code phases for acquisition; if all frequency intervals are searched, whether the acquisition is successful or not is judged, a dynamic threshold (N times of the average value of each frame of FFT operation result) is set, if the FFT peak value is larger than the threshold, the acquisition is judged to be successful, and a tracking module is started; if the peak value is smaller than the threshold, the capturing is judged to be failed, the capturing module is reset, and the capturing is restarted.
(10) And (3) calculating the capture time: the capture time includes a data buffering time and a capture operation time.
(a) Data buffering time: in the step (3) and the step (4), the pseudo code cache needs one pseudo code period more than the data cache, so the time required by the cache is the pseudo code cache time, and the pseudo code cache time can be obtained through the steps
And (4) calculating.
(b) Capturing the operation time: because two buffer areas are arranged before the FFT operation to perform ping-pong buffer on the data, namely the FFT operation and the data buffer are performed simultaneously, and the high-power clock is used for performing the FFT operation, the FFT operation time is the same as the data buffer time, the FFT operation can be omitted when the capture time is calculated. The Doppler frequency offset is divided into J intervals by steps (5) - (8), each interval is searched in series, and the acquisition time required for one frequency interval is calculated firstly. One clock cycle can output k rates of R a Each frame of FFT operation requires D rates of R a I.e., for D/k clock cycles, which is the time for a pseudo code phase acquisition operation in a frequency interval. Assuming that the sliding accuracy of the pseudo code phase is 1/t chips during acquisition, the time for one round of acquisition operation in each frequency interval is
One clock cycle. The acquisition time required for the frequency bins of the J serial searches is
One clock cycle.
Examples of the parameters are: receiving signal level-130 dBm (corresponding carrier-to-noise ratio CNR is 42 dBHz), doppler frequency offset range is-100 kHz, capture time is within 40ms, pseudo code period H is 1023, and pseudo code rate f c 3.069Mcps, radio frequency F s The frequency is 2GHz, the global clock is 60MHz as an example, and various parameters in the invention are exemplified.
The data rate after the accumulation in the step (2) needs to be set to be 3-4 times of the pseudo code rate, so the accumulation point number N can be set to be 6. When the SNR is more than or equal to 20dB, the capture probability can reach 99%, so the accumulated data rate R of capture operation is less than or equal to 158 bps. The number J of divided frequency intervals is rounded up by the formula in step 4, and may be set to 2 here, i.e. divided into 2 frequency intervals. Data rate R before FFT operation a Needs to be set to be 3-4 times of the maximum Doppler frequency offset, and comprehensively considers the integral multiple relation of the speed and the global clock, R a May be set to 312.5kbps. The number of FFT points D can be determined by R a And R is calculated to be the nth power of 2, so D may be set to 2048 here. The parallel accumulation number m can be rounded off from the formula in step (5), and can be set to 32 here. In acquisition, the code phase sliding precision is half a chip, i.e. t can be 2. Completing serial capture of 2 frequency intervals within 40ms, rounding up the number k of parallel results accumulated in the step (5) by a formula in the step (10), and setting the number k to be 4, wherein the specific capture time is 34.9ms; and the number of paths m × k =128 paths for parallel despreading.
Resource occupation estimation: because the resources of the on-satellite devices are limited, the resources occupied by the algorithm are always concerned, the method effectively reduces the resources occupied by the algorithm while ensuring the rapid capture, and the storage space occupied by the algorithm and the number of the used FFT cores are estimated.
(a) In the step (3), the data cache RAM1 occupies the storage resources with the size
B 1 For summing up the sum of the widths of the IQ data after deceleration, according to engineering experience, B 1 Can be set to 5+5=10bit. In the step (4), the size of the storage resource occupied by the local pseudo code cache RAM2 is
In the step (7), the data cache RAM3 occupies the storage resources with the size
B 2 For the sum of IQ data bit widths, to satisfy capture at low signal-to-noise ratio, B 2 Need to be set as 12+12=24bit.
The memory space occupied by the algorithm is the sum of the RAM1, the RAM2 and the RAM 3. Using the parameters in step 11, the total sum of the memory resources occupied can be 797.839kbit.
(b) By the step (7) and the step (8), because the invention uses the high-power clock to read the data in the RAM3 and perform the FFT operation, the multiplexing of FFT operation resources is realized, and the algorithm only uses 1 FFT core.
(c) Compared with the traditional spread spectrum capturing method, the method occupies resources: in order to capture a spread spectrum signal with large Doppler frequency offset and low signal-to-noise ratio, a frequency interval needs to be divided in a traditional capture method, and a pseudo code rate needs to be corrected according to the divided frequency interval before despreading. In order to shorten the capture time, it is necessary to increase the number of parallel processing paths, and a block diagram of the conventional capture method is shown in fig. 3.
Taking the above parameters as examples, that is, the global clock clk is 60MHz, each sampling point is processed serially under the global clock, the pseudo code period H is 1023, the number of coherent accumulation points Nc is 192, r is 158bps, t is 2 (i.e., the code phase sliding precision is half a chip), the number of divided frequency intervals is 2, the number of fft operation points is 2048, and the time required for serially searching one round of code phase in each frequency interval is 2048
To realize fast acquisition within 40ms, each frequency interval needs to be controlled within 20ms, and 799 paths of code phase parallel search are needed.
799 the time required for the phase data buffering of the way code is
If one FFT core is used for operation, the time required for operation is 799 × 2048=1636352 clock cycles, the total is 27.3ms, and the time does not match the data storage time, so that 4 FFT cores are required for parallel operation.
In order to achieve the same performance index and capture time as the present invention, bit widths of 799 parallel correlation operation IQ data in the conventional capture method are all set to be 12bit, fft points are set to be 2048, two memories are used for ping-pong cache, and occupied memory resources are 2 × 24 × 2048 × 799=78.544mbit.
Under the same performance index and capture time conditions, table 1 shows the comparison of the resources of the FPGA occupied by the spread spectrum signal capture method of the present invention and the conventional spread spectrum signal capture method.
Table 1 comparison of resources occupying FPGA between the present invention and the conventional spread spectrum signal capturing method
| Storage space | Parallel correlation path number | Number of FFT kernels | |
| The invention | 797.839kbit | 128 routes of road | 1 |
| Conventional methods | 78.544Mbit | 799 way | 4 |
Therefore, the method effectively reduces the device resources occupied by the algorithm under the condition of ensuring that the capture time is not changed.
From the above, the method for rapidly capturing the low signal-to-noise ratio large dynamic short message signal of the invention provides a novel efficient capturing framework based on multi-level data cache, and achieves rapid capturing of the low signal-to-noise ratio large dynamic short message signal through level-by-level cache. The acquisition architecture is flexible, the acquisition of short message signals under different signal-to-noise ratios and Doppler frequency offsets can be adapted by changing parameters, and the resources occupied by an acquisition algorithm are effectively reduced while the rapid acquisition is ensured. The method has stable performance and can be widely applied to the field of burst spread spectrum measurement and control.
In the process of developing a certain project, after the method provided by the invention is applied, short message signals with large Doppler dynamics (-100 kHz) and low signal-to-noise ratio (the received carrier-to-noise ratio is less than 42 dBHz) can be captured, and rapid capture can be completed within 40ms.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (10)
1. A method for rapidly capturing a low signal-to-noise ratio large dynamic short message signal is characterized by comprising the following steps:
(1) Carrying out orthogonal down-conversion on the AD sampled data, and moving the data to a baseband from an intermediate frequency;
(2) Accumulating and reducing the speed of the data after the down conversion;
(3) Delaying the accumulated data with reduced speed for m x k times, generating m x k data, sequentially storing the m x k data into the same address of a cache region RAM1, writing one data in one clock cycle, reading the m x k data corresponding to one address in the RAM1 at one time during reading, namely converting the accumulated data with reduced speed from serial to parallel;
(4) Dividing frequency intervals according to the Doppler range and the signal-to-noise ratio, and correcting the local pseudo code rate according to the central frequency point of each frequency interval;
(5) Making the initial values of i and j both 1;
(6) Reading m x k data in one address of the RAM1 and m x k chips in a corresponding address of the RAM2 in each clock cycle at the ith code phase, multiplying the data by the chips correspondingly to realize parallel despreading, dividing m x k despreading results obtained in the same clock cycle into k groups, and accumulating the m despreading results in parallel to obtain k groups of accumulated results;
(7) Carrying out orthogonal frequency conversion on the de-spread and accumulated data by using a central frequency point of a jth frequency interval, and dividing intervals for the accumulated results after the orthogonal frequency conversion of all clock periods under the current code phase;
(8) Performing ping-pong cache on the data after the partition by using two storage areas, wherein one of the two storage areas is in a writing state, and the other storage area is in a reading state;
(9) After data storage is finished, calling a pipelined FFT core to perform FFT operation, and when the phase of the local pseudo code is aligned with the data after AD sampling in the step (1), the peak position of the FFT frequency spectrum is Doppler frequency offset;
(10) Judging whether I is equal to I, wherein I is the total number of code phases, if not, sliding one code phase, namely adding 1 to the value of I, and executing the steps (6) - (9), wherein the sliding of the code phases is realized by changing the initial reading address of the RAM 2; if yes, entering the step (11);
(11) Judging whether J is equal to J, wherein J is the total number of the frequency intervals, if not, adding 1 to the value of J, and enabling i =1, and executing steps (6) - (10); if yes, entering the step (12);
(12) If the peak value of the FFT frequency spectrum is larger than a preset threshold, judging that the acquisition is successful, and starting a tracking module; and (4) if the peak value of the FFT frequency spectrum is smaller than a preset threshold, judging that the acquisition fails, and returning to the step (1) to restart the acquisition.
2. The method according to claim 1, wherein in the step (2), if the global clock is clk, the accumulated reduced data rate is clk/N, and N is the accumulated number of points.
3. The method according to claim 2, wherein in step (3), the depth D of the buffer RAM1 is set to be larger than the depth D of the buffer RAM1 e Is composed of
The width is m x k, N is the number of accumulated points, and R is the accumulated data rate.
4. The method for fast capturing high dynamic short message signal with low SNR as claimed in claim 1, wherein in the step (4), the RF frequency is assumed to be F s Pseudo code rate of f c Doppler frequency range of-f d ～f d The accumulation time of the acquisition operation is 1/R, and the number J of the minimum frequency intervals is
R is the accumulated data rate; assuming that the center frequency point of the frequency interval is f q Then the modified pseudo code rate is
5. The method of claim 4, wherein the sampling rate of the local pseudo code is the same as the accumulated reduced data rate of clk/N.
6. The method as claimed in claim 5, wherein the pseudo code storage space has a depth of
Wherein f is c At the pseudo code rate, H is the pseudo code period.
7. The method for rapidly capturing a short message signal with low SNR and high dynamics as claimed in claim 1, wherein in the step (8), the storage depth of a storage area is D/k, and D is the number of FFT operation points.
8. The method for fast acquisition of the large dynamic short message signal with low SNR as claimed in claim 7, wherein D = R a /R，R a The data rate after despreading and accumulation in step (5) and R is the accumulated data rate in step (3).
9. The method according to claim 1, wherein in step (9), a pipeline FFT core is invoked to perform high speed FFT operation using k times the global clock.
10. The method for rapidly capturing a short message signal with low signal-to-noise ratio and high dynamic performance as claimed in claim 1, wherein the capturing time = data buffering time + capturing operation time;
wherein,
r is the accumulated data rate, f c Is the pseudo code rate, H is the pseudo code period;
if the sliding precision of the pseudo code phase is 1/t chips during capturing, the time of one round of capturing operation in each frequency interval is
The acquisition time required for J frequency intervals of serial search is
D is the number of FFT operation points in each clock cycle.
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