CN115765722B - Quadrature six-frequency-division circuit - Google Patents
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Abstract
The invention relates to the field of radio frequency communication chips, in particular to an orthogonal six-frequency division circuit, which comprises: the input buffer driving circuits 1 and 2 are formed by cascading two inverters and used for inputting rfn and rfp differential high-frequency signals, and the frequency division circuit is connected with the input buffer driving circuits 1 and 2 and comprises a latch circuit 4,5,6,7,8,9 and inverter circuits 3, 10, 11, 12 and 13; and the output sampling circuit is connected with the frequency dividing circuit. The frequency division is carried out on the high-frequency signal through the simple single-ended cascade latch circuit, the orthogonal IQ local oscillator signal with small phase mismatch is obtained through the sampling technology, the circuit structure is simple, the power consumption of the circuit is effectively reduced, the matching performance of the phase is guaranteed through the high-frequency re-sampling technology, the power consumption is effectively reduced, and the circuit framework can work to high frequency.
Description
Technical Field
The invention belongs to the field of radio frequency communication chips, and particularly relates to an orthogonal six-frequency division circuit.
Background
At present, most of the common orthogonal local oscillator signal generating circuits of communication chips are generated by a CMLflip-flop architecture frequency division and division 2 circuit, or two VCOs are designed to have an orthogonal IQ-VCO structure to directly generate IQ signals for output.
If the desired IQ signal is much lower than the frequency of the VCO of the PLL, the frequency of the VCO is typically divided by 2 times the frequency of the desired IQ local oscillator signal, and the desired IQ signal is obtained by a divide-by-2 circuit. The IQ orthogonal signals are two paths of signals of an I path and a Q path with the phase difference of 90 degrees. Finally, the IQ signals sent to the mixer are signals with 4 phases of 0 degree, 90 degree, 180 degree and 270 degree. The I paths are differential 0 degree and 180 degree signals, and the Q paths are differential 90 degree and 270 degree signals.
For example, patent No. 201910653341.1, a full swing high-speed orthogonal frequency-halving circuit is proposed, which ensures that the lowest point of an output signal can still reach a low potential under a high-frequency input signal by adding an NMOS cross-coupled pair, so that the swing of the output voltage reaches a power supply voltage, and the circuit can directly drive a post-stage circuit. But it has a problem that it is inconvenient for the frequency dividing operation.
The patent number is 201520256451.1, and the novel low-cost frequency division circuit provided by the patent number realizes that the frequency division multiple can be any integer, is not limited to a frequency division mode of only 2 multiples in the existing frequency division circuit, can realize the modification or setting of the frequency division multiple only by changing a dial switch, and does not need to modify any hardware circuit. Although the frequency division multiple can be modified, the power consumption of the frequency divider is larger, and especially when the frequency is high, the power consumption is larger. IQ divide-by-2 requires strict differentiation of the input signals, otherwise IQ mismatch will occur. Therefore, the frequency dividers on all frequency dividing links are required to be of a differential structure, and the requirement on frequency division is high.
Disclosure of Invention
To solve the above problem, the present invention provides a quadrature six-frequency division circuit, including: the input buffer driving circuits 1 and 2 are formed by cascading two inverters and used for inputting rfn and rfp differential high-frequency signals, and the frequency division circuit is connected with the input buffer driving circuits 1 and 2 and comprises a latch circuit 4,5,6,7,8,9 and inverter circuits 3, 10, 11, 12 and 13; and an output sampling circuit connected to the frequency dividing circuit, the output sampling circuit including a latch circuit 14, 16, 18, 20 and an output drive circuit constituted by inverters 15, 17, 19, 21. Output signals of the input buffer driving circuit are ckn and ckp respectively, wherein the ckn is connected with cn of the latch circuit 4,6,8, 14 and 18 and cp of the latch circuit 5,7,9, 16 and 20; ckp connects cp of latch circuit 4,6,8, 14, 18 and cn of latch circuit 5,7,9, 16, 20.
The latch circuits 4,5,6,7,8,9, 14, 16, 18 and 20 have the same circuit, and each latch circuit includes 2 PMOS transistors p1 and p2 and two NMOS transistors n1 and n2; the source electrode of the PMOS tube p1 is connected with the source electrode of the power vdd drain electrode p2, and the grid electrode of the PMOS tube p1 and the grid electrode of the n2 tube are connected together to the in end; the grid electrode of the PMOS pipe P2 is connected with a port cp, and the drain electrode of the PMOS pipe P2 and the drain electrode of the n1 pipe are connected together and connected with an out port; the grid electrode of the NMOS tube n1 is connected with the cn port, the source electrode of the NMOS tube n1 is connected with the drain electrode of the n2 tube, and the source electrode of the n2 tube is grounded.
The output out of the latch circuit 4 is connected to the in of the latch circuit 5 through a connection d 0; the output out of the latch circuit 5 is connected to the in of the latch circuit 6 through a connection d 1; the output out of the latch circuit 6 is connected to the in of the latch circuit 7 through a connection d 2; the output out of the latch circuit 7 is connected to the in of the latch circuit 8 through a connection d 3; the output out of the latch circuit 8 is connected with the in of the latch circuit 9 through a connecting line d 4; the output out of the latch circuit 9 is connected to the input of the inverter 3 through a connection d 5; the output of the inverter 3 is connected to the input in of the latch circuit 4 via a connection d 6.
The outputs of the input connection lines d1, 10 of the inverter 10 are connected to the input of the inverter 11 via connection i _ n, i _ n is connected to the input in of the sampling latch circuit 14, the output of the sampling latch circuit 14 is connected to the input of the inverter 15, the output of the inverter 15 is connected to the connection LO _ in,
the output of the inverter 11 is connected to the input in of the sampling latch circuit 18 via a connection i _ p, the output of the latch circuit 18 is connected to the input of the inverter 19, and the output of the inverter 19 is connected to the connection LO _ ip. LO _ in and LO _ ip are the I outputs of the divider circuit.
The input of the inverter 12 is connected to the line d4, the output of the inverter 12 is connected to the input of the inverter 13 through a connection q _ n, q _ n is connected to the input in of the sampling latch circuit 16, the output of the latch 16 is connected to the input of the inverter 17, and the output of the inverter 17 is connected to the line LO _ qn.
The output of the inverter 13 is connected to the input in of the sampling latch circuit 20 via a connection q _ p, the output of the latch circuit 20 is connected to the input of the inverter 21, and the output of the inverter 21 is connected to the connection LO _ qp.
The LO _ qn and LO _ qp are Q-path outputs of the frequency divider circuit.
The invention has the beneficial effects that:
1. the orthogonal six-frequency division circuit provided by the invention mainly comprises input buffer driving circuits 1 and 2, a frequency division circuit and an output sampling circuit, frequency division is carried out on a high-frequency signal through a simple single-ended cascade latch circuit, an orthogonal IQ local oscillator signal with small phase mismatch is obtained through a sampling technology, the circuit structure is simple, the power consumption of the circuit is effectively reduced, the matching performance of the phase is ensured through a high-frequency re-sampling technology, the power consumption is effectively reduced, and the circuit architecture can work to very high frequency;
2. the invention realizes the frequency division of high-frequency signals through a single-end cascade circular latch circuit, such as: except for frequency division of 2, two latch circuits are cascaded, 4 latch circuits are used except for 4,6 latch circuits are used except for 6, IQ two-path local oscillation signals with phase difference of 90 degrees can be obtained, and the two IQ signals are resampled through input high-frequency signals, so that IQ local oscillation signals with strict phase difference of 90 degrees can be obtained and output to a mixer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of an IQ-divide-by-6 divider according to a first embodiment of the present invention;
FIG. 2 illustrates a latch circuit diagram of an embodiment of the present invention;
FIG. 3 is a circuit diagram of an IQ-divide-by-4 divider according to a second embodiment of the present invention;
fig. 4 shows a circuit diagram of an IQ-division-2 frequency divider according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
The embodiment of the invention provides an orthogonal six-frequency division circuit, which comprises: the input buffer driving circuits 1 and 2 are composed of two cascaded inverters and used for inputting rfn, rfp differential high-frequency signals, and the frequency dividing circuit is connected with the input buffer driving circuits 1 and 2.
The orthogonal six-frequency-division circuit adopts 6 single-end latch circuits and an inverter which are cascaded end to end, and through an input differential high-frequency clock, the clock inputs of the front latch and the rear latch are opposite to each other, so that shifting latch is formed. Thus, for a 6-stage latching cascade structure, 6 clock cycles make a phase shift of exactly 180 degrees. Since the final output signal to the mixer requires signals with strict phase differences of 0, 90, 180, and 270 degrees, otherwise the receiving system will suffer from image rejection degradation due to the phase difference. For the signals of 0 degree and 90 degree obtained in fig. 1, we first get the signals close to 180 degree and 270 degree through the inverter. And then, the signals are subjected to high-frequency resampling by a resampling technology, so that signals with strict phase difference can be obtained.
The frequency division circuit comprises a latch circuit 4,5,6,7,8,9 and inverter circuits 3, 10, 11, 12 and 13; and an output sampling circuit connected to the frequency dividing circuit, the output sampling circuit including a latch circuit 14, 16, 18, 20 and an output driving circuit composed of inverters 15, 17, 19, 21. The output signals of the input buffer driving circuit are ckn and ckp respectively, wherein ckn is connected with cn of latch circuits 4,6,8, 14 and 18 and cp of latch circuits 5,7,9, 16 and 20; ckp connects cp of latch circuit 4,6,8, 14, 18 and cn of latch circuit 5,7,9, 16, 20.
The latch circuits 4,5,6,7,8,9, 14, 16, 18 and 20 are the same in circuit and each include 2 PMOS transistors p1 and p2 and two NMOS transistors n1 and n2; the source electrode of the PMOS tube p1 is connected with the source electrode of the power vdd drain electrode p2, and the grid electrode of the PMOS tube p1 and the grid electrode of the n2 tube are connected together to the in end; the grid electrode of the PMOS pipe P2 is connected with a port cp, and the drain electrode of the PMOS pipe P2 and the drain electrode of the n1 pipe are connected together and connected with an out port; the grid electrode of the NMOS tube n1 is connected with the cn port, the source electrode of the NMOS tube n1 is connected with the drain electrode of the n2 tube, and the source electrode of the n2 tube is grounded.
The output out of the latch circuit 4 is connected to the in of the latch circuit 5 through a connection d 0; the output out of the latch circuit 5 is connected to the in of the latch circuit 6 through a connection d 1; the output out of the latch circuit 6 is connected to the in of the latch circuit 7 through a connection d 2; the output out of the latch circuit 7 is connected to the in of the latch circuit 8 through a connection d 3; the output out of the latch circuit 8 is connected to the in of the latch circuit 9 through the connection line d 4; the output out of the latch circuit 9 is connected to the input of the inverter 3 through a connection d 5; the output of the inverter 3 is connected to the input in of the latch circuit 4 via a connection d 6.
The outputs of the input connection lines d1, 10 of the inverter 10 are connected to the input of the inverter 11 via connection i _ n, i _ n is connected to the input in of the sampling latch circuit 14, the output of the sampling latch circuit 14 is connected to the input of the inverter 15, the output of the inverter 15 is connected to the connection LO _ in,
the output of the inverter 11 is connected to the input in of the sampling latch circuit 18 via a connection i _ p, the output of the latch circuit 18 is connected to the input of the inverter 19, and the output of the inverter 19 is connected to a connection LO _ ip. LO _ in and LO _ ip are the I outputs of the divider circuit.
The input of the inverter 12 is connected to the line d4, the output of the inverter 12 is connected to the input of the inverter 13 through a connection q _ n, q _ n is connected to the input in of the sampling latch circuit 16, the output of the latch 16 is connected to the input of the inverter 17, and the output of the inverter 17 is connected to the line LO _ qn.
The output of the inverter 13 is connected to the input in of the sampling latch circuit 20 via a connection q _ p, the output of the latch circuit 20 is connected to the input of the inverter 21, and the output of the inverter 21 is connected to the connection LO _ qp. The LO _ qn and LO _ qp are Q outputs of the frequency divider circuit.
Divide by 6 is realized by cascade latch, and the rfp, rfn clock changes correspond to the state changes of d0, d2, d2, d3, d4, d6 as follows:
as can be seen from the above state change, the state cycles every six clock cycles, thereby implementing the divide-by-6 function. From the outputs d1 and d4, a time delay of exactly 3 clock cycles is realized, and a phase difference of 90 degrees is also realized. Since the divide-by-6 circuit is single ended, four phases are obtained by inverters 10, 11, 12, 13. The I _ n and I _ p and Q _ n and Q _ p are not absolute differences due to the time delay of the inverters, so the circuit of fig. 1 resamples I _ n and I _ p and Q _ n and Q _ p by sampling latch circuits 14, 18 and 16, 20, respectively, to obtain I and Q signals with strictly symmetrical phases. The high-frequency signal is subjected to frequency division through a simple single-end cascade latch circuit, and an orthogonal IQ local oscillator signal with small phase mismatch is obtained through a sampling technology. The circuit structure is simple, and the power consumption of the circuit is effectively reduced. The high-frequency re-sampling technology ensures the phase matching performance.
In the present embodiment, an IQ divide by 6 circuit is proposed. This circuit can also realize divide by 2, divide by 4 or even divide by 8 IQ frequency division circuits. This can be achieved by only changing the number of stages of the latch circuit accordingly. The following will specifically explain the present invention with reference to examples.
Example two
In the present embodiment, an IQ divide by 4 circuit is provided, as shown in fig. 3. The divide-by-4 circuit adopts 4 latch unit circuits and an inverter cascade, and then obtains orthogonal output signals by sampling through sampling latch circuits 14, 16, 18 and 20.
The method comprises the following specific steps:
the output out of the latch circuit 4 is connected to the in of the latch circuit 5 through a connection d 0; the output out of the latch circuit 5 is connected to the in of the latch circuit 6 through a connection d 1; the output out of the latch circuit 6 is connected to the in of the latch circuit 9 through a connection d 2; the output out of the latch circuit 9 is connected to the input of the inverter 3 through a connection d 5; the output of the inverter 3 is connected to the input in of the latch circuit 4 via a connection d 6.
The inputs of the inverter 10 are connected to the lines d1, 10 and to the input of the inverter 11 via the connection i _ n, while i _ n is connected to the input in of the sampling latch circuit 14, the output of the sampling latch circuit 14 is connected to the input of the inverter 15, the output of the inverter 15 is connected to the line LO _ in,
the output of the inverter 11 is connected to the input in of the sampling latch circuit 18 via a connection i _ p, the output of the latch circuit 18 is connected to the input of the inverter 19, and the output of the inverter 19 is connected to the connection LO _ ip. LO _ in and LO _ ip are the I outputs of the divider circuit.
The input of the inverter 12 is connected to the line d2, the output of the inverter 12 is connected to the input of the inverter 13 through a connection q _ n, q _ n is connected to the input in of the sampling latch circuit 16, the output of the latch 16 is connected to the input of the inverter 17, and the output of the inverter 17 is connected to the line LO _ qn.
The output of the inverter 13 is connected to the input in of the sampling latch circuit 20 via a connection q _ p, the output of the latch circuit 20 is connected to the input of the inverter 21, and the output of the inverter 21 is connected to the connection LO _ qp. The LO _ qn and LO _ qp are Q-path outputs of the frequency divider circuit.
EXAMPLE III
In the present embodiment, an IQ divide-by-2 circuit is provided, as shown in fig. 4. The division 2 adopts 2 latch units and an inverter cascade connection, and then the quadrature output signals are obtained through sampling latch circuits 14, 16, 18 and 20.
The method comprises the following specific steps:
the output out of the latch circuit 4 is connected to the in of the latch circuit 5 through a connection d 0; the output out of the latch circuit 5 is connected to the input of the inverter 3 through a connection line d 1; the output of the inverter 3 is connected to the input in of the latch circuit 4 via a connection d 6.
The inputs of the inverter 10 are connected to the lines d0, 10 and to the input of the inverter 11 via the connection i _ n, while i _ n is connected to the input in of the sampling latch circuit 14, the output of the sampling latch circuit 14 is connected to the input of the inverter 15, the output of the inverter 15 is connected to the line LO _ in,
the output of the inverter 11 is connected to the input in of the sampling latch circuit 18 via a connection i _ p, the output of the latch circuit 18 is connected to the input of the inverter 19, and the output of the inverter 19 is connected to the connection LO _ ip. LO _ in and LO _ ip are the I outputs of the divider circuit.
The input of the inverter 12 is connected to the line d1, the output of the inverter 12 is connected to the input of the inverter 13 through a connection q _ n, q _ n is connected to the input in of the sampling latch circuit 16, the output of the latch 16 is connected to the input of the inverter 17, and the output of the inverter 17 is connected to the line LO _ qn.
The output of the inverter 13 is connected to the input in of the sampling latch circuit 20 via a connection q _ p, the output of the latch circuit 20 is connected to the input of the inverter 21, and the output of the inverter 21 is connected to the connection LO _ qp. The LO _ qn and LO _ qp are Q-path outputs of the frequency divider circuit.
In the above embodiments, it can be seen that the quadrature six-frequency-division circuit provided in this application is mainly composed of input buffer driving circuits 1 and 2, a frequency division circuit, and an output sampling circuit, and frequency-divides a high-frequency signal by a simple single-ended cascade latch circuit, and obtains a quadrature IQ local oscillator signal with a small phase mismatch by a sampling technique. Through single-end cascade circulating latch circuit, realize the frequency division to high frequency signal, such as: except for frequency division of 2, two latch circuits are cascaded, 4 latch circuits are used except for 4,6 latch circuits are used except for 6, IQ two-path local oscillation signals with phase difference of 90 degrees can be obtained, and the two IQ signals are resampled through input high-frequency signals, so that IQ local oscillation signals with strict phase difference of 90 degrees can be obtained and output to a mixer.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (4)
1. A quadrature divide-by-six circuit, comprising:
input buffer drive circuits 1 and 2 for inputting rfn, rfp differential high frequency signals, formed by cascading two inverters, and
a frequency dividing circuit connected to the input buffer drive circuits 1 and 2, the frequency dividing circuit including a latch circuit 4,5,6,7,8,9 and inverter circuits 3, 10, 11, 12, 13;
and an output sampling circuit connected to the frequency dividing circuit, the output sampling circuit including a latch circuit 14, 16, 18, 20 and an output driving circuit composed of inverters 15, 17, 19, 21;
the output signals of the input buffer driving circuits 1 and 2 are ckn and ckp respectively, wherein ckn is connected with cn of latch circuits 4,6,8, 14 and 18 and cp of latch circuits 5,7,9, 16 and 20; the ckp is connected with cp of the latch circuit 4,6,8, 14 and 18 and cn of the latch circuit 5,7,9, 16 and 20;
the output out of the latch circuit 4 is connected to the in of the latch circuit 5 through a connection d 0; the output out of the latch circuit 5 is connected to the in of the latch circuit 6 through a connection d 1; the output out of the latch circuit 6 is connected to the in of the latch circuit 7 through a connection d 2; the output out of the latch circuit 7 is connected to the in of the latch circuit 8 through a connection d 3; the output out of the latch circuit 8 is connected with the in of the latch circuit 9 through a connecting line d 4; the output out of the latch circuit 9 is connected to the input of the inverter 3 through a connection d 5; the output of the inverter 3 is connected with the input in of the latch circuit 4 through a connection d 6;
the input of the inverter 10 is connected to the input of the inverter 11 through a connection line i _ n, the output of the sampling latch circuit 14 is connected to the input of the inverter 15, the output of the inverter 15 is connected to the input of the LO _ in, the output of the inverter 11 is connected to the input of the sampling latch circuit 18 through a connection line i _ p, the output of the latch circuit 18 is connected to the input of the inverter 19, the output of the inverter 19 is connected to the line LO _ ip, the input of the inverter 12 is connected to the connection line d4, the output of the inverter 12 is connected to the input of the inverter 13 through a connection line q _ n, the input of the sampling latch circuit 16 is connected to q _ n, the output of the latch 16 is connected to the input of the inverter 17, the output of the inverter 17 is connected to the connection line LO _ qn, the output of the inverter 13 is connected to the input of the sampling latch circuit 20 through a connection line q _ p, the output of the latch circuit 20 is connected to the input of the inverter 21, and the output of the inverter 21 is connected to the connection line LO _ p.
2. The quadrature six frequency division circuit of claim 1, wherein the latch circuits 4,5,6,7,8,9, 14, 16, 18, 20 are identical, each including 2 PMOS transistors p1, p2 and two NMOS transistors n1, n2;
the source electrode of the PMOS tube p1 is connected with the source electrode of the power vdd drain electrode p2, and the grid electrode of the PMOS tube p1 and the grid electrode of the n2 tube are connected together to the in end;
the grid electrode of the PMOS pipe P2 is connected with a port cp, and the drain electrode of the PMOS pipe P2 and the drain electrode of the n1 pipe are connected together and connected with an out port;
the grid electrode of the NMOS tube n1 is connected with the cn port, the source electrode of the NMOS tube n1 is connected with the drain electrode of the n2 tube, and the source electrode of the n2 tube is grounded.
3. A quadrature six frequency divider circuit as claimed in claim 2, wherein LO _ in and LO _ ip are I outputs of the divider circuit.
4. A quadrature divide-by-six circuit as claimed in claim 3, wherein LO _ qn and LO _ qp are Q outputs of the frequency divider circuit.
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| US8570076B2 (en) * | 2010-07-01 | 2013-10-29 | Qualcomm Incorporated | Parallel path frequency divider circuit |
| JP5318933B2 (en) * | 2011-11-15 | 2013-10-16 | シャープ株式会社 | Latch circuit, frequency divider circuit and PLL frequency synthesizer |
| CN106788400B (en) * | 2016-12-05 | 2019-11-22 | 中国科学技术大学 | The 50% duty ratio quadrature divider of broadband programmable of high-speed low-power-consumption |
| CN109150178B (en) * | 2018-07-20 | 2022-05-17 | 深圳全志在线有限公司 | Device and method for realizing decimal orthogonal frequency division without inductance |
| US11271550B1 (en) * | 2021-04-27 | 2022-03-08 | International Business Machines Corporation | Synchronous divider based on cascaded retiming |
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