TW201448450A - Odd frequency multiplier having low conversion loss - Google Patents

Abstract

Disclosed is an odd frequency multiplier having low conversion loss. A quadrature regenerative frequency divider has a specific cycle series connection to generate 1/N fin quadrature signals and 2(N-1)/N fin multiplied signals, where N is a positive integer not less than three. Single-balanced mixers mix the two frequency signals. A N-time multiplier is configured for multiple the mixed (2N-1)/N fin signals to transform (2N-1) fin signals. When using the frequency multiplier in series with a frequency synthesizer, the operation frequency of the frequency synthesizer can be reduced and lead to a low power consumption and a good phase noise for the quadrature voltage-controlled oscillator and the frequency divider. Because the multiplier can provide good conversion efficiency as well as the quadrature inputs and the quadrature outputs, it is attractive for application in a quadrature local oscillator generator.

Description

Odd multi-frequency device with low conversion loss

The invention relates to a frequency multiplier, in particular to an odd multiple frequency multiplier device with low conversion loss, which is particularly suitable for the band specification (22~29 GHz) of an automobile anti-collision radar system.

In the past decade of research, the circuit design for RF CMOS has focused on implementing a complete System-on-a-chip (SOC), which is designed to reduce costs and increase The performance of the chip, the main obstacle in implementing a SOC chip is that the heterodyne receiver requires an intermediate frequency (IF) filter, which is bulky due to physical limitations and directly limits the SOC. Therefore, a system for directly down-clocking RF signals into a baseband signal is also issued, which is simply referred to as a Direct-conversion receiver.

Figure 1 shows the architecture of a conventional 24 GHz direct down-conversion receiver. The low noise amplifier (LNA) 12 receives the RF signal from the antenna from the input and amplifies the signal to the next stage mixer. 11 is used for frequency reduction. Since the mixer 11 directly reduces the RF signal to the fundamental frequency, the local oscillator frequency will be very close to the RF signal, and the digital modulation system at the back end of the receiver needs to use the orthogonal carrier to solve the problem. Therefore, the local oscillator signal source must be able to provide an orthogonal signal to the IQ mixer 11 for down-conversion and input via an analog-to-digital converter 13. Out. Usually, the local oscillation signal is generated by a frequency synthesizer 10, and is implemented by using a quadrature voltage-controlled oscillator (QVCO) with a phase-locked loop (PLL). . When the frequency synthesizer 10 is directly operated at 24 GHz, two problems will arise: (1) the oscillator 15 operating at 24 GHz requires a larger current consumption to generate sufficient loop gain to maintain the oscillation condition, and, in addition, The output power and phase noise will also deteriorate as the frequency increases; (2) The first stage frequency divider circuit 14 connected in series with the oscillator 15 will increase the power consumption as the input frequency rises, and simultaneously lock The frequency range is also limited.

In addition, the current odd multi-frequency devices are mostly triplers. The common tripler can be divided into three types: Balanced Triple Frequency Transmitter, Self-mixing Triple Frequency Multi-Frequency and Injection-locked Triple Frequency Multiplier. First, FIG. 2 is a block diagram showing the structure of a conventional balanced triple frequency multiplier 200. The fundamental frequency (f _in ) signal passes through a power divider 210 connected to the input terminal 201, and is mainly utilized. The nonlinear characteristic of the transistor of the low-pass filter (LPF) 230 and the amplifier 240 is used to extract the triple frequency signal (3f _in ), and the band-pass filter (BPF) 250 is reused. To suppress the fundamental frequency (f _in ) signal, and through a 180 degree phase shifter 260, the phase of the double frequency signal between the two signal paths is 180 degrees out of phase, and the power combiner 220 can be utilized. The two frequency signals are mutually canceled before the output terminal 202. The disadvantage of this circuit is that the conversion efficiency is low, and a large input power needs to be injected to generate a triple frequency signal, and a 90 between the input terminal 201 and the output terminal 202 must be matched. The power splitter 210 and the power combiner 220 thus occupy a large wafer area.

In addition, the circuit architecture of the self-mixing tripler 300 is as shown in FIG. 3, and the circuit architecture of the injection-locked tripler 400 is applied. As shown in Figure 4. The self-mixing tripler 300 has a 2nd harmonic generator 310, a mixer 320, and a bandpass filter (BPF) 330 connected in series between its input terminal 301 and the output terminal 302. The other conductive line skips the second harmonic generator 310 and connects the input terminal 301 and the mixer 320. The injection locking type tripler 400 is connected in series between its input terminal 401 and the output terminal 402. There is a 3rd harmonic generator 410, a mixer 420, an injection-locked oscillator 430, and a band pass filter (BPF) 440. Both of these circuits are differential. If the above two circuits are to be designed as quadrature outputs, an additional set of identical circuits must be used, which will significantly increase the power consumption, and most importantly, the two circuits. It is not suitable to obtain high-frequency (five-fold or higher multi-frequency) output in series. The reason is that they all need high input power to drive the circuit. When the two circuits are connected in series, the latter circuit will not be easily driven. Conventional tripler are not suitable for use in 24 GHz direct down-conversion receivers.

In order to solve the above problems, the main object of the present invention is to provide an odd multi-frequency multi-frequency device with low conversion loss, which can relieve the limitation of the performance of the oscillator and the frequency divider by reducing the operating frequency of the frequency synthesizer. Therefore, it can effectively reduce the power consumption and obtain better output power and phase noise.

A second object of the present invention is to provide an odd multiple frequency multiplier device with low conversion loss, wherein the frequency divider loop of the phase locked loop is also reduced by 1/N due to the input frequency (N is not less than A positive integer of three, such as 1/5, can reduce the use of the frequency divider, so that the power consumption of the phase-locked loop can be effectively reduced.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses an odd number with low conversion loss The multi-frequency device includes an orthogonal regenerative frequency divider, a pair of single balanced mixers, and an N frequency multiplier. The quadrature regenerative type frequency divider is a circuit-series combination of a pair of Gilbert mixers, a pair of band pass filters and a current mode logic demultiplexer, so that the Gilbert The paired fundamental frequency signal injected by the special mixer is converted into a 1/N times frequency signal of the quadrature phase output of the current mode logic divider and a 2 (N-1)/N frequency of the common mode node output. Signal, where N is a positive integer not less than three. The single balanced mixer has a first RF transconductance stage and a first local oscillation switch stage respectively connected to the two output ends of the current mode logic demultiplexer for using 1/N times of the above The frequency orthogonal signal and the 2(N-1)/N times frequency signal are mixed and converted into a paired (2N-1)/N times frequency signal. The N frequency multiplier is connected to one of the first intermediate frequency outputs of the single balanced mixer for frequency-converting the (2N-1)/N times frequency signals into pairs (2N-1) Double frequency signal.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing odd multi-frequency multiplier device, the N frequency multiplier is specifically a triple frequency multiplier, so that the injected orthogonal fundamental frequency signal is finally converted into a quadruple frequency signal of the orthogonal output.

In the foregoing odd multi-frequency multiplier device, the two output ends of the current modal logic frequency divider can respectively be two-stage current modal logic circuit outputs for outputting the above-mentioned 1/N times frequency orthogonal signals. And an input pulse wave driving stage for outputting the above 2(N-1)/N times frequency signal, wherein the input pulse wave driving stage of the current mode logic frequency divider is connected to the first balanced wave mixer An RF transconductance stage, the output of the two-stage current mode logic circuit of the current mode logic divider is connected to the first local oscillation switch stage of the single balanced mixer.

In the foregoing odd multiple frequency multiplier, the Gilbert mixer may have a second RF transconductance stage and a second local oscillation switch stage. The output of the two-stage current modal logic circuit of the current mode logic divider can be further connected to the second RF transducing stage of the Gilbert mixer.

In the foregoing odd multiple frequency multiplier device, an output buffer stage circuit may be further included, which is connected to the N frequency multiplier, and the output buffer stage circuit is composed of a differential amplifier as the above (2N-1) The output buffer of the frequency signal.

10‧‧‧ frequency synthesizer

11‧‧‧ Mixer

12‧‧‧Low noise amplifier

13‧‧‧ Analog Digital Converter

14‧‧‧ phase-locked loop

15‧‧‧Oscillator

100‧‧‧ odd multiple frequency multiplier

101‧‧‧ input

102‧‧‧output

110‧‧‧Orthogonal regenerative frequency divider

120‧‧‧Single Balanced Mixer

121‧‧‧First RF Transducing Stage

122‧‧‧First local oscillation switch stage

123‧‧‧First IF output

124‧‧‧ Filter

130‧‧‧N frequency multiplier

131‧‧‧Multiplier switch stage

132‧‧‧Multiplier output

140‧‧‧Output buffer stage circuit

150‧‧‧Gibbert Mixer

151‧‧‧second RF transduction stage

152‧‧‧Second local oscillator switch stage

153‧‧‧second IF output

160‧‧‧Bandpass filter

170‧‧‧ Current mode logic divider

171‧‧‧Two-stage current modal logic circuit

172‧‧‧Input pulse drive stage

173‧‧‧Filter input

174‧‧‧拴Lock circuit

200‧‧‧Balanced Triple Frequency Transmitter

201‧‧‧ input

202‧‧‧output

210‧‧‧Power splitter

220‧‧‧Power Synthesizer

230‧‧‧ low pass filter

240‧‧‧Amplifier

250‧‧‧Bandpass filter

260‧‧‧180 degree phase shifter

300‧‧‧Self-mixing triple frequency multiplier

301‧‧‧ input

302‧‧‧output

310‧‧‧second harmonic generator

320‧‧‧ Mixer

330‧‧‧Bandpass filter

400‧‧‧Injected Locked Triple Frequency Transmitter

401‧‧‧ input

402‧‧‧output

410‧‧‧3rd harmonic generator

420‧‧‧ Mixer

430‧‧‧Injection Locking Oscillator

440‧‧‧ bandpass filter

Figure 1: Architecture diagram of a conventional 24 GHz quadrature direct down-conversion receiver.

Figure 2: Architecture diagram of a well-balanced triple frequency multiplier.

Figure 3: Schematic diagram of the conventional self-mixing triple frequency multiplier.

Figure 4: Schematic diagram of a conventional injection-locked tripler.

Figure 5 is a block diagram showing the principle of an odd multiple frequency multiplier with low conversion loss in accordance with an embodiment of the present invention.

Figure 6 is a block diagram showing the architecture of the odd multiple frequency multiplier according to an embodiment of the present invention.

Figure 7 is a circuit diagram of a set of Gilbert mixers and bandpass filters in an orthogonal regenerative frequency divider of the odd multiple frequency multiplier in accordance with an embodiment of the present invention.

Figure 8 is an illustration of an equivalent block diagram (A) and a signal clock of a current mode logic divider of an orthogonal regenerative frequency divider of the odd multiple frequency multiplier according to an embodiment of the present invention (B) ).

Figure 9 is a circuit diagram of a current mode logic divider of an orthogonal regenerative frequency divider of the odd multiple frequency multiplier according to an embodiment of the present invention.

Figure 10 is a schematic diagram showing the frequency simulation of a current mode logic frequency divider of an orthogonal regenerative frequency divider of the odd multiple frequency multiplier according to an embodiment of the present invention.

Figure 11 is a circuit diagram of a pair of single balanced mixers of the odd multiple frequency multiplier according to an embodiment of the present invention.

Figure 12 is a circuit diagram of a triple frequency multiplier of the odd multiple frequency multiplier according to an embodiment of the present invention.

Figure 13 is a circuit diagram of an output buffer stage circuit of the odd multiple frequency multiplier device in accordance with an embodiment of the present invention.

Figure 14 is a diagram showing specific operational data sheets for the odd multiple frequency multiplier device in accordance with an embodiment of the present invention.

Figure 15 is a graph showing the ratio of the output power to the output frequency of the odd multi-frequency device (input power of 3.9 dBm) in accordance with an embodiment of the present invention.

Figure 16 is a comparison chart of the test of the odd multi-frequency multiplier and the conventional triple frequency multiplier according to an embodiment of the present invention.

Figure 17 is a block diagram of an architecture of a 24 GHz quadrature direct down-conversion receiver constructed using the odd multiple frequency multiplier in accordance with an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with an embodiment of the present invention, an odd multiple frequency multiplier having low conversion loss is illustrated in the schematic block diagram of FIG. 5, the architectural block diagram of FIG. 6, and the circuits of the components of FIGS. 7-13. frame Composition. As shown in FIGS. 5 and 6, the odd multi-frequency multiplier 100 having low conversion loss includes an orthogonal regenerative frequency divider 110, a pair of single balanced mixers 120, and an N frequency multiplier 130. , wherein N is a positive integer not less than three. As shown in FIG. 5, the odd multi-frequency multiplier 100 uses the orthogonal regenerative frequency divider 110, the pair of single balanced mixers 120, and the N frequency multiplier 130 to provide a fundamental frequency signal. Converted to a paired (2N-1) times frequency signal, such as five times, seven times or nine times. In the present invention, the odd multi-frequency multiplier device 100 is a five-fold frequency device (when N=3, 2N-1=5), and the fundamental frequency signal (fo) input from the input terminal 101 passes through the orthogonal reproduction type. The frequency divider 110 can be reduced to a one-third frequency signal (fo/3), and the quadrature regenerative frequency divider 110 takes out four-fourths of the multi-frequency signal (4fo/3), and then passes the single balance. The mixer 120 can mix the two frequency signals to form an orthogonal three-fifth frequency signal (5fo/3), and the N-multiplier 130, for example, a triple frequency multiplier, can be multiplied by the output. The five-frequency signal (5fo) derived by the terminal 102 shows that the output frequency is five times the frequency multiplied and is a quadrature output signal. It has been proved by experiments that the odd multi-frequency multiplier device 100 has good frequency conversion efficiency and orthogonal output, quadrature input and other characteristics to convert the 4.8 Ghz frequency signal into 24 Ghz frequency signal to be suitable for orthogonal application. The local oscillator generator is further adapted to the band specification (22 to 29 GHz) of the automotive collision avoidance radar system.

Figure 6 is an architectural block diagram of the odd multi-frequency multiplier device 100. Referring to Figures 7-9, the orthogonal regenerative frequency divider 110 is a pair of Gilbert mixers 150 (Gilert mixer). a pair of bandpass filter 160 (BPF) and a current modal logic divider 170 (or CML (Current-mode-logic frequency divider) loop combination, that is A bandpass filter 160 is coupled between the corresponding Gilbert mixer 150 and the current mode logic divider 170, and the current mode logic divider 170 is coupled back to the Gilbert mixes. Frequency converter 150. By this one The loop serial combination relationship converts the paired fundamental frequency signals injected by the Gilbert mixer 150 into 1/N times the frequency signal and the common mode node of the quadrature phase output of the current modal logic divider 170. Output 2 (N-1) / N times the frequency signal.

The single balanced mixer 120 has a first RF transconductance stage 121 and a first local oscillation switch stage 122 respectively connected to the two outputs of the current mode logic demultiplexer 170 for The 1/N frequency orthogonal signal and the 2(N-1)/N frequency signal are mixed and converted into a paired (2N-1)/N frequency signal. In addition, the N frequency multiplier 130 is connected to the first intermediate frequency output end 123 of the single balanced mixer 120 for multiplying and converting the (2N-1)/N times frequency signals into pairs ( 2N-1) frequency signal. In this embodiment, N may be equal to 3. The N frequency multiplier 130 may specifically be a triple frequency multiplier, so that the injected orthogonal fundamental frequency signal is finally converted into a quadruple frequency signal of the orthogonal output. In different embodiments, N can be equal to 4, and the N frequency multiplier 130 can be specifically a quadruple frequency multiplier, so that the injected paired 7/4 times frequency signal is finally converted into a pair of seven times frequency signal. Alternatively, N may be equal to 5, and the N frequency multiplier 130 may specifically be a five-frequency multiplier, so that the injected 9/5 times frequency signal is finally converted into a pair of nine times frequency signal.

In this embodiment, the two output ends of the current mode logic frequency divider 170 are respectively output terminals of the two-stage current mode logic circuit 171 for outputting the 1/N times frequency orthogonal signal. An input pulse wave drive stage 172 for outputting the above 2 (N-1)/N frequency signals, the input pulse wave drive stage 172 of the current mode logic frequency divider 170 is coupled to the single balanced mixer 120 The first RF transconductance stage 121, the output of the two-stage current mode logic circuit 171 of the current mode logic frequency divider 170 is connected to the first local oscillation switch stage of the single balanced mixer 120. 122. More specifically, the Gilbert mixer 150 can have a second RF transduction stage 151 and a second local oscillation switch stage 152. The current mode logic The output of the two-stage current mode logic circuit 171 of the frequency divider 170 can be further connected to the second RF transconductance stage 151 of the Gilbert mixer 150.

In this embodiment, the current modal logic frequency divider 170 is a two-thirds frequency doubling signal (2fo/) mixed by the Gilbert mixer 150 and the band pass filters 160. 3 frequency signal) is introduced by its filter input terminal 173 and is reduced to half, and becomes a one-third frequency signal (fo/3 frequency signal) in the two-stage current mode logic circuit 171, and each has orthogonality Phase (0°, 90°, 180°, 270°) fo/3 frequency output signals (as shown in Figure 9), and finally these quadrature output signals are fed back by the two-stage current modal logic circuit 171 The second RF transducing stage 151 is injected into the Gilbert mixers 150. On the other hand, the 4fo/3 frequency output signals generated by the input pulse wave drive stages 172 of the current mode logic frequency divider 170 (or referred to as a driver stage clock-driven stage) are The orthogonal output signals (fo/3) of the two-stage current modal logic circuit 171 are transmitted together to the corresponding first RF transconductance stage 121 of the next-stage single balanced mixer 120 for mixing with the first local oscillation switch 122. The single balanced mixer 120 mixes two sets of mutually orthogonal 5fo/3 (0°, 180° and 90°, 270°) outputs at the first intermediate frequency output 123 (ie, the IF output 埠). The frequency signal is finally passed through the N frequency multiplier 130, for example, an orthogonal triple frequency multiplier, to upconvert the 5fo/3 output mixing signal to an N multiplied output signal such as a fifth frequency (5fo) at the output terminal 102. In addition, in order for the fifth frequency multiplier to drive the 50 Ω load resistance of the measuring instrument, the odd multi-frequency multiplying device 100 preferably further includes an output buffering stage circuit 140 connected to the N frequency multiplier 130. The output buffer stage circuit 140 is composed of a differential amplifier as an output buffer of the above (2N-1) times frequency signal. Therefore, two sets of differential amplifiers are used as the output buffer of the circuit.

As shown in FIG. 7, the circuit architecture of the Gilbert mixer 150 and the band pass filter 160 is shown. The Gilbert mixer 150 can be divided The second RF transduction stage 151 and the second local oscillation switch stage 152 are two parts. The second RF transconductance stages 151 are formed by source-level coupling pairs (M5-M6), and the second local oscillation switch stages 152 are stacked by the two sets of differential pairs (M1-M4). Above the RF transduction stage 151. The input signals (IN_P, IN_M) are injected into the second local oscillation switch stages 152 via the input terminal 101, and the source coupling pairs of the second RF transduction stages 151 are fed back the differential signal fo/3 (0°). Driven by 180°), each transistor of the second RF transducing stage 151 is turned on once in a period of one third of the signal, and then the second local oscillation switch stage 152 is switched by using an input signal, and finally The second intermediate frequency output 153 of the Gilbert mixer 150 generates 2fo/3 and 4fo/3 output mixing signals, and then the 2fo/3 frequency signals are taken out through the band pass filters 160. In addition, since the second RF transduction stage 151 has a transduction gain, the mixer can provide a conversion gain to the entire loop circuit to ensure that the feedback signal is not attenuated and disappear, and the current modal logic is divided. The frequency converter 170 can provide the correct divisor. The bandpass filters 160 are constructed of stray capacitances of two center-tapped spiral inductors (L1, L2) and transistors M9-M12 (not shown). In the layout considerations, the center-tapped spiral inductor is chosen to save the chip area. The resonant frequency is designed at 3.4 GHz, and when the frequency is higher than 3.4 GHz, the amplitude response shows the effect of signal attenuation. Let the bandpass filters The 160 can filter out the 6.8 GHz output mixing signal while suppressing the 5.1 GHz signal component leaking from the input terminals 101 to the second intermediate frequency output terminals 153.

As shown in Fig. 8 (A) and (B), the equivalent block diagram and signal clock map of the current mode logic frequency divider 170 are respectively shown. The current mode logic frequency divider 170 is composed of two latch circuits 174 (L1, L2), and the output terminals (Q ₂ , Q _2b ) of the latch circuit 174 labeled L2 can be cross-referenced to the label. It is the input terminal (D ₁ , D _1b ) of the latch circuit 174 of L1. In Fig. 8(B), the period of the output signal (Q ₁ , Q _1b , Q ₂ , Q _2b ) is twice the input pulse signal, and the phases of Q ₁ , Q ₂ and Q _1b , Q _2b are mutually The difference is 90 degrees, so the entire circuit can provide the function of dividing by two and the orthogonal output signal. According to this principle, when a differential signal (2fo/3) of 0° and 180° is injected into the filter input terminals 173 labeled CK _P and CK _M , (0°, 90°, 180°, 270°) of the divided output signal (fo/3) at the two-stage current modal logic circuit 171 labeled I _P , I _M , Q _P , Q _M , and as shown in FIG. 9 and as follows Thus, a multiplier output signal (4fo/3) can be obtained at the input pulse drive stage 172. Figure 9 is a circuit diagram of the current mode logic frequency divider 170, which is composed of two latch circuits 174 (i.e., CML circuits), wherein the output of the second stage cross-coupled pair is cross-referenced to the first level difference. At the input of the pair, the output voltage amplitude of the differential pair is approximately the starting voltage of the component, and the differential pair change of each output point is from V _DD -R _D I _SS to V _DD , so the maximum differential output voltage is approximately R _D I _SS , assuming that the output load of the shackle circuit 174 is a 50 Ω pull-up resistor, the swing of the output signal of the single-ended shackle circuit 174 is V _DD -R _D I _SS to V _{DD ,} which is V _DD ~ V _DD -0.8 V. In this case, the differential output signal swings less and the charge and discharge time for the parasitic capacitance will be less, so the circuit can be used as a high speed circuit. Figure 10 is a schematic diagram of the current mode logic frequency divider 170 taking out the double frequency signal, when the input signals from the filter input terminals 173 are 0° and 180° differential signals (2fo/3), and Biasing the current mirror below the source terminal in the ohmic region will achieve the effect of switching only the positive half of the input signal, ie at the input pulse drive stage 172 (ie, the source of the Clock differential pair) Extremely) produces a multiplier effect and derives the multiplier signal (4fo/3), which causes a small amount of variation in the vibration due to the different load of the Clock differential amplifier.

Figure 11 is a circuit diagram of the single balanced mixer 120. The circuit is used to divide the frequency (fo/3) and multiplier (4fo/3) signals generated by the quadrature regenerative frequency divider 110. Mixing with the first RF transconductance stage 121 via its first local oscillation switch stage 122, and filtering by its connection A 124 (e.g., bandpass filter) takes the signal out to produce a five-fifths (5fo/3) frequency signal at its first intermediate frequency output 123.

Figure 12 is a circuit architecture of the N frequency multiplier 130 (specifically a triple frequency multiplier). The circuit at its tail end partially grounds the two transistors (M ₃ , M ₄ ) to form a differential pair, and inputs a differential signal at the lower frequency multiplier switch stage 131 because of the difference. For the positive half-cycle input signal action, a doubling current (10fo/3) can be generated at the 汲 extreme, and then the upper frequency multiplier switch stage 131 is close to the input frequency of the transistor (M ₁ , M ₂ ) ( 5fo/3) mixes and then takes out the signal with a bandpass filter (BPF), so a signal of five times the frequency (5fo) can be generated at the output of the frequency multiplier 132.

Figure 13 is a circuit architecture of the output buffer stage circuit 140, which is composed of a differential amplifier, wherein the design of the differential amplifier is to allow the input end to have good impedance matching with the output of the fifth frequency multiplier, and Provides enough output power from the five-frequency multiplier to push the 50 Ω instrument load smoothly.

Figure 14 is an operational data table in which the odd multi-frequency multiplier device 100 is specifically a K-band quadrature octave. The input frequency (f _in ) of the five-frequency multiplier of the present invention has an input frequency of 4.5 to 5.7 GHz, and the output frequency of the output signal (f _out ) is 25.5 GHz. When the Post-layout simulation is completed, the 15th figure is the spectrum simulation result of the individual four phase output signals (f _out = 25.5 GHz). When the Post-layout is completed, the input signal (f _in = 5.1 GHz) is 3.9dBm, its output power is 1.871~2.392dBm. Further, as shown in Fig. 14, the phase error of the quadrature phase of the odd multi-frequency multiplier device 100 is between 1.907 and 2.398 degrees. And from the ratio of the output power to the output frequency in Figure 15, it is found that the five-fold output power can be positive, and the suppression of the fundamental, second, triple and quad-frequency output power is improved to exceed 39dB, 20dB, 26dB and 30dB.

Figure 16 is an odd multiple frequency multiplier device 100 of the present invention A comparison table of conventional triple frequency multipliers. The odd-numbered multi-frequency multiplier device 100 of the present invention can achieve an odd frequency of five times or more, which is incomparable to the conventional triple frequency multiplier. Further, in comparison with the conventional balanced triple frequency multiplier of FIG. 2, the conventional self-mixing triple frequency multiplier of FIG. 3, and the conventional injection-locked triple frequency multiplier of FIG. 4, the present invention The odd multi-frequency device 100 can have the lowest conversion loss, the lower phase error that can be measured, and the lower dissipated power at an input frequency of 5.1 GHz. In addition, the odd multi-frequency multiplier device 100 proposed by the present invention is particularly suitable for a five-frequency multiplier, and the maximum difference from the conventional active multiplier is: (1) the input stage uses a regenerative loop divider to obtain a low input. Sensitivity and the characteristics of the quadrature input, (2) using the regenerative loop divider to drive the mixer, the mixer can achieve good conversion gain and high output power, (3) using the second-order orthogonal triple frequency The output frequency is increased to 5 times the input frequency, and a quadrature output signal is obtained. As described above, the five-frequency multiplier can provide good low conversion loss, and can obtain characteristics such as orthogonal injection and quadrature output.

Figure 17 is a block diagram of an exemplary multi-frequency multiplier device 100 of the present invention constructed in a 24 GHz quadrature direct-conversion receiver to improve the aforementioned conventional problems. The odd multiple frequency multiplier device 100 of the present invention is specifically designed to be used as a five-frequency multiplier and is connected in series between a frequency synthesizer 10 and a pair of mixers 11, and each mixer 11 is connected in series. By reducing the low noise amplifier 12 (LNA) connected to the input terminal and the analog digital converter 13 (A/D) correspondingly connected to the output terminal, by reducing the operation of the frequency synthesizer 10 The frequency, for example, is 4.8 GHz QVCO, so the operating frequency of the oscillator 15 of the frequency synthesizer 10 can be reduced to 1/5 to 4.8 GHz, so as to effectively reduce the power consumption and obtain better output power and phase noise. In addition, the frequency divider loop of the phase-locked loop 14 (PLL) is also reduced by 1/5 due to the input frequency, so the frequency divider can be reduced. The power consumption of the phase locked loop 14 can be effectively reduced. Finally, after the odd multiplier effect of the odd multi-frequency multiplier device 100, a signal frequency of 24 GHz can be obtained at the output to be suitable for the band specification (22-29 GHz) of the automobile anti-collision radar system.

Therefore, the present invention provides an odd multiple frequency multiplier with low conversion loss by reducing the operating frequency of the frequency synthesizer, which can alleviate the limitations of the performance of the oscillator and the frequency divider, thereby effectively reducing the power consumption thereof. And get the best output power and phase noise. In addition, the frequency divider loop of the phase-locked loop of the odd multi-frequency device is also reduced by 1/N (where N is a positive integer not less than three), such as 1/5. Reduce the use of the frequency divider so that the power consumption of the phase-locked loop can be effectively reduced.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧ odd multiple frequency multiplier

101‧‧‧ input

102‧‧‧output

110‧‧‧Orthogonal regenerative frequency divider

120‧‧‧Single Balanced Mixer

121‧‧‧First RF Transducing Stage

122‧‧‧First local oscillation switch stage

123‧‧‧First IF output

124‧‧‧ Filter

130‧‧‧N frequency multiplier

131‧‧‧Multiplier switch stage

132‧‧‧Multiplier output

140‧‧‧Output buffer stage circuit

150‧‧‧Gibbert Mixer

151‧‧‧second RF transduction stage

152‧‧‧Second local oscillator switch stage

153‧‧‧second IF output

160‧‧‧Bandpass filter

170‧‧‧ Current mode logic divider

171‧‧‧Two-stage current modal logic circuit

172‧‧‧Input pulse drive stage

173‧‧‧Filter input

Claims (6)

An odd multiple frequency multiplier device with low conversion loss, comprising: an orthogonal regenerative frequency divider, which is a pair of Gilbert mixers, a pair of band pass filters and a current mode logic The loops of the frequency dividers are serially coupled to convert the paired fundamental frequency signals injected by the Gilbert mixer into 1/N times the frequency signal of the quadrature phase output of the current modal logic divider The common mode node outputs 2 (N-1)/N times the frequency signal, wherein N is a positive integer not less than three; a pair of single balanced mixers each have a first RF transducing stage and one The first local oscillation switch stage is respectively connected to the two output ends of the current mode logic frequency divider for mixing the 1/N times frequency orthogonal signal with the 2(N-1)/N times frequency signal The frequency is converted into a paired (2N-1)/N times frequency signal; and an N frequency multiplier is connected to one of the first intermediate frequency outputs of the single balanced mixer for using the above (2N-1) ) / N times the frequency signal is multiplied into a pair of (2N-1) times the frequency signal. The odd multi-frequency multiplier device with low conversion loss according to claim 1 of the patent application scope, wherein the N multiplier is a triple frequency multiplier, so that the injected orthogonal fundamental frequency signal is finally converted into a quadrature output. Five times the frequency signal. An odd-numbered multi-frequency multiplier device having a low conversion loss according to the first aspect of the patent application, wherein the two output ends of the current modal logic divider are respectively used to output the 1/N times frequency orthogonal The output of the two-stage current mode logic circuit of the signal and the input pulse wave drive stage for outputting the above 2(N-1)/N times frequency signal, the input pulse wave drive stage of the current mode logic frequency divider Connected to the first RF transconductance stage of the single balanced mixer, the output of the two-stage current modal logic circuit of the current modal logic divider is connected to the single balanced mixer The first local oscillation switch stage. An odd-numbered multi-frequency multiplier device having a low conversion loss according to claim 3, wherein the Gilbert mixer has a second RF transconductance stage and a second local oscillation switch stage, the current mode The output of the two-stage current modal logic circuit of the state logic divider is further connected to the second RF transducing stage of the Gilbert mixer. An odd multiple frequency multiplier device having low conversion loss according to claim 1 of the patent application, further comprising an output buffer stage circuit connected to the N frequency multiplier, the output buffer stage circuit being connected by a differential amplifier It is composed as an output buffer of the above (2N-1) times frequency signal. An orthogonal direct down-conversion receiver comprising an odd multiple frequency multiplying device with low conversion loss as described in claim 1 of the patent application, which is connected in series between a frequency synthesizer and a pair of mixers, Each mixer is connected in series between a low noise amplifier correspondingly connected to one input terminal and an analog digital converter correspondingly connected to an output terminal.