CN115764797A

CN115764797A - Undervoltage locking circuit

Info

Publication number: CN115764797A
Application number: CN202211262113.XA
Authority: CN
Inventors: 袁莹莹
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2022-10-14
Filing date: 2022-10-14
Publication date: 2023-03-07

Abstract

An embodiment of the present disclosure provides an under-voltage locking circuit, which includes: the circuit includes a sampling circuit, a comparison circuit, a reference voltage detection circuit, and an output circuit. The sampling circuit samples a voltage to be measured to generate a sampling voltage. The comparison circuit compares the sampled voltage with a reference voltage to generate a first indication signal. The reference voltage is generated from the voltage to be measured. The reference voltage detection circuit compares one of the first and second reference voltages with a reference voltage to generate a second indication signal. The output circuit generates an under-voltage lockout indication signal based on the first indication signal and the second indication signal. The first reference voltage is above the false positive threshold. The second reference voltage is lower than the misjudgment threshold. The misjudgment threshold is equal to the voltage of the first intersection point of the sampling voltage and the reference voltage in the process of increasing along with the voltage to be measured. The reference voltage detection circuit selects which of the first reference voltage and the second reference voltage is compared with the reference voltage according to the under-voltage-lock indication signal.

Description

Undervoltage locking circuit

Technical Field

The disclosed embodiments relate to the technical field of integrated circuits, and in particular, to an under-voltage locking circuit.

Background

In order to provide stable and reliable power supply to an application system, a power management chip may be used in the application system. The power management chip comprises an under-voltage lockout (UVLO) circuit. The under-voltage locking circuit can output an under-voltage locking indication signal for controlling the power management chip. And when the power supply voltage of the power supply management chip is lower than a preset value, the power supply management chip does not work and enters a locking state. Before the power supply voltage is enough to drive the power supply management chip to stably work, the internal control signal of the power supply management chip is locked and does not act.

In the starting process of the power management chip, the power voltage of the power management chip is stably increased. When the voltage rises to the turn-on voltage, the power management chip starts to work. The internal circuit or load of the power management chip may pull down the power supply voltage of the power management chip to below the turn-on voltage, resulting in a malfunction of the power management chip. At this time, the under-voltage locking circuit also needs to lock the internal control signal of the power management chip to make it not operate.

In the power management chip, the stability of the power voltage is particularly important, so it is necessary to integrate an under-voltage locking circuit inside the power management chip to improve the reliability and safety of the power supply. For other integrated circuits, the undervoltage locking circuit is also very important for improving the reliability and stability of the circuit.

Disclosure of Invention

Embodiments described herein provide an under-voltage lockout circuit.

In accordance with the present disclosure in the first aspect of (1) or (b), an under-voltage lockout circuit is provided. This undervoltage locking circuit includes: the circuit includes a sampling circuit, a comparison circuit, a reference voltage detection circuit, and an output circuit. Wherein the sampling circuit is configured to: the voltage to be measured from the voltage end to be measured is sampled to generate a sampled voltage, and the sampled voltage is provided to the comparison circuit via the first node. The comparison circuit is configured to: the sampled voltage is compared with a reference voltage from a reference voltage terminal to generate a first indication signal, and the first indication signal is provided to the output circuit via the second node. Wherein the reference voltage is generated according to the voltage to be measured. The reference voltage detection circuit is configured to: one of the first reference voltage and the second reference voltage is compared with the reference voltage to generate a second indication signal, and the second indication signal is provided to the output circuit via the third node. The output circuit is configured to: and generating an under-voltage locking indication signal based on the first indication signal and the second indication signal, and outputting the under-voltage locking indication signal from the signal output end. Wherein the first reference voltage is higher than the false positive threshold. The second reference voltage is lower than the misjudgment threshold. The misjudgment threshold is equal to the voltage of the first intersection point of the sampling voltage and the reference voltage in the process of increasing along with the voltage to be measured. The reference voltage detection circuit selects which of the first reference voltage and the second reference voltage is compared with the reference voltage according to the under-voltage-lock indication signal.

In some embodiments of the present disclosure, the reference voltage detection circuit compares the first reference voltage with the reference voltage if the under-voltage-lockout indication signal is at an active level and compares the second reference voltage with the reference voltage if the under-voltage-lockout indication signal is at an inactive level.

In some embodiments of the present disclosure, a sampling circuit includes: a first resistor, and a second resistor. The first end of the first resistor is coupled to the voltage terminal to be tested. The second end of the first resistor is coupled to the first end of the second resistor and the first node. The second end of the second resistor is coupled to the second voltage end.

In some embodiments of the present disclosure, the comparison circuit comprises: a first voltage comparator. The first input terminal of the first voltage comparator is coupled to the first node. The second input terminal of the first voltage comparator is coupled to the reference voltage terminal. The output end of the first voltage comparator is coupled with the second node.

In some embodiments of the present disclosure, the first input of the first voltage comparator is a non-inverting input. The second input terminal of the first voltage comparator is an inverting input terminal.

In some embodiments of the present disclosure, a reference voltage detection circuit includes: the voltage-controlled switch circuit comprises a second voltage comparator, an inverter, a first voltage-controlled switch and a second voltage-controlled switch. The first input terminal of the second voltage comparator is coupled to the reference voltage terminal. The second input terminal of the second voltage comparator is coupled to the first terminal of the first voltage-controlled switch and the first terminal of the second voltage-controlled switch. The output end of the second voltage comparator is coupled with the third node. The input end of the inverter is coupled with the signal output end. The output end of the inverter is coupled with the controlled end of the first voltage-controlled switch. The second terminal of the first voltage controlled switch is provided with a first reference voltage. The controlled end of the second voltage-controlled switch is coupled with the signal output end. The second terminal of the second voltage controlled switch is provided with a second reference voltage.

In some embodiments of the present disclosure, the first input of the second voltage comparator is a non-inverting input. The second input terminal of the second voltage comparator is an inverting input terminal.

In some embodiments of the present disclosure, the output circuit includes: and an AND gate. The first input terminal of the AND gate is coupled to the second node. The second input terminal of the AND gate is coupled to the third node. The output end of the AND gate is coupled with the signal output end.

In some embodiments of the present disclosure, the active level of the under-voltage-lockout indication signal is used to indicate that the circuit using the voltage to be tested enters an under-voltage-lockout state.

In some embodiments of the present disclosure, the active level of the under-voltage-lockout indication signal is a low level.

According to a second aspect of the present disclosure, an under-voltage lockout circuit is provided. This undervoltage locking circuit includes: the circuit comprises a first resistor, a second resistor, a first voltage comparator, a second voltage comparator, an inverter, a first voltage-controlled switch, a second voltage-controlled switch and an AND gate. The first end of the first resistor is coupled to the voltage terminal to be tested. The second end of the first resistor is coupled to the first end of the second resistor and the first input end of the first voltage comparator. The second end of the second resistor is coupled to the second voltage end. The second input terminal of the first voltage comparator is coupled to the reference voltage terminal. The output end of the first voltage comparator is coupled with the first input end of the AND gate. The first input terminal of the second voltage comparator is coupled to the reference voltage terminal. The second input terminal of the second voltage comparator is coupled to the first terminal of the first voltage-controlled switch and the first terminal of the second voltage-controlled switch. The output end of the second voltage comparator is coupled with the second input end of the AND gate. The input end of the inverter is coupled with the output end of the AND gate. The output end of the inverter is coupled with the controlled end of the first voltage-controlled switch. The second terminal of the first voltage controlled switch is provided with a first reference voltage. The controlled end of the second voltage-controlled switch is coupled with the output end of the AND gate. The second terminal of the second voltage controlled switch is provided with a second reference voltage. Wherein the reference voltage from the reference voltage terminal is generated according to the voltage to be measured from the voltage to be measured terminal. The first reference voltage is above the false positive threshold. The second reference voltage is lower than the misjudgment threshold. The misjudgment threshold is equal to the voltage of the voltage at the second end of the first resistor and the voltage of the reference voltage at the first intersection in the process of rising with the voltage to be measured.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, it being understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

FIG. 1 is an exemplary circuit diagram of an under-voltage lockout circuit;

FIG. 2 is a waveform diagram of some of the signals used in the under-voltage-lockout circuit of FIG. 1;

FIG. 3 is an exemplary circuit diagram of another under-voltage lockout circuit;

FIG. 4 is a waveform diagram of some of the signals used in the under-voltage-lockout circuit shown in FIG. 3;

FIG. 5 is a schematic block diagram of an under-voltage lockout circuit according to an embodiment of the present disclosure;

FIG. 6 is an exemplary circuit diagram of an under-voltage lockout circuit according to an embodiment of the present disclosure; and

FIG. 7 is a waveform diagram of some of the signals used in the under-voltage-lockout circuit shown in FIG. 6.

In the drawings, the same reference numerals in the last two digits correspond to the same elements. It should be noted that the elements in the figures are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).

Fig. 1 shows an exemplary circuit diagram of an under-voltage lockout circuit 100. The under-voltage lockout circuit 100 includes a first resistor R1, a second resistor R2, and a first voltage comparator CMP1. The first resistor R1 and the second resistor R2 may divide the voltage Vdd to be measured from the voltage terminal Vdd to be measured, so as to obtain the sampling voltage Vddr at the coupling point of the first resistor R1 and the second resistor R2. Thus, the sampling voltage Vddr = (Vdd × R2)/(R1 + R2). Where R1 represents the resistance value of the first resistor R1, and R2 represents the resistance value of the second resistor R2. In some embodiments of the present disclosure, the voltage to be measured Vdd may be used as a power supply voltage in a circuit (e.g., a power management chip) using the voltage to be measured Vdd. The sampled voltage Vddr is supplied to the non-inverting input terminal of the first voltage comparator CMP1. The inverting input terminal of the first voltage comparator CMP1 is coupled to the reference voltage terminal Vbg. The reference voltage terminal Vbg may provide the reference voltage Vbg. When the sampling voltage Vddr is higher than the reference voltage Vbg, the first indication signal Vdd _ good output from the first voltage comparator CMP1 is at a high level. When the sampling voltage Vddr is lower than the reference voltage Vbg, the first indication signal Vdd _ good is at a low level. Thus, the first indication signal Vdd _ good can be used as an under-voltage locking indication signal to indicate the under-voltage locking state. If the first indication signal Vdd _ good is at a low level (here, an active level), the under-voltage-locking circuit may control the circuit using the voltage to be measured to enter an under-voltage-locking state.

However, in some application scenarios, the reference voltage Vbg is also obtained from the voltage Vdd to be measured as the power supply voltage. The reference voltage Vbg will reach a stable value only after waiting for the voltage Vdd to be measured to be high enough. FIG. 2 shows waveforms of some signals for the under-voltage-lockout circuit shown in FIG. 1. As shown in fig. 2, the sampling voltage Vddr rises during the rising of the voltage Vdd to be measured. The reference voltage Vbg is substantially 0V when the voltage Vdd to be measured is low, and then gradually rises. The reference voltage Vbg rises faster than the sampling voltage Vddr. Thus, the reference voltage Vbg and the sampling voltage Vddr intersect at a voltage value V1 (time T1) during the rise of the voltage to be measured Vdd. In other words, V1 is the voltage of the reference voltage Vbg and the sampling voltage Vddr at the first intersection in the process of rising with the voltage Vdd to be measured. At time T2, the reference voltage Vbg crosses the sampling voltage Vddr again, at which point the reference voltage Vbg has reached the stable value Vs.

In practical applications, it is desirable that the under-voltage locking circuit 100 outputs the first indication signal Vdd _ good at a low level when the sampled voltage Vddr is lower than the stable value Vs, and outputs the first indication signal Vdd _ good at a high level when the sampled voltage Vddr is higher than or equal to the stable value Vs. On the other hand, as shown in fig. 2, the first indication signal Vdd _ good is erroneously at a high level when the sampling voltage Vddr is lower than V1 (before the time T1) because the reference voltage Vbg is too low.

The voltage Vdd to be measured can make the power management chip work normally after reaching a stable value. At the end of the operation, the voltage to be measured Vdd may slowly decrease. For convenience of description, the process in which the voltage to be measured Vdd is at a stable value is omitted in the example of fig. 2, and the process in which the voltage to be measured Vdd is dropped is shown immediately after the process in which the voltage to be measured Vdd is raised. At time T3, the sampling voltage Vddr is lower than the stable value Vs of the reference voltage Vbg, and therefore, the first indication signal Vdd _ good is inverted to a low level. The first indication signal Vdd _ good erroneously turns back to the high level again when the sampling voltage Vddr falls below V1 (at time T4) because the reference voltage Vbg is too low.

To solve this problem, it is proposed in the example of fig. 3 to add a reference voltage detection circuit 330 AND an AND gate AND to the under-voltage lockout circuit 300. The reference voltage detection circuit 330 includes: a second voltage comparator CMP2, an inverter NG, a first voltage controlled switch S1, and a second voltage controlled switch S2. The non-inverting input terminal of the second voltage comparator CMP2 is coupled to the reference voltage terminal Vbg. The inverting input terminal of the second voltage comparator CMP2 is coupled to the first terminal of the first voltage-controlled switch S1 and the first terminal of the second voltage-controlled switch S2. The second indication signal Vbg _ good is output from the output terminal of the second voltage comparator CMP 2. The input terminal of the inverter NG is coupled to the output terminal of the second voltage comparator CMP 2. The output terminal of the inverter NG is coupled to the controlled terminal of the first voltage controlled switch S1. The second terminal of the first voltage controlled switch S1 is provided with a first reference voltage Vref1. The controlled terminal of the second voltage-controlled switch S2 is coupled to the output terminal of the second voltage comparator CMP 2. The second terminal of the second voltage controlled switch S2 is provided with a second reference voltage Vref2. The first AND second indication signals Vdd _ good AND Vbg _ good are supplied to both input terminals of the AND gate AND, AND the under-voltage lockout indication signal Vdd _ good2 is output from an output terminal of the AND gate AND.

In the example of fig. 3, the second indication signal Vbg _ good is used to select whether the first reference voltage vref1 or the second reference voltage vref2 is supplied to the inverting input terminal of the second comparator CMP 2. Wherein the first reference voltage vref1> the second reference voltage vref2.

FIG. 4 shows waveforms of some signals for the under-voltage-lockout circuit shown in FIG. 3. As shown in fig. 4, the reference voltage Vbg is 0V right from the beginning, and thus the second indication signal Vbg _ good is at a low level. Thus, the first voltage controlled switch S1 is closed and the second voltage controlled switch S2 is open, the first reference voltage vref1 being selected for comparison with the reference voltage Vbg. When the reference voltage Vbg rises to the first reference voltage vref1 (time T5), the second indication signal Vbg _ good is inverted to a high level. At this time, the first voltage controlled switch S1 is opened and the second voltage controlled switch S2 is closed, and the second reference voltage vref2 is selected for comparison with the reference voltage Vbg. When the reference voltage Vbg falls to the second reference voltage vref2 (time T6), the second indication signal Vbg _ good is inverted to a low level.

The under-voltage lockout indication signal Vdd _ good2 outputted from the AND gate AND is at a high level only when both the second indication signal Vbg _ good AND the first indication signal Vdd _ good are at a high level. As long as both the second reference voltage vref2 and the first reference voltage vref1 are greater than V1, the under-voltage-lockout indication signal can be correctly output. However, when the main module served by the main module operates (the under-voltage lockout indication signal Vdd _ good2 is at a high level), the reference voltage Vbg is inevitably lowered due to signal disturbance such as the voltage Vdd to be measured, and therefore, the second reference voltage vref2 is designed to be relatively low to avoid that the reference voltage Vbg is disturbed to be lowered during normal operation and output an erroneous (low level) second indication signal Vbg _ good. However, if the second reference voltage vref2 is lower than V1, the situation that the under-voltage lockout indication signal Vdd _ good2 still has a wrong high level when the voltage to be measured Vdd drops occurs again.

In the example of fig. 4, the second reference voltage vref2 is set lower than V1. As shown in fig. 4, at time T5, the reference voltage Vbg is higher than the first reference voltage vref1, and thus, the second indication signal Vbg _ good is flipped to a high level. While the second reference voltage vref2 is selected for comparison with the reference voltage Vbg. The reference voltage Vbg is higher than the second reference voltage vref2 from time T5 until time T6, and thus the second indication signal Vbg _ good is at a high level between time T5 and time T6. Thus, at time T2, the under-voltage-lockout indication signal Vdd _ good2 is correctly inverted to a high level when the first indication signal Vdd _ good is inverted to a high level. At time T4, the first indication signal Vdd _ good erroneously toggles high, which still causes the under-voltage-lockout indication signal Vdd _ good2 to erroneously toggle high.

In view of the above problems, an embodiment of the present disclosure further provides an under-voltage locking circuit. Fig. 5 shows a schematic block diagram of an under-voltage-lockout circuit 500 according to an embodiment of the present disclosure. The under-voltage lockout circuit 500 may include: a sampling circuit 510, a comparison circuit 520, a reference voltage detection circuit 530, and an output circuit 540.

The sampling circuit 510 may be coupled to a voltage terminal Vdd to be measured. The sampling circuit 510 may be coupled to the comparison circuit 520 via a first node N1. The sampling circuit 510 may be configured to: the voltage to be measured Vdd from the voltage terminal to be measured Vdd is sampled to generate a sampling voltage Vddr, and the sampling voltage Vddr is provided to the comparison circuit 520 via the first node N1.

The comparison circuit 520 may be coupled to the sampling circuit 510 via a first node N1 and coupled to the output circuit 540 via a second node N2. The comparison circuit 520 may also be coupled to the reference voltage terminal Vbg. The comparison circuit 520 may be configured to: the sampling voltage Vddr is compared with the reference voltage Vbg from the reference voltage terminal Vbg to generate the first indication signal Vdd _ good, and the first indication signal Vdd _ good is provided to the output circuit 540 via the second node N2. The reference voltage Vbg is generated according to the voltage Vdd to be measured. In one example, the circuit that generates the reference voltage Vbg uses the voltage to be measured Vdd as the power supply voltage. The reference voltage Vbg may increase as the voltage to be measured Vdd increases and decrease as the voltage to be measured Vdd decreases.

The reference voltage detecting circuit 530 may be coupled to the output circuit 540 via a third node N3. The reference voltage detection circuit 530 may be further coupled to a reference voltage terminal Vbg, a first reference voltage terminal Vref1, a second reference voltage terminal Vref2, and a signal output terminal OUT. The reference voltage detection circuit 530 may be configured to: one of the first reference voltage Vref1 from the first reference voltage terminal Vref1 and the second reference voltage Vref2 from the second reference voltage terminal Vref2 is compared with the reference voltage Vbg to generate a second indication signal Vbg _ good, and the second indication signal Vbg _ good is provided to the output circuit 540 via the third node N3. The voltage of the sampling voltage Vddr and the reference voltage Vbg at the first intersection in the process of rising with the voltage Vdd to be measured may be set as the misjudgment threshold V1. The first reference voltage Vref1 is set to be higher than the erroneous determination threshold V1. The second reference voltage Vref2 is set to be lower than the erroneous determination threshold V1.

The reference voltage detection circuit 530 may be further configured to: which of the first reference voltage Vref1 and the second reference voltage Vref2 is compared with the reference voltage Vbg is selected according to the under-voltage lockout indication signal Vdd _ good2. In some embodiments of the present disclosure, the reference voltage detection circuit 530 compares the first reference voltage Vref1 with the reference voltage Vbg in a case where the under-voltage lockout indication signal Vdd _ good2 is at an active level (e.g., a low level), and compares the second reference voltage Vref2 with the reference voltage Vbg in a case where the under-voltage lockout indication signal Vdd _ good2 is at an inactive level (e.g., a high level).

The output circuit 540 may be configured to: the under-voltage lockout indication signal Vdd _ good2 is generated based on the first indication signal Vdd _ good and the second indication signal Vbg _ good, and the under-voltage lockout indication signal Vdd _ good2 is output from the signal output terminal OUT. In some embodiments of the present disclosure, the active level of the under-voltage-lockout indication signal Vdd _ good2 is used to indicate that a circuit using the voltage Vdd to be tested enters an under-voltage-lockout state. In some embodiments of the present disclosure, the active level of the under-voltage lockout indication signal Vdd _ good2 is a low level. In some embodiments of the present disclosure, the under-voltage-lockout indication signal Vdd _ good2 is at a high level when both the first indication signal Vdd _ good and the second indication signal Vbg _ good are at a high level. And the under-voltage lockout indication signal Vdd _ good2 is at a low level when any one of the first indication signal Vdd _ good and the second indication signal Vbg _ good is at a low level.

Fig. 6 illustrates an example circuit diagram of an under-voltage-lockout circuit 600 in accordance with an embodiment of the disclosure. The sampling circuit 610 may include: a first resistor R1, and a second resistor R2. The first end of the first resistor R1 is coupled to the voltage terminal Vdd to be measured. The second end of the first resistor R1 is coupled to the first end of the second resistor R2 and the first node N1. The second end of the second resistor R2 is coupled to the second voltage terminal V2.

The comparison circuit 620 may include: a first voltage comparator CMP1. A first input terminal of the first voltage comparator CMP1 is coupled to the first node N1. The second input terminal of the first voltage comparator CMP1 is coupled to the reference voltage terminal Vbg. The output terminal of the first voltage comparator CMP1 is coupled to the second node N2. In the example of fig. 6, the first input terminal of the first voltage comparator CMP1 is a non-inverting input terminal. The second input terminal of the first voltage comparator CMP1 is an inverting input terminal.

The reference voltage detecting circuit 630 may include: a second voltage comparator CMP2, an inverter NG, a first voltage controlled switch S1, and a second voltage controlled switch S2. The first input terminal of the second voltage comparator CMP2 is coupled to the reference voltage terminal Vbg. A second input terminal of the second voltage comparator CMP2 is coupled to the first terminal of the first voltage-controlled switch S1 and the first terminal of the second voltage-controlled switch S2. The output terminal of the second voltage comparator CMP2 is coupled to the third node N3. The input terminal of the inverter NG is coupled to the signal output terminal OUT. The output terminal of the inverter NG is coupled to the controlled terminal of the first voltage controlled switch S1. The second terminal of the first voltage controlled switch S1 is provided with a first reference voltage Vref1. The controlled terminal of the second voltage-controlled switch S2 is coupled to the signal output terminal OUT. The second terminal of the second voltage controlled switch S2 is provided with a second reference voltage Vref2. In the example of fig. 6, the first input terminal of the second voltage comparator CMP2 is a non-inverting input terminal. The second input terminal of the second voltage comparator CMP2 is an inverting input terminal.

The output circuit 640 may include: AND gate AND. The first input terminal of the AND gate AND is coupled to the second node N2. A second input terminal of the AND gate AND is coupled to the third node N3. The output end of the AND gate AND is coupled to the signal output end OUT.

In the example of fig. 6, the second voltage terminal V2 is grounded. Those skilled in the art will appreciate that variations to the circuit shown in fig. 6 based on the above inventive concepts are intended to fall within the scope of the present disclosure. In this modification, the input terminal and the voltage terminal of the voltage comparator described above may also have different arrangements from the example shown in fig. 6.

FIG. 7 illustrates waveforms of some of the signals used in the under-voltage-lockout circuit 600 shown in FIG. 6. The operation of the under-voltage lockout circuit 600 according to embodiments of the present disclosure is described below in conjunction with the examples of fig. 6 and 7.

In the example of fig. 7, the first reference voltage vref1 is set higher than V1, and the second reference voltage vref2 is set lower than V1. As shown in fig. 7, before the time T1, the sampling voltage Vddr is higher than the reference voltage Vbg, and thus the first indication signal Vdd _ good is at a high level. The reference voltage Vbg is 0V right from the beginning, so the second indication signal Vbg _ good is at a low level, so that the under-voltage-lock indication signal Vdd _ good2 is at a low level. During the period when the under-voltage-lock indication signal Vdd _ good2 is at a low level, the first voltage-controlled switch S1 is closed and the second voltage-controlled switch S2 is opened, and the first reference voltage vref1 is selected for comparison with the reference voltage Vbg. Until time T5, the reference voltage Vbg is lower than the first reference voltage vref1. The second indication signal Vbg _ good is at a low level until the time T5. At time T5, the reference voltage Vbg rises to the first reference voltage vref1, and thus, the second indication signal Vbg _ good is inverted to a high level. Since the first indication signal Vdd _ good is at a low level at this time, the under-voltage-lockout indication signal Vdd _ good2 is still at a low level. During the period when the under-voltage-lock indication signal Vdd _ good2 is at a low level, the first reference voltage vref1 is selected for comparison with the reference voltage Vbg. The reference voltage Vbg is higher than the first reference voltage vref1 from the time T5 until the time T2, and thus the second indication signal Vbg _ good is at a high level between the time T5 and the time T2. At time T2, the reference voltage Vbg has reached the stable value Vs, and the first indication signal Vdd _ good is flipped high, so that the under-voltage-lockout indication signal Vdd _ good2 is flipped high correctly. During the period when the under-voltage-lock indication signal Vdd _ good2 is at a high level, the first voltage-controlled switch S1 is open and the second voltage-controlled switch S2 is closed, and the second reference voltage vref2 is selected for comparison with the reference voltage Vbg. In the case where the reference voltage Vbg has reached the stable value Vs, since the second reference voltage vref2 is lower than V1, it is possible to avoid that the reference voltage Vbg is disturbed to become low to output an erroneous (low-level) second indication signal Vbg _ good at the time of normal operation. At time T3, the sampling voltage Vddr falls below the reference voltage Vbg, and therefore, the first indication signal Vdd _ good flips to a low level, so that the under-voltage-lock indication signal Vdd _ good2 flips to a low level. At this time, the first reference voltage vref1 is selected for comparison with the reference voltage Vbg. At the time T7, the reference voltage Vbg drops below the first reference voltage vref1, and therefore, the second indication signal Vbg _ good is at a low level after the time T7, so that the under-voltage-lockout indication signal Vdd _ good2 is kept at a low level, and the false-flipping phenomenon in fig. 4 does not occur.

In summary, the under-voltage locking circuit according to the embodiment of the present disclosure can accurately output the under-voltage locking indication signal, and avoids the phenomenon of false turning of the under-voltage locking indication signal caused by the generation of the reference voltage from the voltage to be measured.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An under-voltage lockout circuit, comprising: a sampling circuit, a comparison circuit, a reference voltage detection circuit, and an output circuit,

wherein the sampling circuit is configured to: sampling a voltage to be measured from a voltage end to be measured to generate a sampling voltage, and providing the sampling voltage to the comparison circuit through a first node;

the comparison circuit is configured to: comparing the sampled voltage with a reference voltage from a reference voltage terminal to generate a first indication signal, and providing the first indication signal to the output circuit via a second node, wherein the reference voltage is generated according to the voltage to be measured;

the reference voltage detection circuit is configured to: comparing one of a first reference voltage and a second reference voltage with the reference voltage to generate a second indication signal, and providing the second indication signal to the output circuit via a third node;

the output circuit is configured to: generating an under-voltage locking indication signal based on the first indication signal and the second indication signal, and outputting the under-voltage locking indication signal from a signal output end;

wherein the first reference voltage is higher than a false determination threshold, the second reference voltage is lower than the false determination threshold, the false determination threshold is equal to a voltage at a first intersection point of the sampling voltage and the reference voltage in a process of increasing with the voltage to be measured, and the reference voltage detection circuit selects which of the first reference voltage and the second reference voltage is compared with the reference voltage according to the under-voltage locking indication signal.

2. The under-voltage-lockout circuit of claim 1, wherein the reference voltage detection circuit compares the first reference voltage to the reference voltage if the under-voltage-lockout indication signal is at an active level and compares the second reference voltage to the reference voltage if the under-voltage-lockout indication signal is at an inactive level.

3. The under-voltage lockout circuit of claim 1, wherein the sampling circuit comprises: a first resistor, and a second resistor,

wherein a first end of the first resistor is coupled to the voltage terminal to be measured, and a second end of the first resistor is coupled to a first end of the second resistor and the first node;

the second end of the second resistor is coupled to a second voltage end.

4. The under-voltage lockout circuit of claim 1, wherein the comparison circuit comprises: a first voltage comparator for comparing a first voltage with a second voltage,

a first input terminal of the first voltage comparator is coupled to the first node, a second input terminal of the first voltage comparator is coupled to the reference voltage terminal, and an output terminal of the first voltage comparator is coupled to the second node.

5. The under-voltage-lockout circuit of claim 4, wherein the first input of the first voltage comparator is a non-inverting input and the second input of the first voltage comparator is an inverting input.

6. The under-voltage-lockout circuit of claim 1, wherein the reference voltage detection circuit comprises: a second voltage comparator, an inverter, a first voltage controlled switch, and a second voltage controlled switch,

a first input terminal of the second voltage comparator is coupled to the reference voltage terminal, a second input terminal of the second voltage comparator is coupled to the first terminal of the first voltage-controlled switch and the first terminal of the second voltage-controlled switch, and an output terminal of the second voltage comparator is coupled to the third node;

the input end of the inverter is coupled with the signal output end, and the output end of the inverter is coupled with the controlled end of the first voltage-controlled switch;

a second terminal of the first voltage controlled switch is provided with the first reference voltage;

the controlled terminal of the second voltage-controlled switch is coupled to the signal output terminal, and the second terminal of the second voltage-controlled switch is provided with the second reference voltage.

7. The under-voltage-lockout circuit of claim 6, wherein the first input of the second voltage comparator is a non-inverting input and the second input of the second voltage comparator is an inverting input.

8. The under-voltage lockout circuit of claim 1, wherein the output circuit comprises: an AND gate is connected to the first and second switches,

the first input end of the AND gate is coupled to the second node, the second input end of the AND gate is coupled to the third node, and the output end of the AND gate is coupled to the signal output end.

9. The under-voltage-lockout circuit of claim 1, wherein an active level of the under-voltage-lockout indication signal is used to indicate that a circuit using the voltage to be tested enters an under-voltage-lockout state.

10. An under-voltage lockout circuit, comprising: a first resistor, a second resistor, a first voltage comparator, a second voltage comparator, an inverter, a first voltage controlled switch, a second voltage controlled switch, and an AND gate,

the first end of the first resistor is coupled to a voltage end to be tested, and the second end of the first resistor is coupled to the first end of the second resistor and the first input end of the first voltage comparator;

a second end of the second resistor is coupled to a second voltage end;

a second input end of the first voltage comparator is coupled with a reference voltage end, and an output end of the first voltage comparator is coupled with a first input end of the AND gate;

a first input end of the second voltage comparator is coupled to the reference voltage end, a second input end of the second voltage comparator is coupled to the first end of the first voltage-controlled switch and the first end of the second voltage-controlled switch, and an output end of the second voltage comparator is coupled to a second input end of the and gate;

the input end of the phase inverter is coupled with the output end of the AND gate, and the output end of the phase inverter is coupled with the controlled end of the first voltage-controlled switch;

a second terminal of the first voltage controlled switch is provided with a first reference voltage;

the controlled end of the second voltage-controlled switch is coupled with the output end of the AND gate, and the second end of the second voltage-controlled switch is provided with a second reference voltage;

wherein the reference voltage from the reference voltage terminal is generated in accordance with the voltage to be measured from the voltage to be measured terminal, the first reference voltage is higher than a misjudgment threshold, the second reference voltage is lower than the misjudgment threshold, and the misjudgment threshold is equal to a voltage of the voltage at the second terminal of the first resistor and a voltage of the reference voltage at a first intersection in a process of rising with the voltage to be measured.