CN115763515A - Image sensor and manufacturing method thereof - Google Patents

Abstract

The present invention provides an image sensor including: the shallow trench isolation structure is arranged in the substrate, and the substrate is divided into a plurality of active regions by the shallow trench isolation structure; a gate structure disposed on the substrate; a plurality of metal layers stacked on the gate structure; a pixel array structure disposed on the substrate; one end of each conductive plug is connected with the grid structure or the shallow groove isolation structure or the active region, and the other end of each conductive plug is connected with the metal layer; and a plurality of heat conducting plugs connected to the metal layer, wherein the heat conducting plugs extend towards the direction close to the substrate, and the orthographic projections of the heat conducting plugs on the substrate are positioned in the active region. The invention provides an image sensor and a manufacturing method thereof, which can improve the consistency of dark current of the image sensor and improve the performance of the image sensor.

Description

Image sensor and manufacturing method thereof

Technical Field

The present invention relates to the field of image sensing technologies, and in particular, to an image sensor and a method for manufacturing the same.

Background

When an image sensor acquires an image, the output of an analog to digital converter (ADC) is not zero even if the pixels are not exposed, and thus the image does not appear to be absolutely black. The output level of the image sensor in a completely black environment is called a dark current. Dark current affects the color reproduction, dynamic range and sharpness of an image. The magnitude of the dark current is linear with exposure time and exponential with temperature. When the temperature rises to about 6 ℃, the dark current doubles. Because different module circuits of the chip generate heat unevenly, dark currents in different areas of the pixel array have certain difference, and the performance of the image sensor is affected.

If the dark current is corrected by the algorithm, the area of the chip circuit is increased, which results in an increase in chip cost and a decrease in frame rate of the image sensor. And insufficient compensation and excessive compensation can also occur through algorithm correction.

Disclosure of Invention

The invention aims to provide an image sensor and a manufacturing method thereof, which can improve the consistency of dark current of the image sensor and improve the performance of the image sensor.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the present invention provides an image sensor including:

the shallow trench isolation structure comprises a substrate, a plurality of first isolation layers and a plurality of second isolation layers, wherein the substrate is provided with a shallow trench isolation structure and is divided into a plurality of active regions by the shallow trench isolation structure;

a gate structure disposed on the substrate;

a plurality of metal layers stacked on the gate structure;

a pixel array structure disposed on the substrate;

a plurality of conductive plugs, one end of each conductive plug is connected to the gate structure or the shallow trench isolation structure or the active region, and the other end of each conductive plug is connected to the metal layer; and

and the plurality of heat conducting plugs are connected to the metal layer, extend towards the direction close to the substrate, and the orthographic projections of the heat conducting plugs on the substrate are positioned in the active region.

In an embodiment of the present invention, the shallow trench isolation structure includes a thermal conduction portion disposed in the substrate and connected to a portion of the conductive plug.

In an embodiment of the invention, the shallow trench isolation structure includes an isolation layer, the isolation layer is disposed in the substrate, and the isolation layer covers the thermal conduction portion.

In an embodiment of the present invention, a plurality of dielectric layers are disposed between the metal layer and the gate structure, and a heat dissipation layer is disposed between adjacent dielectric layers.

In an embodiment of the invention, the thermal conductive plug is disposed on the metal layer near the gate structure.

In an embodiment of the present invention, one end of the thermal conductive plug passes through the dielectric layer and is connected to the heat dissipation layer.

In an embodiment of the present invention, the heat dissipation layer is at least one of diamond, silicon carbide, graphene or a metal material.

In an embodiment of the invention, the thermal conductive plug is connected to the heat dissipation layer.

In an embodiment of the invention, the metal layer adjacent to the gate structure is connected to a plurality of pixel units of the pixel array structure.

The invention provides a manufacturing method of an image sensor, which comprises the following steps:

providing a pixel array structure and a substrate, and forming a shallow trench isolation structure in the substrate, wherein the substrate is divided into a plurality of active regions by the shallow trench isolation structure;

forming a gate structure on the substrate;

stacking a plurality of metal layers on the gate structure, wherein part of the metal layers are connected with the pixel array structure;

forming a conductive plug between the metal layer and the gate structure, or between the metal layer and the shallow trench isolation structure, or between the metal layer and the active region;

and forming a heat conducting plug at the same time of forming the metal layer, wherein the heat conducting plug is connected with the metal layer and extends towards the direction close to the substrate, and the orthographic projection of the heat conducting plug on the substrate is positioned in the active region.

As described above, the present invention provides an image sensor and a method for manufacturing the same, which can rapidly diffuse heat in the image sensor, reduce the influence of heat generated by different circuit modules on the image sensor, reduce non-uniformity of dark current in the image sensor, and improve the performance of the image sensor. The image sensor provided by the invention can reduce the difficulty of dark current algorithm correction, save the cost and improve the frame rate.

Of course, it is not necessary for any product to practice the invention to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic layout structure of an image sensor according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a shallow trench in an embodiment of the invention.

Fig. 3 is a schematic diagram of a shallow trench isolation structure according to an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a plurality of doped regions on a DD' cross-section in an embodiment of the invention.

FIG. 5 is a schematic structural diagram of a plurality of doped regions on an AA' cross-section in an embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a gate structure according to an embodiment of the invention.

FIG. 7 is a schematic view of a structure after deposition of a heat dissipation layer according to an embodiment of the invention.

Fig. 8 is a schematic structural view of an etched heat dissipation layer according to another embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a conductive plug in an embodiment of the invention.

Fig. 10 is a schematic structural diagram of a conductive plug according to another embodiment of the present invention.

FIG. 11 is a schematic diagram illustrating the distribution of conductive plugs between adjacent pixel cells on the BB' cross section in an embodiment of the present invention.

FIG. 12 is a schematic diagram of the distribution of conductive plugs between adjacent pixel cells on the BB' cross section in another embodiment of the present invention.

Fig. 13 is a schematic diagram of a stacked structure according to an embodiment of the invention.

FIG. 14 is a schematic structural diagram of a first deposition trench in accordance with an embodiment of the present invention.

FIG. 15 is a schematic view of a third photoresist pattern according to an embodiment of the invention.

FIG. 16 is a structural diagram of a second deposition trench in accordance with an embodiment of the present invention.

FIG. 17 is a schematic diagram of a structure for forming a metal layer and a thermal conductive plug in accordance with one embodiment of the present invention.

FIG. 18 is a schematic structural diagram of a polished metal layer according to an embodiment of the present invention.

Fig. 19 is a schematic structural diagram of a metal interconnect structure according to an embodiment of the invention.

FIG. 20 is a schematic view of a contact hole structure according to another embodiment of the present invention.

Fig. 21 is a schematic view of a conductive plug and a stacked structure in another embodiment of the invention.

FIG. 22 is a schematic structural diagram of a first deposition trench in another embodiment of the present invention.

FIG. 23 is a diagram illustrating a second deposition trench in accordance with another embodiment of the present invention.

FIG. 24 is a schematic structural diagram of a metal layer and a thermal conductive plug formed in another embodiment of the present invention.

Fig. 25 is a schematic diagram of a metal interconnect structure in another embodiment of the invention.

Fig. 26 is a schematic diagram of an image sensor according to an embodiment of the invention.

Fig. 27 is a schematic diagram of an image sensor according to another embodiment of the invention.

In the figure: 1. a pixel unit; 10. a substrate; 101. shallow trench; 102. a first doped region; 103. an isolation layer; 104. a heat conducting portion; 105. a second doped region; 106. a third doped region; 107. a fourth doped region; 20. a gate structure; 201. a gate oxide layer; 202. a polysilicon layer; 203. a protective layer; 30. a first dielectric layer; 40. a heat dissipation layer; 50. a second dielectric layer; 60. a contact hole; 601. a conductive plug; 70. a barrier layer; 80. a third dielectric layer; 90. a buffer layer; 100. a hard mask layer; 110. shielding the oxide layer; 111. a second photoresist pattern; 120. a first deposition trench; 121. a third photoresist pattern; 130. a second deposition trench; 140. a metal layer; 141. an inter-metal layer isolation structure; 142. a metal interlayer connection structure; 150. a thermally conductive plug; 160. a deep trench isolation structure; 170. a light transmitting layer; 180. a light shielding structure; 190. an optical filter; 200. a micro lens.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The image sensor provided by the invention can be a CMOS sensor, and can also be a Charge Coupled Device (CCD) image sensor. The image sensor provided by the invention can be applied to digital cameras and various electronic and optical devices.

Referring to fig. 1, the present invention provides an image sensor, which includes a plurality of pixel units 1, and the plurality of pixel units 1 are arranged in an array along a vertical direction and a horizontal direction to form a pixel array structure. Only 4 pixel units 1, for example, are shown in the pixel array structure shown in fig. 1, so as to illustrate the structure of the pixel unit 1 in the present invention. The number of pixel units 1 in the pixel array structure is not limited in the present invention. In the pixel array structure, the adjacent pixel units 1 are connected with each other, and a plurality of or even all the pixel units 1 in the pixel array structure are connected through metal, so that the whole array is uniformly heated, and the consistency of dark current is improved.

Referring to fig. 1 and fig. 2, a method for fabricating an image sensor according to the present invention first provides a substrate 10, and etches the substrate 10 to form a plurality of shallow trenches 101 on the substrate 10. After forming the shallow trench 101, the substrate 10 is implanted with first ions to form a first doped region 102. Fig. 2 shows the semiconductor structure from a DD' viewing angle. In the present embodiment, the substrate 10 is, for example, a silicon substrate forming a semiconductor structure. The substrate 10 may include a base material such as silicon (Si), silicon carbide (SiC), sapphire (Al), and an epitaxial single crystal silicon layer disposed over the base material ₂ O ₃ ) Gallium arsenide (GaAs), lithium aluminate (LiAlO) ₂ ) Etc. semiconductor substrate material. The present invention does not limit the material and thickness of the substrate 10. In the present embodiment, a plurality of shallow trenches 101 extending in the first direction and a plurality of shallow trenches 101 extending in the second direction are included. Wherein the first direction and the second direction intersect, and the specific first direction may be perpendicular to the second direction. The present invention does not limit the spacing between adjacent shallow trenches 101. On the substrate 10, a plurality of shallow trenches 101 are distributed in a regular grid. In the present embodiment, the first doped region 102 surrounds the shallow trench 101. In this embodiment, the first ions may be P + type ions.

Referring to fig. 1 to fig. 3, in an embodiment of the invention, an isolation layer 103 and a first thermal conductive portion 104 are formed in the shallow trench 101. In the present embodiment, an isolation medium, such as an insulating material, e.g., silicon oxide, is deposited in the trench by Atomic Layer Deposition (ALD), so as to form the isolation layer 103. Wherein the isolation layer 103 covers the walls of the shallow trenches 101. The invention does not limit the thickness of the isolation layer 103. After the isolation layer 103 is formed, a heat dissipation material may be deposited on the isolation layer 103 by chemical vapor deposition or sputtering, until the shallow trench 101 is filled with the heat dissipation material, thereby forming the thermal conductive portion 104. The heat dissipation material may be diamond, silicon carbide, or other materials, or may be a metal or alloy material, a nano carbon material, or the like, which has good heat dissipation performance. In this embodiment, in order to fill the shallow trench 101 with the thermal conductive portion 104, a heat dissipation material may be filled into the shallow trench 101 until the heat dissipation material covers the surface of the substrate 10. The excess heat sink material on the surface of the substrate 10 is removed by Chemical Mechanical Polishing (CMP), thereby forming the heat conductive portion 104. The isolation layer 103 and the thermal conduction portion 104 form a shallow trench isolation structure, and the shallow trench isolation structure can divide a plurality of active regions on the substrate 10. The isolation layer 103 is used to isolate adjacent active areas, and the thermal conduction portion 104 can be used to help conduct heat, avoiding local high temperatures and heat build-up on the substrate 10.

Referring to fig. 1 to 5, in an embodiment of the invention, second ions, third ions and fourth ions are sequentially implanted into the substrate 10, and a second doped region 105, a third doped region 106 and a fourth doped region 107 are sequentially formed. The second ions may be P-type ions with a low doping dose, and the second doped region 105 surrounds the first doped region 102. As shown in fig. 4, in the present embodiment, the third ions may be N-type ions with a low dopant amount, and the third doped region 106 is located between the adjacent second doped regions 105. In the present embodiment, the fourth ions may be P-type ions with a high dopant amount, and the fourth doping region 107 is disposed in the surface layer region of the substrate 10. The thickness of the fourth doped region 107 is not limited by the present invention. In the present embodiment, the ion implantation depth of the fourth doping region 107 is less than that of the first doping region 102, and the ion implantation depth of the first doping region 102 is less than that of the third doping region 106. The ion implantation depth of the third doped region 106 is smaller than that of the second doped region 105.

Referring to fig. 6, in an embodiment of the invention, a gate structure 20 is then formed on the substrate 10. Specifically, a gate oxide layer 201 is formed on the substrate 10 and the shallow trench isolation structure, a polysilicon layer 202 is formed on a portion of the gate oxide layer 201, and a protection layer 203 is formed on the polysilicon layer 202 and the gate oxide layer 201. In this embodiment, a gate oxide layer 201 is formed by oxidizing silicon oxide on the surface of the substrate 10 by a furnace process. And then, depositing polysilicon on the gate oxide layer 201 by using a furnace tube process, wherein the deposited polysilicon covers the surface of the gate oxide layer 201. After the polysilicon is deposited, a portion of the polysilicon may be etched with the aid of a Photoresist (PR) to form polysilicon layer 202. Wherein the polysilicon layer 202 is located on the second doped region 105, and the polysilicon layer 202 is located between adjacent shallow trench isolation structures. A protective layer 203 is then formed by depositing, for example, silicon nitride on the polysilicon layer 202 and on the gate oxide layer 201 by chemical vapor deposition. Wherein the protective layer 203 covers the surface of the polysilicon layer 202 and the gate oxide layer 201. In this embodiment, the thickness of the protection layer 203 is, for example, 500 angstroms to 1500 angstroms, and may be, for example, 1000 angstroms, it is to be noted that the protection layer 203 is not a single-layer film structure, but includes a plurality of films such as a sidewall dielectric layer, a metal silicide barrier, a via etching barrier, and the like.

Referring to fig. 1 and fig. 6, in an embodiment of the present invention, the gate structures 20 are distributed on the active region, and in the present embodiment, the pixel unit 1 includes a plurality of gate structures 20, and for example, includes a reset transistor RX, a source follower transistor SF, a transfer transistor TX, and a row select transistor SEL. The pixel unit 1 further includes a Floating Diffusion (FD) and a PhotoDiode (PD).

Referring to fig. 6 and 7, in the present embodiment, a first dielectric layer 30 is formed by depositing tetraethyl orthosilicate (TEOS) on the protection layer 203 by chemical vapor deposition. Wherein the first dielectric layer 30 covers the protection layer 203, and the thickness of the deposited first dielectric layer 30 is, for example, 5000 angstroms to 9000 angstroms. The first dielectric layer 30 is thinned to 2500 angstroms to 3500 angstroms, specifically 3000 angstroms, by chemical mechanical polishing. In this embodiment, a heat sink layer 40 is formed by depositing a thermally conductive material on the first dielectric layer 30. The thickness of the heat dissipation layer 40 may be, for example, 300 angstroms to 450 angstroms, and specifically, may be, for example, 300 angstroms.

Referring to fig. 1, 7-9, in an embodiment of the invention, the material forming the heat dissipation layer 40 may be an insulating and heat-conducting material such as diamond, and when the heat dissipation layer 40 is an insulating material, as shown in fig. 7. The heat dissipation layer 40 may also be a semiconductor heat conduction material such as silicon carbide, or a conductor heat conduction material such as graphene, and when the heat dissipation layer 40 is a semiconductor material or a conductor material, as shown in fig. 8, a portion of the heat dissipation layer 40 may be removed by photolithography, so as to facilitate the subsequent formation of the conductive plug 601. Through setting up the second heat radiation material, be favorable to the regional heat distribution homogenization of pixel, can avoid the heat local accumulation, promote image sensor's heat-sinking capability.

Referring to fig. 7 to 10 and 20, in an embodiment of the invention, a second dielectric layer 50 is formed on the first dielectric layer 30 and the heat dissipation layer 40, and the second dielectric layer 50, the first dielectric layer 30, the protective layer 203 and the gate oxide layer 201 are etched to form a contact hole 60. The contact hole 60 is not shown in the first embodiment shown in fig. 7 to 10, and may be referred to as the contact hole 60 of the second embodiment shown in fig. 20, or the position of the conductive plug 601 formed by filling the contact hole 60. Specifically, tetraethyl silicate is deposited by chemical vapor deposition on the first dielectric layer 30 and on the heat spreading layer 40 to form the second dielectric layer 50. The thickness of the second dielectric layer 50 is, for example, 1000 to 3000 angstroms, specifically, 1000 angstroms. Next, a photoresist layer may be spin-coated on the second dielectric layer 50 to form a photoresist layer, and a first photoresist pattern (not shown) may be formed by exposing and developing the photoresist layer. Wherein a portion of the contact hole 60 is connected to the surface of the thermal conductor 104. Specifically, the second dielectric layer 50, the first dielectric layer 30, the protective layer 203, and the gate oxide layer 201 are etched by plasma gas with the first photoresist pattern as a mask, and the contact hole 60 is formed by etching to the surface of the heat conductive portion 104. Wherein another portion of contact hole 60 connects to polysilicon layer 202 and the active region. In the present embodiment, the plasma gas used to form the contact hole 60 may be tetrafluoromethane (CF) ₄ ) And octafluorocyclobutane (C) ₄ F ₈ ) The mixed gas of (2).

Referring to fig. 7-10 and 20, in one embodiment of the present invention, after forming the contact hole 60, a metal material is deposited in the contact hole 60 to form a conductive plug 601. When the heat dissipation layer 40 is made of an insulating material, it is shown in fig. 9. When the heat dissipation layer 40 is made of a semiconductor or conductor material, as shown in fig. 10, the conductive plug 601 is spaced from the heat dissipation layer 40 by a predetermined distance. Wherein the predetermined distance is greater than the diameter of the conductive plug 601.

Referring to fig. 1, 11 and 12, in an embodiment of the invention, a portion of the conductive plug 601 is connected to the thermal via 104, and a portion of the conductive plug 601 is connected to the polysilicon layer 202 and the active region. Between adjacent pixel cells 1, the image sensor of the present invention is provided with a plurality of conductive plugs 601. As shown in fig. 11, fig. 11 is a schematic cross-sectional structure of the image sensor at BB'. It should be noted that, in fig. 1, the present invention only shows the position schematic diagram of the gate structure 20, and the present invention is not limited to the four types of gate structures 20 shown in fig. 1, and is not limited to the distribution of the gate structures 20 shown in fig. 1. Among them, at the BB' cross section, between the polysilicon layers 202 of the adjacent pixel cells 1, a plurality of conductive plugs 601 are connected to the substrate 10. And between the polysilicon layers 202 of the adjacent pixel units 1, a shallow trench isolation structure is provided in the substrate 10, wherein the heat conduction portion 104 extends along the connection line direction of the two adjacent polysilicon layers 202. In this embodiment, as shown in fig. 11, there are a plurality of conductive plugs 601 on the thermal conduction portion 104, and the conductive plugs 601 are distributed in a linear array along the extending direction of the thermal conduction portion 104. In another embodiment of the present invention, as shown in fig. 12, there are, for example, 1 conductive plugs 601, and the conductive plugs 601 extend along the extending direction of the heat conducting portion 104. The connection of the conductive plug 601 to the thermal conduction portion 104 facilitates uniform distribution of local heat throughout the pixel array.

Referring to fig. 10 and 13, in one embodiment of the present invention, after forming the conductive plug 601, a stacked structure is formed on the barrier layer 70. Specifically, a barrier layer 70 is formed on the second dielectric layer 50 and the conductive plug 601, a third dielectric layer 80 is formed on the barrier layer 70, a buffer layer 90 is formed on the third dielectric layer 80, a hard mask layer 100 is formed on the buffer layer 90, and a shielding oxide layer 110 is formed on the hard mask layer 100. In this embodiment, the barrier layer 70 may be formed by depositing silicon nitride or carbon-doped silicon nitride on the second dielectric layer 50 and on the conductive plug 601 by chemical vapor deposition. Wherein the barrier layer 70 and the heat sink layer 40 have the same thickness. In this embodiment, the third dielectric layer 80 may be formed by depositing low-k silicon dioxide on the barrier layer 70 by chemical vapor deposition. The thickness of the third dielectric layer 80 may be, for example, 1500 angstroms to 2500 angstroms, specifically 1800 angstroms. In this embodiment, the buffer layer 90 may be formed by depositing silicon oxide on the third dielectric layer 80 by chemical vapor deposition. Wherein the thickness of the buffer layer 90 is, for example, 500 to 900 angstroms, and specifically, may be, for example, 700 angstroms. Next, a hard metal material, such as titanium nitride (TiN), may be deposited on the buffer layer 90 by physical vapor deposition to form the hard mask layer 100. The hard mask layer 100 may be made of silicon nitride (SiN) or carbon-doped silicon Nitride (NDC), and the thickness of the hard mask layer 100 may be, for example, 100 to 400 angstroms, and more specifically, 300 angstroms. Next, an oxide material may be deposited on the hard mask layer 100 by chemical vapor deposition to form a masking oxide layer 110. Next, a photoresist may be spin-coated on the screen oxide layer 110 to form a photoresist layer, and a second photoresist pattern 111 may be formed by exposing and developing the photoresist layer.

Referring to fig. 13 and 14, in an embodiment of the invention, the masking oxide layer 110 and the hard mask layer 100 are etched by using the second photoresist pattern 111 as a mask; and etching the buffer layer 90, the third dielectric layer 80 and the barrier layer 70 by using the patterned hard mask layer 100 as a mask to form a first deposition trench 120. In this embodiment, portions of the screen oxide layer 110, the hard mask layer 100, the buffer layer 90 and the third dielectric layer 80 are removed by dry etching.

Referring to fig. 15-17, in an embodiment of the invention, the second dielectric layer 50 is etched and stops on the heat dissipation layer 40 to form a second deposition trench 130. Specifically, a photoresist layer may be formed on the exposed second dielectric layer 50 by using a photoresist, and the third photoresist pattern 121 may be formed by performing operations such as exposure and development on the photoresist layer. Wherein the third photoresist pattern 121 is disposed in the first deposition trench 120, and the third photoresist pattern 121 includes a plurality of etching windows. Wherein the etching windows are disposed between the adjacent polysilicon layers 202, and the etching windows in the third photoresist pattern 121 are disposed corresponding to the third doped regions 106. The second dielectric layer 50 is etched by plasma gas using the third photoresist pattern 121 as a mask and the heat dissipation layer 40 as an etch stop layer. In particular, can be prepared byOctafluorocyclobutane (C) ₄ F ₈ ) And carbon tetrafluoride (CF) ₄ ) The second dielectric layer 50 is etched to the surface of the heat dissipation layer 40 to form a second deposition trench 130.

Referring to fig. 16-17, in an embodiment of the invention, a metal layer 140 is formed in the first deposition trench 120 and a thermal conductive plug 150 is formed in the second deposition trench 130. In the present embodiment, the second deposition trench 130 is filled with a metal material, such as copper, by an electroplating process to form the thermal conductive plug 150. After the formation of the thermal conductive plug 150, the first deposition trench 120 is filled with a metal material to form a metal layer 140. The cross section of the heat conducting plug 150 may be rectangular or cylindrical. The cross-sectional width of the thermally conductive plug 150 may be, for example, 1/8 to 1/5 of the spacing between adjacent polysilicon layers 202. Specifically, the cross-sectional width of the thermal conductive plug 150 may be, for example, 0.1 μm to 0.2 μm. The invention does not limit the critical dimension of the thermal conductive plug 150, and the critical dimension of the thermal conductive plug 150 and the distance between the adjacent polysilicon layers 202 can be adjusted according to the different design areas of the image sensor circuit. In the present embodiment, the metal material is electroplated until the metal layer 140 is flush with the surface of the screen oxide layer 110 or exceeds the surface of the screen oxide layer 110, so as to ensure that the metal layer 140 fills the first deposition trench 120.

Referring to fig. 1 and 18, in an embodiment of the invention, after the metal layer 140 is formed, the masking oxide layer 110, the hard mask layer 100, the buffer layer 90 and a portion of the metal layer 140 may be removed by chemical mechanical polishing, so that the thickness of the metal layer 140 reaches a target value. In the image sensing apparatus, when the local temperature is raised due to the heat accumulated in the image sensing apparatus, the accumulated heat can be quickly and uniformly spread out through the heat dissipation structure formed by the conductive plug 601, the heat conduction portion 104, the heat dissipation layer 40, the heat conduction plug 150, and the metal layer 140, so that the heat accumulation inside the image sensing apparatus, especially the local heat accumulation, is avoided, the non-uniformity of dark current is reduced, and the performance of the image sensing apparatus is improved. The metal layer 140, the conductive plug 601 and the thermal conductive plug 150 can form a fast heat dissipation path, and the heat dissipation layer 40 and the thermal conductive portion 104 can dissipate heat more efficiently. The heat conducting plugs 150 are disposed between adjacent conductive plugs 601, and a plurality of heat conducting plugs 150 are disposed between adjacent conductive plugs 601, and the connection between the metal layer 140 and the heat conducting plugs 150 and the connection between the heat conducting portion 104 and the conductive plugs 601 can promote uniform diffusion of heat in the image sensing device. Also, the entire pixel array structure is connected together by the metal layer 140, as shown in fig. 1 and 18, thereby making heat distribution uniform in each area in the image sensor and facilitating rapid heat dissipation.

Referring to fig. 19, in an embodiment of the invention, a second metal layer 140, a third metal layer 140 to an nth metal layer 140 may be sequentially formed on the metal layer 140 by a damascene process. Wherein, an inter-metal layer isolation structure 141 is disposed between adjacent metal layers 140, and an inter-metal layer connection structure 142 is disposed between adjacent metal layers 140, thereby forming a metal interconnection structure. In the present embodiment, the metal interconnection structure includes a plurality of stacked metal layers 140, inter-metal layer isolation structures 141 disposed between adjacent metal layers 140, and inter-metal layer connection structures 142.

Referring to fig. 6 and 20, in another embodiment of the present invention, after forming the gate structure 20, a first dielectric layer 30 is formed on the gate structure 20, and a first photoresist pattern (not shown) is formed on the first dielectric layer 30. Then, the first dielectric layer 30 and a portion of the gate structure 20 are etched using the first photoresist pattern as a mask to form a contact hole 60. Specifically, silicon dioxide is deposited on the protective layer 203 by chemical vapor deposition to form the first dielectric layer 30, wherein the thickness of the first dielectric layer 30 is, for example, 3500 angstroms to 5000 angstroms, specifically, 4000 angstroms. Followed by octafluorocyclobutane (C) ₄ F ₈ ) And carbon tetrafluoride (CF) ₄ ) The first dielectric layer 30, the protective layer 203, and a portion of the gate oxide layer 201 are etched to expose a portion of the thermal conductive portion 104 and a portion of the polysilicon layer 202, thereby forming the contact hole 60.

Referring to fig. 20 and 21, in another embodiment of the present invention, the contact hole 60 is filled, a conductive plug 601 is formed, and a stacked structure is formed on the conductive plug 601 and on the first dielectric layer 30. Specifically, the heat dissipation layer 40 is formed on the first dielectric layer 30 and the conductive plug 601, the second dielectric layer 50 is formed on the heat dissipation layer 40, the buffer layer 90 is formed on the second dielectric layer 50, the hard mask layer 100 is formed on the buffer layer 90, and the shielding oxide layer 110 is formed on the hard mask layer 100. In the present embodiment, the stacked structure may be formed by chemical vapor deposition. Specifically, a material such as diamond or graphene is deposited on the first dielectric layer 30 and the conductive plug 601 to form a heat dissipation layer 40, wherein the thickness of the heat dissipation layer 40 is, for example, 200 angstroms to 400 angstroms, and specifically, may be, for example, 300 angstroms. Next, a low-k silicon dioxide is deposited on the heat dissipation layer 40 to form a second dielectric layer 50. The thickness of the second dielectric layer 50 is, for example, 1500 angstroms to 2500 angstroms, specifically 1800 angstroms. Next, silicon oxide is deposited on the second dielectric layer 50 to form a buffer layer 90. Wherein the thickness of the buffer layer 90 is, for example, 500 to 900 angstroms, and specifically, may be, for example, 700 angstroms. Next, a hard metal material, such as titanium nitride (TiN), is deposited on the buffer layer 90 to form a hard mask layer 100. The hard mask layer 100 may be made of silicon nitride (SiN) or carbon-doped silicon Nitride (NDC), and the thickness of the hard mask layer 100 may be, for example, 100 to 400 angstroms, and more specifically, 300 angstroms. Next, an oxide material is deposited on the hard mask layer 100 to form a masking oxide layer 110. Next, a photoresist may be spin-coated on the screen oxide layer 110 to form a photoresist layer, and a second photoresist pattern 111 may be formed by exposing and developing the photoresist layer.

Referring to fig. 21 and 22, in another embodiment of the present invention, the masking oxide layer 110, the hard mask layer 100, the buffer layer 90, the second dielectric layer 50 and the heat dissipation layer 40 are etched to form a first deposition trench 120. Specifically, the stacked structure is etched in multiple steps by using the second photoresist pattern 111 as a mask, so that the surface of the first dielectric layer 30 and the surface of the conductive plug 601 are exposed.

Referring to fig. 22 and 23, in another embodiment of the present invention, the first dielectric layer 30 is etched to form a second deposition trench 130. Specifically, a photoresist layer may be formed on the exposed first dielectric layer 30 by using a photoresist, and the third photoresist pattern 121 may be formed by performing operations such as exposure and development on the photoresist layer. Wherein the third photoresist pattern 121 are disposed in the first deposition trench 120, and the third photoresist pattern 121 includes a plurality of etch windows. Wherein the etching windows are disposed between the adjacent polysilicon layers 202, and the etching windows in the third photoresist pattern 121 are disposed corresponding to the third doped regions 106. Then, the third photoresist pattern 121 is used as a mask to pass through octafluorocyclobutane (C) ₄ F ₈ ) And carbon tetrafluoride (CF) ₄ ) The first dielectric layer 30 is etched to form a second deposition trench 130. Wherein the depth of the second deposition trench 130 may be, for example, 1/3 to 1/2 of the depth of the first dielectric layer 30. After the second deposition groove 130 is formed, the third photoresist pattern 121 is removed.

Referring to fig. 23 to 25, in another embodiment of the present invention, the first deposition trench 120 is filled to form a metal layer 140, and the second deposition trench 130 is filled to form a thermal conductive plug 150. Specifically, the metal layer 140 and the thermal conductive plug 150 may be formed by electroplating copper into the second deposition trench 130 and into the first deposition trench 120. In the present embodiment, after the metal layer 140 and the thermal conductive plug 150 are formed, the masking oxide layer 110, the hard mask layer 100, the buffer layer 90, and a portion of the metal layer 140 are removed by chemical mechanical polishing, so that the thickness of the metal layer 140 reaches a target value. In the present embodiment, next, a plurality of stacked metal layers 140 are formed on the metal layer 140, thereby forming a metal interconnection structure.

Referring to fig. 19, 26 and 27, in an embodiment of the present invention, after forming the metal interconnection structure, the substrate 10 is thinned, and a deep trench isolation structure 160 is formed on the backside of the substrate 10. Specifically, the deep trench isolation structure 160 may be formed on the back surface of the substrate 10 through a Deep Trench Isolation (DTI) process. The depth of the deep trench isolation structure 160 can be, for example, 0.3um to 1um. In the present embodiment, an active region is formed between the deep trench isolation structures 160. The deep trench isolation structure 160 corresponds to the thermal conductive portion 104. The deep trench isolation structures 160 may be distributed in a grid. Next, a transparent layer 170 is formed on the substrate 10 and the deep trench isolation structure 160, and a light shielding structure 180 is formed in the transparent layer 170. The light-shielding structure 180 separates a plurality of light-transmitting channels from the light-transmitting layer 170. In the image sensor, light passes through the light-transmitting channel to reach the pixel unit 1, and an optical signal is converted into an electric signal. In the present embodiment, the metal interconnection structure is electrically connected to the pixel unit 1. The electrical connection structure of the pixel unit 1 and the metal interconnection structure is not shown in the figure, wherein the metal interconnection structure and the pixel unit 1 can be connected through a through silicon via. The semiconductor device structure and the metal interconnection structure form a logic integrated circuit which accords with layout design. The logic integrated circuit can process the electric signal and realize the function of the image sensor.

Referring to fig. 19, 26 and 27, in an embodiment of the invention, a plurality of filters 190 are disposed on the transparent layer 170, and a microlens 200 is disposed on the filters 190. In the present embodiment, the filter 190 may be a Color Filter (CF). Wherein, the adjacent light transmission channels may correspond to filters 190 with different colors. For example, the filter 190 may be a red filter, a green filter, a blue filter, and the like. The present invention does not limit the type and thickness of the optical filter 190. The micro lens 200 covers the optical filter 190, and the light passes through the micro lens 200, and the light of the color corresponding to the wavelength selected by the optical filter 190 passes through the transparent layer 170 after being filtered by the optical filter 190. Specifically, the light passes through the optical filter 190 and the light-transmitting channel and then reaches between the deep trench isolation structures 160. Part of the incoming light may enter the pixel unit 1 through diffuse reflection by the light shielding structure 180.

Referring to fig. 1, 19, 26 and 27, a plurality of pixel units 1 form a pixel array structure of the image sensor. A metal layer 140 overlies the third doped region 106 and the conductive plug 601. In the integrated circuit layout structure provided by the invention, the whole pixel array structure is connected through the metal layer 140, and the metal heat conduction is superior to the silicon heat conduction and the electrolyte heat conduction, so that the temperature of the whole pixel array structure is uniform, and the heat dissipation capability is enhanced. In addition, the three-dimensional heat dissipation structure formed by the conductive plug 601, the heat conductive plug 150, the metal layer 140, the heat conduction part 104 and the heat dissipation layer 40 enables heat in the image sensor to be quickly and uniformly dissipated, effectively avoids local high heat, limits local dark current from being too high, and improves the performance of the image sensor. Wherein the metal layer 140 connecting the entire pixel array structure may be the first metal layer 140 near the gate structure 20.

The invention provides an image sensor and a manufacturing method thereof, wherein the image sensor comprises a substrate, a grid structure, a plurality of metal layers, an electric conduction plug and a plurality of heat conduction plugs. The substrate is provided with a shallow slot isolation structure, and the substrate is separated into a plurality of active regions by the shallow slot isolation structure. The gate structure is disposed on the substrate. A plurality of metal layers are stacked on the gate structure, and a part of the metal layers are connected to a plurality of pixel units of the image sensor. One end of the conductive plug is connected with the grid structure, the shallow groove isolation structure or the active region, and the other end of the conductive plug is connected with the metal layer. A plurality of heat conduction plugs are connected to the metal layer, wherein the heat conduction plugs extend towards the direction close to the substrate, and the orthographic projection of the heat conduction plugs on the substrate is located in the active region.

The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. An image sensor, comprising:

the shallow trench isolation structure comprises a substrate, a plurality of first isolation layers and a plurality of second isolation layers, wherein the substrate is provided with a shallow trench isolation structure and is divided into a plurality of active regions by the shallow trench isolation structure;

a gate structure disposed on the substrate;

a plurality of metal layers stacked on the gate structure;

a pixel array structure disposed on the substrate;

a plurality of conductive plugs, one end of each conductive plug is connected to the gate structure or the shallow trench isolation structure or the active region, and the other end of each conductive plug is connected to the metal layer; and

and the plurality of heat conducting plugs are connected to the metal layer, the heat conducting plugs extend towards the direction close to the substrate, and the orthographic projections of the heat conducting plugs on the substrate are positioned in the active region.

2. The image sensor of claim 1, wherein the shallow trench isolation structure comprises a thermal conduction portion disposed in the substrate and connected to a portion of the conductive plug.

3. The image sensor of claim 2, wherein the shallow trench isolation structure comprises an isolation layer disposed in the substrate, and the isolation layer covers the thermal conductive portion.

4. The image sensor as claimed in claim 1, wherein a plurality of dielectric layers are disposed between the metal layer and the gate structure, and a heat dissipation layer is disposed between adjacent dielectric layers.

5. The image sensor of claim 4, wherein the thermally conductive plug is disposed on the metal layer proximate to the gate structure.

6. The image sensor of claim 5, wherein one end of the thermal conductive plug is connected through the dielectric layer and the heat sink layer.

7. The image sensor of claim 4, wherein the heat spreading layer is at least one of diamond, silicon carbide, graphene, or a metal material.

8. The image sensor of claim 4, wherein the thermal conductive plug is connected to the heat sink layer.

9. The image sensor as claimed in claim 1, wherein the metal layer adjacent to the gate structure is connected to a plurality of pixel cells of the pixel array structure.

10. A method of manufacturing an image sensor, comprising the steps of:

providing a pixel array structure and a substrate, and forming a shallow trench isolation structure in the substrate, wherein the substrate is divided into a plurality of active regions by the shallow trench isolation structure;

forming a gate structure on the substrate;

stacking a plurality of metal layers on the grid structure, wherein part of the metal layers are connected with the pixel array structure;

forming a conductive plug between the metal layer and the gate structure, or between the metal layer and the shallow trench isolation structure, or between the metal layer and the active region;

and forming a heat conducting plug at the same time of forming the metal layer, wherein the heat conducting plug is connected with the metal layer and extends towards the direction close to the substrate, and the orthographic projection of the heat conducting plug on the substrate is positioned in the active region.

Images