CN115763499A - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN115763499A CN115763499A CN202211667947.9A CN202211667947A CN115763499A CN 115763499 A CN115763499 A CN 115763499A CN 202211667947 A CN202211667947 A CN 202211667947A CN 115763499 A CN115763499 A CN 115763499A
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- 238000000034 method Methods 0.000 claims description 24
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- 238000000151 deposition Methods 0.000 claims description 15
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- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 5
- 230000000994 depressogenic effect Effects 0.000 claims description 2
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- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
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- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
The application provides an array substrate, a preparation method of the array substrate and a display device, relates to the technical field of display, and aims to solve the problems that the mobility of current carriers in the array substrate and the on-state current are not ideal. The array substrate includes: a substrate; the first buffer layer is arranged on the substrate and provided with a first groove; the second buffer layer is arranged on the first buffer layer and fills the first groove to form a second groove, and the maximum caliber of the second groove is smaller than or equal to the minimum caliber of the first groove; an active layer disposed on the second buffer layer and a portion of which is located in the second groove to form a channel.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display device.
Background
In recent years, display technology has been rapidly developed, and the demand for Thin Film Transistor (TFT) technology has been increasing, such that the TFT has a volume as small as possible and a response speed as high as possible is also required. However, in the manufacturing process of the array substrate based on the thin film transistor, the mobility of carriers and the on-state current in the array substrate are not ideal due to the limitation of exposure accuracy and etching accuracy.
Disclosure of Invention
In view of the above, the present disclosure provides an array substrate, a method for manufacturing the array substrate, and a display device, so as to improve the problems of the array substrate that the mobility of carriers and the on-state current are not ideal.
The technical solution adopted by the present application to solve the above technical problems is as follows:
in a first aspect, the present application provides an array substrate, including:
a substrate;
the first buffer layer is arranged on the substrate and provided with a first groove;
the second buffer layer is arranged on the first buffer layer, the part of the second buffer layer corresponding to the first groove is adapted to the first groove and defines a second groove, and the maximum caliber of the second groove is smaller than or equal to the minimum caliber of the first groove;
an active layer disposed on the second buffer layer and a portion of which is located in the second groove to form a channel.
In some embodiments of the present application, the array substrate further includes a gate insulating layer disposed on the second buffer layer, a portion of the gate insulating layer corresponding to the second groove fits into the second groove and defines a third groove, the active layer is located in the gate insulating layer, and a portion of the active layer is located in the third groove.
In some embodiments of the present application, the array substrate includes a first insulating layer and a second insulating layer, the first insulating layer is disposed on the second buffer layer and forms the third groove along with the second groove, the active layer is disposed on the first insulating layer and a portion thereof is located in the third groove to form a fourth groove, the second insulating layer is disposed on the first insulating layer and covers the active layer, and a portion of the second insulating layer is recessed along the fourth groove formed by the active layer to form a fifth groove.
In some embodiments of the present application, the array substrate includes a first gate layer and a second gate layer, the first gate layer is disposed at the bottom of the second recess and covered by the first insulating layer, and the second gate layer is located in the fifth recess.
In some embodiments of the present application, the active layer includes a U-shaped portion and a conductor portion, the conductor portion is located on two sides of the U-shaped portion, the conductor portion is located on the first insulating layer and located outside the third groove, and the U-shaped portion is located in the third groove and defines the fourth groove.
In some embodiments of the present application, both sides of the U-shaped portion and the conductor portion are doped with P ions, and the conductor portion contains a concentration of P ions that is greater than a concentration of P ions contained in both sides of the U-shaped portion.
In some embodiments of the present application, the doping concentration of P ions in the U-shaped portion gradually decreases along the depth direction of the third groove.
In some embodiments of the present application, the array substrate further includes an interlayer insulating layer and a source drain layer, the interlayer insulating layer is disposed on the second insulating layer, and the second insulating layer and the interlayer insulating layer have all been provided with via holes, just the via holes on the second insulating layer and the via holes on the interlayer insulating layer communicate with each other to expose portions of the conductor portions, the source drain layer is disposed on the interlayer insulating layer and passes through the via holes and the conductor portions are connected.
In a second aspect, the present application provides a method for manufacturing an array substrate, including:
depositing a first buffer layer on a substrate;
patterning the first buffer layer and forming a first groove;
depositing a second buffer layer on the first buffer layer and filling the first groove, wherein the second buffer layer fills the first groove and is sunk to form a second groove;
forming an active layer on the second buffer layer, the active layer covering a partial region of the second buffer layer and a portion of the active layer being depressed with the second groove.
In some embodiments of the present application, the forming an active layer on the second buffer layer, and the sinking a portion of the active layer with the second groove includes:
forming a first gate layer at the bottom of the second groove of the second buffer layer;
forming a first insulating layer on the second buffer layer, wherein a part of the first insulating layer sinks along with the second groove to form a third groove;
an active layer is formed on the first insulating layer, and a portion of the active layer is sunken with the third groove to form a fourth groove.
In some embodiments of the present application, the method further comprises:
forming a second insulating layer on the first insulating layer, wherein the second insulating layer covers the active layer and is sunk with the fourth groove to form a fifth groove;
forming a second gate layer on the second insulating layer, and the second gate layer fills the fifth groove;
and etching the part of the second gate layer outside the fifth groove to ensure that the second gate layer is only located in the fifth groove finally.
In some embodiments of the present application, the method further comprises:
forming an interlayer insulating layer on the second insulating layer and the etched second gate layer, and etching the interlayer insulating layer and the second insulating layer to form mutually communicated via holes, wherein a part of the active layer is exposed out of the via holes;
and forming a source drain layer on the interlayer insulating layer, wherein the source drain layer penetrates through the through hole to be connected with the active layer.
In a third aspect, the present application provides a display device comprising the array substrate according to the first aspect.
In summary, due to the adoption of the technical scheme, the application at least comprises the following beneficial effects:
according to the array substrate, the preparation method thereof and the display device, a first buffer layer is formed on the substrate, and a first groove is formed on the first buffer layer; then, a second buffer layer is formed on the first buffer layer, and the first groove is filled to form a second groove. Here, the first groove is formed on the first buffer layer, mainly for the convenience of directly forming the second groove in the first groove. The second buffer layer is formed on the first buffer layer, and the first groove is formed on the first buffer layer, so that the second buffer layer can sink along with the first groove in the deposition process of the second buffer layer and is laid on the first groove to form a second groove, and the second groove is formed to be narrower than the first groove due to the thickness of the second buffer layer. The maximum caliber of the second groove is smaller than or equal to the minimum caliber of the first groove by controlling the deposition thickness, and the width of the groove is reduced; the active layer is arranged in the second groove to form a channel, and the width of the second groove is reduced compared with that of the first groove, so that the width of the channel is effectively reduced, the channel resistance is reduced, the mobility of carriers is increased, the on-state current is improved, the power consumption is reduced, and the performance of the product is greatly improved.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting of the present application, wherein:
FIG. 1 is a schematic diagram of a prior art array substrate;
fig. 2 is a schematic cross-sectional structure view of the array substrate in the length direction according to the embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present application;
FIG. 4 is a schematic view illustrating a process of fabricating an array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic view of a manufacturing process of an array substrate according to an embodiment of the present disclosure.
Description of reference numerals:
1. a substrate; 2. a first buffer layer; 21. a first groove; 3. a second buffer layer; 31. a second groove; 4. an active layer; 41. a third groove; 42. a conductor part; 43. a U-shaped portion; 5. a first insulating layer; 51. a fourth groove; 6. a second insulating layer; 61. a fifth groove; 7. a first gate layer; 8. a second gate layer; 9. an interlayer insulating layer; 10. a source drain layer; 11. a second light-shielding layer;
100. a substrate; 101. a first light-shielding layer; 102. a buffer layer; 103. an insulating layer; 104. an active layer; 105. a gate electrode; 106. an oxide insulating layer; 107. and a source drain electrode layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the words "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not set forth in detail in order to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles disclosed herein.
To facilitate understanding of the solution of the present application, the spline curves and arrows used as reference numbers in the drawings are described herein: the part indicated for the spline curve without the arrow is a solid part, i.e., a part having a solid structure; the parts indicated for the spline curves with arrows are phantom parts, i.e. parts without solid structures.
Fig. 1 is a schematic structural diagram of a conventional array substrate. As shown in fig. 1, the conventional array substrate includes a substrate 100, a first light shielding layer 101, a buffer layer 102, an insulating layer 103, an active layer 104, a gate electrode 105, an oxide insulating layer 106, and a source/drain electrode layer 107. 107 a first light-shielding layer 101 is formed on the substrate 100, and a buffer layer 102 is also formed on the substrate 100 and covers the light-shielding layer; depositing an active layer 104 and an insulating layer 103 on the buffer layer 102, wherein the active layer 104 is covered by the insulating layer 103; a gate electrode 105 and an oxide insulating layer 106 are formed over the insulating layer 103, and the gate electrode 105 is covered with the oxide insulating layer 106; through holes are formed in the oxide insulating layer 106 and the insulating layer 103, the through holes of the oxide insulating layer 106 and the insulating layer 103 are communicated with each other to expose the active layer 104, and the source-drain electrode layer 107 is connected with the active layer 104 through the through holes.
In the schematic structure of the array substrate shown in fig. 1, it can be seen that the active layer 104 is disposed parallel to the substrate 100, and this arrangement would increase the occupied area of the array substrate, which is not favorable for the development of the thin film transistor toward a smaller size. Also, in the conventional array substrate, the channel width is approximately equal to the length of the gate electrode 105. Because the margin (margin) in the current array substrate preparation process is very small and limited by the exposure precision of an exposure machine, the minimum critical dimension of the width of the gate electrode 105 can only be 4 μm, so the minimum channel length of the structure can only reach 4 μm, and under the limit of the current process, the yield cannot be ensured by further reducing the width of the gate electrode 105. Therefore, how to reduce the channel length has become a bottleneck in high frequency, high resolution, high aperture ratio and low power consumption display technology.
To this end, referring to fig. 2 and fig. 3 together, the present application provides an array substrate, including:
a substrate 1;
the first buffer layer 2 is arranged on the substrate 1, and the first buffer layer 2 is provided with a first groove 21;
the second buffer layer 3 is arranged on the first buffer layer 2, the part of the second buffer layer 3 corresponding to the first groove 21 is adapted to the first groove 21 and defines a second groove 31, and the maximum caliber of the second groove 31 is smaller than or equal to the minimum caliber of the first groove 21;
an active layer 4, the active layer 4 being disposed on the second buffer layer 3 and a portion thereof being positioned in the second groove 31 to form a channel.
The technical scheme provided by the application mainly depends on forming the first buffer layer 2 on the substrate 1, the first buffer layer 2 forms the first groove 21, and the first groove 21 is utilized to enable one part of the active layer 4 to be positioned in the first groove 21, so that the area required by the array substrate is saved compared with the mode that the active layer 4 and the substrate 100 are directly arranged in parallel; in addition, compared with the method of directly forming a channel by depending on the length of the gate electrode 105, the method of forming a channel on the first buffer layer 2 can also make the channel width smaller, which is beneficial to improving the carrier mobility. Furthermore, in order to further reduce the channel width, the second buffer layer 3 is formed on the first buffer layer 2, the second buffer layer 3 is used to sink along with the first groove 21 in the first groove 21 to form the second groove 31, the second groove 31 is formed without depending on an exposure machine, that is, without depending on the precision of the exposure machine, so that the influence of the precision of the exposure machine on the first groove 21 due to the fact that the first groove 21 depends on the formation of the exposure machine can be compensated, and the channel width formed at the first groove 21 can only be maintained between 1um and 1.5um. The second buffer layer 3 is formed to have a size of the second groove 31 smaller than that of the first groove 21 by its thickness. And the size of the second groove 31 can be precisely controlled by controlling the deposition thickness of the second buffer layer 3, so that the maximum caliber of the second groove 31 is smaller than or equal to the minimum caliber of the first groove 21, thereby ensuring that the second groove 31 can further reduce the width of the channel. A part of the active layer 4 is disposed in the second groove 31 to form a channel, the length of the channel is mainly determined by the width of the bottom of the second groove 31, and the width of the bottom of the second groove 31 is smaller than the width of the first groove 21 or the width of the gate electrode 105 in the prior art, which is beneficial to reducing the channel resistance, increasing the mobility of carriers, promoting the on-state current, reducing the power consumption, and greatly improving the product performance.
In some embodiments, the array substrate further includes a second light-shielding layer 11. The second light-shielding layer 11 is disposed on the substrate 1, and the first buffer layer 2 is disposed on the substrate 1 and covers the second light-shielding layer 11. The first groove 21 on the first buffer layer 2 is formed by patterning the first buffer layer 2 to form the first groove 21 mainly through processes such as exposure and etching. The width of the first groove 21 is limited by the precision of the exposure machine, and the width is in the range of 1um to 1.5um. The formation of the first groove 21 exposes a part of the second light-shielding layer 11, and is not shielded by the first buffer layer 2.
Further, the second buffer layer 3 is deposited on the first buffer layer 2, and due to the existence of the first groove 21, a portion of the deposition material is deposited in the first groove 21 during the deposition of the second buffer layer 3, so that a second groove 31 having the same shape as the first groove 21 is formed on the second buffer layer 3. The second groove 31 is formed by the thickness of the second buffer layer 3, so that the width of the second groove 31 is reduced compared with that of the first groove 21, and the purpose of solving the problem that the width of the first groove 21 cannot be further reduced due to the accuracy of the exposure machine is achieved. And the second buffer layer 3 is formed and the second groove 31 is formed on the second buffer layer 3, and the process of depositing the second buffer layer 3 is only needed, so that the process is simplified, and the production efficiency is improved.
In some embodiments, the array substrate further includes a gate insulating layer. The gate insulating layer is disposed on the second buffer layer 3 and covers the second recess 31 to form a third recess 41. As for the formation method of the gate insulating layer on the second buffer layer 3, a deposition method is mainly used, and the gate insulating layer is directly deposited on the second buffer layer 3, and in the deposition process, the material of the gate insulating layer also covers the second groove 31, and a third groove 41 having the same shape as the second groove 31 is formed along the shape of the second groove 31. Similarly, the width of the third groove 41 is further reduced compared to the second groove 31, which is more favorable for improving the carrier mobility. It should be further noted that, for the active layer 4, it is located in the gate insulating layer, and a part of the active layer 4 is located in the third groove 41.
Further, the gate insulating layer includes a first insulating layer 5 and a second insulating layer 6. The first insulating layer 5 is disposed on the second buffer layer 3 and forms a third groove 41 along with the second groove 31. Here again, the first insulating layer 5 is formed on the second buffer layer 3, mainly by deposition, and during the deposition, along the path of the second recess 31, i.e. forming the third recess 41. The active layer 4 is disposed on the first insulating layer 5, and a portion thereof is located in the third groove 41 to form a fourth groove 51. In detail, i.e., the material forming the active layer 4 is deposited on the first insulating layer 5, and at the third groove 41, the material of the active layer 4 is deposited on the third groove 41 following the shape of the third groove 41 to form a fourth groove 51 of reduced size, the same shape as the third groove 41. The second insulating layer 6 is provided on the first insulating layer 5 and covers the active layer 4. In detail, the second insulating layer 6 is also deposited on the first insulating layer 5, and during the deposition process, the fifth groove 61 is deposited along the contour of the fourth groove 51.
It should be noted that, for the second buffer layer 3 and the second groove 31, the first insulating layer 5 and the third groove 41, the active layer 4 and the fourth groove 51, and the second insulating layer 6 and the fifth groove 61, the formation of their layer structures and the formation of the grooves are all formed simultaneously by one step process, which saves the process steps, and the formation of each groove does not need to use external equipment such as an exposure machine, does not depend on the precision of the external equipment, and the process is simpler.
In some embodiments, the array substrate includes a first gate layer 7 and a second gate layer 8. The first gate layer 7 is arranged at the bottom of the second groove 31 and covered by the first insulating layer 5; the second gate layer 8 is disposed in the second insulating layer 6 and in the fourth recess 51. The first gate layer 7 is disposed at the bottom of the second recess 31, i.e. in the channel, and the channel width is mainly determined by the thickness of the second buffer layer 3 deposited in the first recess 21, and the channel width can be limited to be shorter regardless of the width of the first gate layer 7 itself. The second gate layer 8 is disposed in the second insulating layer 6 and located in the fourth recess 51, and when viewed from the structure in which the array substrate is sequentially stacked, the positional relationship between the second gate layer 8 and the first gate layer 7 can be regarded as a vertical relationship, where the first gate layer 7 corresponds to a bottom gate layer and the second gate layer 8 corresponds to a top gate layer. The two gate layers are arranged up and down, and the first gate layer 7 and the second gate layer 8 can generate an electric field on the surface of the active layer 4, so that carriers can be generated on the surface of the active layer 4, and the mobility and the on-state current are improved.
In some embodiments, for the active layer 4, it includes a U-shaped portion 43 and a conductor portion 42. The conductor parts 42 are located on both sides of the U-shaped part 43, the conductor parts 42 are disposed on the first insulating layer 5 and outside the third groove 41, and the U-shaped part 43 is disposed in the third groove 41 and defines a fourth groove 51. The U-shaped portion 43 is attached to the inner sidewall and the bottom wall of the third groove 41, and the conductor portion 42 is located at two sides of the third groove 41. The conductor part 42 is arranged outside the third groove 41 and on the first insulating layer 5, mainly in order that the conductor part 42 can be electrically connected with the subsequent electrode; the U-shaped portion 43 is provided in the third groove 41 mainly for reducing an excessive area occupied by the active layer 4 in the width direction of the first insulating layer 5, and the fourth groove 51 can be formed using the U-shaped portion 43.
Further, the shapes of the first groove 21, the second groove 31, the third groove 41, the fourth groove 51 and the fifth groove 61 are the same, and are different only in size. The shape of each groove is in an inverted trapezoid shape. In some embodiments, the active layer 4 is coated with photoresist and exposed to light, and the exposure amount is adjusted so that the photoresist is only located at the U-shaped portion 43. P ions are doped on both sides of the U-shaped portion 43, and the conductor portion 42 is also doped with P ions. Since the photoresist is only located in the U-shaped portion 43, and there is no photoresist at the conductor portion 42, during doping, heavily doped P ions are formed at the conductor portion 42, and lightly doped P ions are formed at two sides of the U-shaped portion 43. The term "heavily doped" and "lightly doped" as used herein mainly means the concentration of P ions, and heavily doped means that the concentration of P ions is high, and lightly doped means that the concentration of P ions is low. From this, it is understood that the P ion concentration contained in the conductor portion 42 is higher than the P ion concentration contained in both sides of the U-shaped portion 43. For the bottom of the U-shaped portion 43, the photoresist is thicker than for both sides of the U-shaped portion 43, and is almost undoped. It should be noted that, for the light doping of the U-shaped portion 43, since the third groove 41 is in the inverse trapezoid shape, the thickness of the photoresist coated along the depth direction of the third groove 41 is gradually increased during the photoresist coating process, so that the P ions are reduced with the increase of the photoresist thickness during the doping process, thereby forming a gradient P ion doping.
In some embodiments, the array substrate further includes an interlayer insulating layer 9 and a source drain layer 10. The interlayer insulating layer 9 is disposed on the second insulating layer 6, and the second insulating layer 6 and the interlayer insulating layer 9 are both provided with via holes communicated with each other to expose a portion of the conductor portion 42. By opening via holes communicating with each other on both the interlayer insulating layer 9 and the second insulating layer 6, a part of the conductor portion 42 is exposed at the via holes without being covered by the interlayer insulating layer 9 and the second insulating layer 6. The source drain layer 10 is disposed on the interlayer insulating layer 9, and a connection end of the source drain layer 10 extends into the conductor portion 42 through the via hole to be connected to the conductor portion 42, thereby realizing conduction.
Referring to fig. 4 and 5, for the array substrate according to any of the above embodiments, the present application further provides a method for manufacturing an array substrate, including:
s1, depositing a first buffer layer 2 on a substrate 1;
s2, patterning the first buffer layer 2 and forming a first groove 21;
s3, depositing a second buffer layer 3 on the first buffer layer 2 and filling the first groove 21, wherein the second buffer layer 3 fills the first groove 21 and is partially sunk to form a second groove 31;
s4, forming an active layer 4 on the second buffer layer 3, the active layer 4 covering a partial region of the second buffer layer 3 and a portion of the active layer 4 being sunk with the second groove 31.
The first buffer layer 2 is an inorganic film layer such as SiOx, siNx, siON, or the like, or a lamination of various inorganic film layers, the thickness is 600-1000nm, and then the first buffer layer 2 is patterned by exposure and etching to form a first groove 21, wherein the groove width of the groove along the length direction of the array substrate is 1-1.5um.
The second buffer layer 3 is also an inorganic film layer such as SiOx, siNx, siON, or a stack of various inorganic film layers, and has a thickness 1 to 3 times that of the first buffer layer 2. The greater the thickness of the second buffer layer 3, the smaller the width of the second groove 31. The width of the second groove 31 along the length direction of the array substrate after being covered by the second buffer layer 3 is 0.1-0.5um.
For the active layer 4, the thickness thereof is 50-100nm, the single crystal silicon in the active layer 4 is converted into polycrystalline silicon, and then the polycrystalline silicon is patterned by exposure and etching. The active layer 4 pattern is formed on the surface, side surface and bottom surface of the groove along the length direction, and is only formed on the bottom surface of the groove along the width direction of the array substrate.
In some embodiments, the step of forming the active layer 4 on the second buffer layer 3 and sinking a portion of the active layer 4 along with the second groove 31 specifically includes:
forming a first gate layer 7 at the bottom of the second groove 31 of the second buffer layer 3;
forming a first insulating layer 5 on the second buffer layer 3, and a portion of the first insulating layer 5 is sunk with the second groove 31 to form a third groove 41;
the active layer 4 is formed on the first insulating layer 5, and a portion of the active layer 4 is sunken with the third groove 41 to form a fourth groove 51.
The first gate layer 7 specifically includes processes such as film formation, exposure, etching, and the like. The first gate layer 7 is made of metal such as Mo, ti, W, etc. or a stacked layer of each metal, and has a thickness of 10-100nm.
The first insulating layer 5 is an inorganic film layer of SiOx, siNx, siON, or the like, and has a thickness of 30 to 200nm.
In some embodiments, the method for preparing the array substrate further comprises:
forming a second insulating layer 6 on the first insulating layer 5, and the second insulating layer 6 covers the active layer 4 and is sunken with the fourth groove 51 to form a fifth groove 61;
forming a second gate layer 8 on the second insulating layer 6, and the second gate layer 8 fills the fifth groove 61;
and etching the part of the second gate layer 8, which is positioned outside the fifth groove 61, so that the second gate layer 8 is finally positioned only in the fifth groove 61.
The second insulating layer 6 is an inorganic film layer such as SiOx, siNx, siON, or the like.
The second gate layer 8 is made of a metal such as Mo, ti, W, or a stack of metals, and has a thickness equal to the depth of the fifth recess 61. However, when the second gate layer 8 is completely located in the fifth recess 61, the initially deposited second gate layer 8 fills the fifth recess 61 and also has a certain thickness on the second insulating layer 6. Coating a photoresist on the second gate layer 8, performing full-surface exposure, adjusting the exposure amount to enable the photoresist after development to only fill the fifth groove 61, then patterning the second gate layer 8, performing full-surface etching on the second gate layer 8 outside the fifth groove 61, etching the second gate layer 8 without the photoresist protection, and finally only leaving the second gate layer 8 in the fifth groove 61.
In some embodiments, the method of making further comprises:
forming an interlayer insulating layer 9 on the second insulating layer 6 and the etched second gate electrode layer 8, and etching the interlayer insulating layer 9 and the second insulating layer 6 to form via holes communicating with each other, the via holes exposing a portion of the active layer 4;
a source drain layer 10 is formed on the interlayer insulating layer 9, and the source drain layer 10 is connected to the active layer 4 through a via hole.
The present application further provides a display device, which includes the array substrate in any of the above embodiments, and also has the corresponding beneficial effects of the array substrate, which are not described herein again.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing detailed disclosure is to be considered merely illustrative and not restrictive of the broad application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, certain features, structures, or characteristics may be combined as suitable in one or more embodiments of the application.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
For each patent, patent application publication, and other material cited in this application, such as articles, books, specifications, publications, documents, and the like, the entire contents of which are hereby incorporated by reference into this application, except for application history documents that are inconsistent with or conflict with the contents of this application, and except for documents that are currently or later become incorporated into this application as though fully set forth in the claims below. It is noted that the descriptions, definitions and/or use of terms in this application shall control if they are inconsistent or contrary to the present disclosure.
Claims (13)
1. An array substrate, comprising:
a substrate;
the first buffer layer is arranged on the substrate and provided with a first groove;
the second buffer layer is arranged on the first buffer layer, the part of the second buffer layer corresponding to the first groove is adapted to the first groove and defines a second groove, and the maximum caliber of the second groove is smaller than or equal to the minimum caliber of the first groove;
an active layer disposed on the second buffer layer and a portion of which is located in the second groove to form a channel.
2. The array substrate of claim 1, further comprising a gate insulating layer disposed on the second buffer layer, wherein a portion of the gate insulating layer corresponding to the second recess fits into the second recess and defines a third recess, and wherein the active layer is disposed in the gate insulating layer and a portion of the active layer is disposed in the third recess.
3. The array substrate of claim 1, wherein the array substrate comprises a first insulating layer and a second insulating layer, the first insulating layer is disposed on the second buffer layer and forms the third groove along with the second groove, the active layer is disposed on the first insulating layer and a portion of the active layer is located in the third groove to form a fourth groove, the second insulating layer is disposed on the first insulating layer and covers the active layer, and a portion of the second insulating layer is recessed along the fourth groove formed by the active layer to form a fifth groove.
4. The array substrate of claim 3, wherein the array substrate comprises a first gate layer and a second gate layer, the first gate layer is disposed at the bottom of the second recess and covered by the first insulating layer, and the second gate layer is disposed in the fifth recess.
5. The array substrate of claim 3, wherein the active layer comprises a U-shaped portion and conductor portions, the conductor portions are located on two sides of the U-shaped portion, the conductor portions are located on the first insulating layer and outside the third groove, and the U-shaped portion is located in the third groove and defines the fourth groove.
6. The array substrate of claim 5, wherein both sides of the U-shaped portion and the conductor portion are doped with P ions, and the conductor portion has a concentration of P ions that is greater than a concentration of P ions contained on both sides of the U-shaped portion.
7. The array substrate of claim 6, wherein the doping concentration of the P ions in the U-shaped part is gradually reduced along the depth direction of the third groove.
8. The array substrate of claim 5, further comprising an interlayer insulating layer and a source drain layer, wherein the interlayer insulating layer is disposed on the second insulating layer, the second insulating layer and the interlayer insulating layer are both provided with via holes, the via holes on the second insulating layer and the via holes on the interlayer insulating layer are communicated with each other to expose a portion of the conductor portion, and the source drain layer is disposed on the interlayer insulating layer and connected to the conductor portion through the via holes.
9. A preparation method of an array substrate is characterized by comprising the following steps:
depositing a first buffer layer on a substrate;
patterning the first buffer layer and forming a first groove;
depositing a second buffer layer on the first buffer layer and filling the first groove, wherein the second buffer layer fills the first groove and is sunk to form a second groove;
forming an active layer on the second buffer layer, the active layer covering a partial region of the second buffer layer and a portion of the active layer being depressed with the second groove.
10. The method for manufacturing the array substrate according to claim 9, wherein the forming of the active layer on the second buffer layer and the sinking of a portion of the active layer with the second groove comprise:
forming a first gate layer at the bottom of the second groove of the second buffer layer;
forming a first insulating layer on the second buffer layer, wherein a part of the first insulating layer sinks along with the second groove to form a third groove;
an active layer is formed on the first insulating layer, and a portion of the active layer is sunken with the third groove to form a fourth groove.
11. The method for manufacturing an array substrate according to claim 10, further comprising:
forming a second insulating layer on the first insulating layer, wherein the second insulating layer covers the active layer and is sunken along with the fourth groove to form a fifth groove;
forming a second gate layer on the second insulating layer, and the second gate layer fills the fifth groove;
and etching the part of the second gate layer outside the fifth groove to ensure that the second gate layer is only located in the fifth groove finally.
12. The method for manufacturing an array substrate according to claim 11, further comprising:
forming an interlayer insulating layer on the second insulating layer and the etched second gate layer, and etching the interlayer insulating layer and the second insulating layer to form mutually communicated via holes, wherein a part of the active layer is exposed out of the via holes;
and forming a source drain layer on the interlayer insulating layer, wherein the source drain layer penetrates through the through hole to be connected with the active layer.
13. A display device comprising the array substrate according to any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211667947.9A CN115763499A (en) | 2022-12-23 | 2022-12-23 | Array substrate, preparation method thereof and display device |
| PCT/CN2023/132703 WO2024131411A1 (en) | 2022-12-23 | 2023-11-20 | Array substrate and preparation method therefor, and display device |
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| CN202211667947.9A CN115763499A (en) | 2022-12-23 | 2022-12-23 | Array substrate, preparation method thereof and display device |
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| WO2024131411A1 (en) * | 2022-12-23 | 2024-06-27 | 武汉华星光电技术有限公司 | Array substrate and preparation method therefor, and display device |
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| CN107369693A (en) * | 2017-08-04 | 2017-11-21 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN111430382A (en) * | 2020-04-23 | 2020-07-17 | 上海天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
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|---|---|---|---|---|
| US7419858B2 (en) * | 2006-08-31 | 2008-09-02 | Sharp Laboratories Of America, Inc. | Recessed-gate thin-film transistor with self-aligned lightly doped drain |
| CN109378317A (en) * | 2018-10-12 | 2019-02-22 | 合肥鑫晟光电科技有限公司 | Array substrate and preparation method thereof, display device |
| CN113451411A (en) * | 2020-03-26 | 2021-09-28 | 深圳市柔宇科技有限公司 | Thin film transistor, manufacturing method thereof, display panel and electronic equipment |
| CN113540131B (en) * | 2021-09-15 | 2022-01-18 | 惠科股份有限公司 | Array substrate, display panel and preparation method of array substrate |
| CN114122026A (en) * | 2021-11-25 | 2022-03-01 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN115000087A (en) * | 2022-05-26 | 2022-09-02 | 武汉华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN115763499A (en) * | 2022-12-23 | 2023-03-07 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107369693A (en) * | 2017-08-04 | 2017-11-21 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display panel |
| CN111430382A (en) * | 2020-04-23 | 2020-07-17 | 上海天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024131411A1 (en) * | 2022-12-23 | 2024-06-27 | 武汉华星光电技术有限公司 | Array substrate and preparation method therefor, and display device |
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