CN115763495A - Array substrate, counter substrate and display panel - Google Patents

Abstract

The application relates to an array substrate, an opposite substrate and a display panel, wherein the array substrate comprises a plurality of repeated pixel units and a plurality of conductive wires, the repeated pixel units comprise at least two sub-pixels and at least two switch elements with opposite polarities, the conductive wires are located between every two adjacent repeated pixel units, and the two adjacent sub-pixels in the two adjacent repeated pixel units are respectively and electrically connected with the same conductive wire through the two switch elements with opposite polarities. The same conductive wire can be shared by two adjacent sub-pixels in two adjacent repeated pixel units, so that the number of the conductive wires and the wiring space can be reduced; meanwhile, the two switch elements with opposite polarities are electrically connected with the same conductive wire, so that the display control of the whole display panel can be realized, the aperture opening ratio and the light transmittance of the display panel can be improved while the manufacturing cost is not increased, and the competitiveness of the product is further improved.

Description

Array substrate, counter substrate and display panel

Technical Field

The present application relates to the field of display technologies, and in particular, to an array substrate, an opposite substrate, and a display panel.

Background

The light transmittance of an active Thin Film Transistor liquid crystal display (TFT-LCD) panel is an important optical index, and has positive effects of improving the brightness of the display panel and reducing the power consumption. Among them, the aperture ratio of the pixel greatly affects the transmittance of the display panel. In the conventional display panel, a Black Matrix (BM) is generally covered above the signal lines to block light and prevent light leakage due to disturbance of liquid crystal near the conductive lines, but the conventional display panel has a large number of signal lines, complicated wiring, and a large BM occupation area, which affects the aperture ratio of pixels and the light transmittance of the product.

Disclosure of Invention

The application aims at providing an array substrate, a counter substrate and a display panel, which can reduce the quantity of conducting wires and wiring space, and can improve the aperture ratio and the light transmittance of the display panel while not increasing the manufacturing process cost.

In a first aspect, an embodiment of the present application provides an array substrate, which includes a plurality of repeating pixel units and a plurality of conductive lines, where the repeating pixel units include at least two sub-pixels and at least two switch elements with opposite polarities, the conductive lines are located between two adjacent repeating pixel units, and two adjacent sub-pixels in the two adjacent repeating pixel units are electrically connected to a same conductive line through two switch elements with opposite polarities.

In one possible embodiment, one of the two switching elements with opposite polarities is a P-type thin film transistor, the other one is an N-type thin film transistor, and the P-type thin film transistor and the N-type thin film transistor are located on two sides of the conductive line and are arranged adjacently.

In a possible implementation manner, the drains of the P-type thin film transistor and the N-type thin film transistor are both U-shaped structures with openings, and the directions of the openings are opposite.

In a possible implementation mode, the working state of the P-type thin film transistor is that a low-level signal is turned on and a high-level signal is turned off; the working state of the N-type thin film transistor is that a high level signal is conducted and a low level signal is cut off.

In a possible implementation mode, when the level signal of the conducting wire is a first voltage, the N-type thin film transistor is conducted; when the level signal of the conducting wire is a second voltage, the P-type thin film transistor is conducted; when the level signal of the conducting wire is the third voltage, the P-type thin film transistor and the N-type thin film transistor are both turned off, and the absolute values of the first voltage, the second voltage and the third voltage are sequentially reduced.

In one possible implementation, the repeating pixel unit comprises two sub-pixels and P-type thin film transistors or N-type thin film transistors respectively and sequentially distributed along a column direction, the conductive line comprises a scanning line extending along a row direction, and the scanning line is positioned between two adjacent rows of repeating pixel units; the P-type thin film transistor and the N-type thin film transistor of two adjacent sub-pixels in two adjacent repeated pixel units in the column direction are respectively and electrically connected with the same scanning line.

In one possible implementation, the repeating pixel unit comprises two sub-pixels and P-type thin film transistors or N-type thin film transistors which are respectively and sequentially distributed along a row direction, the conductive line comprises a data line extending along a column direction, and the data line is positioned between two adjacent columns of repeating pixel units; the P-type thin film transistor and the N-type thin film transistor of two adjacent sub-pixels in two adjacent repeated pixel units in the row direction are respectively and electrically connected with the same data line.

In a possible implementation manner, the repeating pixel unit comprises four sub-pixels distributed in rows and columns and P-type thin film transistors or N-type thin film transistors corresponding to the sub-pixels, the conductive line comprises a scanning line extending along a row direction and a data line extending along a column direction, the scanning line is positioned between two rows of repeating pixel units adjacent to each other along the column direction, and the data line is positioned between two columns of repeating pixel units adjacent to each other along the row direction; the two P-type thin film transistors or the two N-type thin film transistors are arranged diagonally, and the P-type thin film transistors and the N-type thin film transistors of two adjacent sub-pixels in two adjacent repeated pixel units in the column direction are electrically connected with the same scanning line respectively; the P-type thin film transistor and the N-type thin film transistor of two adjacent sub-pixels in two adjacent repeated pixel units in the row direction are respectively electrically connected with the same data line.

In a second aspect, the present application provides a counter substrate, which is disposed opposite to the array substrate as described above, and on which a light-shielding layer is disposed, the light-shielding layer including a plurality of light-transmitting portions distributed in an array and a light-shielding portion located between the light-transmitting portions, the light-transmitting portions corresponding to sub-pixels of a repeating pixel unit of the array substrate, and an orthographic projection of the light-shielding portion on the array substrate at least covering the conductive line and the switching element.

In a third aspect, an embodiment of the present application provides a display panel, which includes the array substrate and the counter substrate as described above, and a liquid crystal layer located between the array substrate and the counter substrate.

According to the array substrate, the opposite substrate and the display panel provided by the embodiment of the application, the array substrate comprises a plurality of repeated pixel units and a plurality of conducting wires which are distributed in an array mode, each repeated pixel unit comprises at least two sub-pixels and at least two switch elements with opposite polarities, the conducting wires are located between every two adjacent repeated pixel units, and the two adjacent sub-pixels in the two adjacent repeated pixel units are electrically connected with the same conducting wire through the two switch elements with opposite polarities. The same conductive line can be shared by two adjacent sub-pixels in two adjacent repeated pixel units, so that the number of the conductive lines and the wiring space can be reduced; meanwhile, through optimizing the layout of the switch elements, the two switch elements with opposite polarities are electrically connected with the same conductive wire, the display control of the whole display panel can be realized, the aperture opening ratio and the light transmittance of the display panel can be improved while the manufacturing cost is not increased, and the competitiveness of products is further improved.

Drawings

Features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are provided with like reference numerals. The drawings are not necessarily to scale, and are merely intended to illustrate the relative positions of the layers, the thicknesses of the layers in some portions being exaggerated for clarity, and the thicknesses in the drawings are not intended to represent the proportional relationships of the actual thicknesses.

Fig. 1 illustrates a schematic structural diagram of a display panel provided in an embodiment of the present application;

fig. 2 is a schematic view illustrating a partial structure of an array substrate in the related art;

fig. 3 is a perspective view showing a light-shielding layer of an opposite substrate to the array substrate shown in fig. 2;

fig. 4 is a schematic diagram illustrating a pixel structure of an array substrate according to a first embodiment of the present disclosure;

fig. 5 is a schematic partial structural view of an array substrate according to a first embodiment of the present disclosure;

FIG. 6 shows an I-V plot of two switching elements of FIG. 5;

FIG. 7 illustrates voltage driving waveform diagrams of scan lines of FIG. 5;

fig. 8 is a perspective view showing a light-shielding layer of a counter substrate opposite to the array substrate shown in fig. 5;

fig. 9 is a schematic view illustrating a pixel structure of an array substrate according to a second embodiment of the present application;

fig. 10 is a schematic view illustrating a pixel structure of an array substrate according to a third embodiment of the present disclosure.

Description of reference numerals:

1. an array substrate; 11. a pixel electrode; px, sub-pixel; x, the row direction; y, the column direction; p1, a device region; p2, a pixel area; t, a switching element; PU, repeat pixel unit; G. scanning a line; D. a data line;

2. an opposing substrate; 21. an opposite common electrode; 22. a light-shielding layer; 22a, a light-transmitting portion; 22b, a light shielding portion;

3. and a liquid crystal layer.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 illustrates a schematic structural diagram of a display panel provided in an embodiment of the present application.

As shown in fig. 1, an embodiment of the present application provides a display panel, including: the liquid crystal display device includes an array substrate 1, a counter substrate 2 disposed opposite to the array substrate 1, and a liquid crystal layer 3 disposed between the array substrate 1 and the counter substrate 2. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, which are typically rod-shaped and both fluid like a liquid and have certain crystalline characteristics. When liquid crystal molecules are placed in an electric field, their alignment direction changes according to the change of the electric field.

Since the display panel is a non-emissive light receiving element, a light source needs to be provided through a backlight module disposed on a backlight surface side thereof. The display panel controls the rotation of liquid crystal molecules of the liquid crystal layer 3 by applying a driving voltage to the pixel electrode 11 of the array substrate 1 and the common electrode 21 of the opposite substrate 2, so as to refract light provided by the backlight module to generate a picture. In order to display a picture, a thin film transistor array is generally prepared on the array substrate 1 for driving the rotation of liquid crystal molecules and controlling the display of each sub-pixel Px.

Fig. 2 is a schematic diagram illustrating a pixel architecture of an array substrate in the related art, and fig. 3 is a perspective view illustrating a light-shielding layer of an opposite substrate opposite to the array substrate shown in fig. 2.

As shown in fig. 2 and 3, in the related art, the array substrate 1 includes a plurality of subpixels Px, each of which is controlled to be charged/discharged by one switching element T. However, since the level signal of the scanning line G changes, the electric field near the scanning line G is complicated, which causes disorder of the arrangement of liquid crystal molecules and easily causes a light leakage phenomenon, and therefore, a light shielding layer such as a black matrix BM is usually used to shield signal lines such as the scanning line. However, the existing signal lines are large in number, complex in wiring and large in occupied area of the light shielding layer, the aperture opening ratio of the pixels is reduced, and the light transmittance of the display panel is sacrificed.

In view of this, embodiments of the present disclosure provide an array substrate and an opposite substrate, which adopt an improved pixel structure, so as to reduce the number of signal lines and the wiring space, and improve the aperture ratio and the light transmittance of the display panel without increasing the manufacturing cost. The array substrate and the counter substrate provided in each embodiment are described below with reference to the drawings.

First embodiment

Fig. 4 is a schematic view illustrating a pixel structure of an array substrate according to a first embodiment of the present disclosure; fig. 5 is a schematic partial structure diagram of an array substrate according to a first embodiment of the present disclosure.

The array substrate 1 provided by the first embodiment of the present application includes a plurality of repeating pixel units PU distributed in an array and a plurality of conductive lines, where the repeating pixel unit PU includes at least two sub-pixels Px and at least two switching elements T with opposite polarities, the conductive lines are located between two adjacent repeating pixel units PU, and two adjacent sub-pixels Px in the two adjacent repeating pixel units PU are electrically connected to the same conductive line through the two switching elements T with opposite polarities, respectively.

As shown by the dotted line frames in fig. 4 and 5, in the plurality of repeated pixel units PU distributed in the array, each repeated pixel unit PU includes two sub-pixels Px, each sub-pixel Px includes an adjacent device region P1 and a pixel region P2, the pixel region P2 is provided with a pixel electrode 11, the light transmittance is high, and the device region P1 is provided with a switching element T, and the light transmittance is low. The conductive wire is located between two adjacent repeated pixel units PU, two adjacent sub-pixels Px in the two adjacent repeated pixel units PU share the same conductive wire, and the conductive wire can be omitted between the sub-pixels Px in the repeated pixel units PU, so that the number of the conductive wires can be greatly reduced, more spaces are reserved for the pixel area P2, and the pixel aperture ratio and the light transmittance are improved. In addition, the two switching elements T with opposite polarities are electrically connected to the same conductive line, and each sub-pixel Px in the adjacent repeating pixel unit PU can be charged or discharged through the same conductive line, so that the display control of the entire display panel can be realized.

The array substrate provided by the embodiment of the application comprises a plurality of repeating pixel units PU and a plurality of conductive wires, wherein the repeating pixel units PU are distributed in an array, each repeating pixel unit PU comprises at least two sub-pixels Px and at least two switching elements T with opposite polarities, the conductive wires are located between two adjacent repeating pixel units PU, and two adjacent sub-pixels Px in the two adjacent repeating pixel units PU are electrically connected with the same conductive wire through the two switching elements T with opposite polarities. Since the same conductive line can be shared by two adjacent sub-pixels Px in two adjacent repeating pixel units PU, the number of conductive lines and the wiring space can be reduced; meanwhile, by optimizing the layout of the switch elements T, the two switch elements T with opposite polarities are electrically connected with the same conductive wire, the display control of the whole display panel can be realized, the aperture opening ratio and the light transmittance of the display panel can be improved while the manufacturing cost is not increased, and the competitiveness of the product is further improved.

Furthermore, any one of the two switch elements T with opposite polarities is a P-type thin film transistor, the other one is an N-type thin film transistor, and the P-type thin film transistor and the N-type thin film transistor are located on two sides of the conductive line and are adjacently disposed. With such arrangement, the distance between the P-type thin film transistor or the N-type thin film transistor and the pixel electrode 11 in each repeating pixel unit PU can be made closer, the routing distance between the pixel electrode 11 and the drain electrode of the P-type thin film transistor or the N-type thin film transistor can be shortened, the cross-line or jumper design can be avoided, and the circuit design can be simplified.

Specifically, the P-type thin film transistor is a switching element T that mainly conducts Positive holes, where "P" of the P-type thin film transistor denotes Positive (Positive), and a hole-type semiconductor is formed by doping a small amount of an impurity, such as, but not limited to, trivalent boron (B) element, into intrinsic semiconductor silicon (Si). In contrast, the N-type thin film transistor is a switching element T mainly conducting electrons, wherein "N" of the N-type thin film transistor represents Negative electricity (Negative), which is an electronic type semiconductor formed by doping a small amount of impurities, such as, but not limited to, pentavalent phosphorus (P) element, into intrinsic semiconductor silicon (Si).

In some embodiments, the drains of the P-type thin film transistor and the N-type thin film transistor are both U-shaped structures having openings, and the directions of the openings are opposite. The drain electrodes of the P-type thin film transistor and the N-type thin film transistor are in U-shaped structures, so that a larger width-length ratio can be realized in a limited area, and the performance of the switching element T is improved. The drain openings of the P-type thin film transistor and the N-type thin film transistor are opposite in direction, so that the layout of a pixel framework can be more compact, and the wiring space is further saved.

Furthermore, the working state of the P-type thin film transistor is that a low-level signal is turned on and a high-level signal is turned off; the working state of the N-type thin film transistor is that a high level signal is conducted and a low level signal is cut off. Therefore, the P-type thin film transistor of a certain subpixel Px in the repeating pixel unit PU and the N-type thin film transistor of another subpixel Px in the adjacent repeating pixel unit PU share the same conductive line, so that each subpixel Px in the adjacent repeating pixel unit PU can be charged or discharged through the same conductive line, and the display control of the whole display panel can be realized.

Specifically, when the level signal of the conductive line is a first voltage, for example, a high level signal, the N-type thin film transistor is turned on; when the level signal of the conductive line is a second voltage, for example, a low level signal, the P-type thin film transistor is turned on; when the level signal of the conducting wire is a third voltage, the P-type thin film transistor and the N-type thin film transistor are both turned off, and the absolute values of the first voltage, the second voltage and the third voltage are sequentially reduced.

For example, at time t1, when the level signal of the conductive line is at a high level that meets the conduction requirement, the N-type thin film transistor is turned on, the liquid crystal capacitor corresponding to the subpixel Px in a certain row is charged, then the N-type thin film transistor is turned off, and the liquid crystal capacitor potential is maintained; at the time t2, when the level signal of the conductive line is at a low level meeting the conduction requirement, the P-type thin film transistor is turned on, the liquid crystal capacitor corresponding to the subpixel Px in a certain row is charged, then the P-type thin film transistor is turned off, and the liquid crystal capacitor potential is maintained. And at the time of t3, when the level signal of the conductive wire is a preset small value, the P-type thin film transistor and the N-type thin film transistor are both turned off, so that the charge and discharge control is realized.

In the first embodiment of the present application, the repeating pixel unit PU includes two sub-pixels Px sequentially distributed along the column direction Y and P-type thin film transistors or N-type thin film transistors respectively corresponding to the two sub-pixels Px, the conductive line includes a scanning line G extending along the row direction X, and the scanning line G is located between two adjacent rows of repeating pixel units PU. The P-type thin film transistor and the N-type thin film transistor of two adjacent subpixels Px in two adjacent repeating pixel units PU in the column direction Y are electrically connected to the same scanning line G, respectively.

In one example, as shown in fig. 5, two adjacent sub-pixels Px of the repeating pixel unit PU along the column direction Y may be symmetrically distributed with respect to the row direction X, but in other examples, the two adjacent sub-pixels Px may also be asymmetrically distributed with respect to the row direction X, which is within the protection scope of the present application. In addition, the scanning line G is located between two adjacent rows of the repeating pixel units PU, and the gates of the P-type thin film transistors and the N-type thin film transistors of two adjacent sub-pixels Px in two adjacent repeating pixel units PU share the same scanning line G, so that the number of the scanning lines G is halved, the wiring space is more compact correspondingly, more layout spaces are reserved for the pixel electrodes 11, the aperture ratio and the light transmittance of the display panel are improved, and the competitiveness of the product is further improved.

In addition, the array substrate 1 further includes a data line D extending along the column direction Y, and the data line D is located between two adjacent columns of the repeating pixel units PU. And when the P-type thin film transistor or the N-type thin film transistor is switched on, the liquid crystal capacitor corresponding to the sub-pixel Px in a certain row is charged through the data line D, then the N-type thin film transistor is switched off, and the potential of the liquid crystal capacitor is maintained.

FIG. 6 shows the I-V plot of two switching elements of FIG. 5; fig. 7 illustrates voltage driving waveform diagrams of the scan lines of fig. 5.

In some embodiments, when the level signal of the scan line G is the first voltage, the N-type thin film transistor controls the corresponding data line D to charge and discharge to the corresponding sub-pixel Px; when the level signal of the scanning line G is a second voltage, the P-type thin film transistor controls the corresponding data line D to charge and discharge to the corresponding subpixel Px; when the level signal of the scanning line G is the third voltage, both the P-type thin film transistor and the N-type thin film transistor are turned off, and the absolute values of the first voltage, the second voltage, and the third voltage are sequentially reduced.

As shown in fig. 4 to 7, the repeating pixel unit PU includes a first sub-pixel and a second sub-pixel that are adjacent to each other in the column direction Y and are symmetrically distributed, and the first sub-pixel is located above the second sub-pixel. The first sub-pixel corresponds to an N-type thin film transistor located in the device region P1, and the second sub-pixel corresponds to a P-type thin film transistor located in the device region P1. When the level signal of the scanning line G is a first voltage of 15V, the N-type thin film transistor controls the data line D to carry out charge-discharge control on the corresponding first sub-pixel; when the level signal of the scanning line G is the second voltage of-10V, the P-type thin film transistor controls the data line D to carry out charge and discharge control on the corresponding second sub-pixel. When the level signal of the scanning line G is the third voltage of-0.5V, the N-type thin film transistor and the P-type thin film transistor can be switched off under the voltage. Therefore, the control of the two subpixels Px in the repeated pixel unit PU can be realized, and the display control of the whole display panel can be further realized.

Fig. 8 is a perspective view showing a light-shielding layer of the counter substrate opposite to the array substrate shown in fig. 4.

As shown in fig. 8, the first embodiment of the present application further provides a counter substrate 2 disposed opposite to the array substrate 1, wherein a light shielding layer 22 is disposed on the counter substrate 2, the light shielding layer 22 includes a plurality of light transmitting portions 22a distributed in an array and light shielding portions 22b located between the light transmitting portions 22a, the light transmitting portions 22a correspond to the sub-pixels Px of the repeating pixel unit PU of the array substrate 1, and an orthogonal projection of the light shielding portions 22b on the array substrate 1 at least covers the conductive wires and the switching elements T.

Specifically, the conductive line is a scanning line G, the light-transmitting portion 22a of the light-shielding layer 22 corresponds to the pixel electrode 11 of each sub-pixel Px of the array substrate 1, and the light-shielding portion 22b can shield the scanning line G and each switching element T. In the first embodiment of the present application, the number of scanning lines G is halved by optimizing the layout of the switching elements T, and the corresponding wiring space is more compact, so that the area of the light shielding portion 22b that shields the scanning lines G and the respective switching elements T can be reduced, and the area of the light transmitting portion 22a can be increased.

According to simulation analysis and calculation, the pixel aperture ratio of the display panel adopting the design is improved by about 13.2%, the light transmittance is improved by about 12.2%, and the competitiveness of products is favorably improved.

Second embodiment

Fig. 9 is a schematic diagram illustrating a pixel structure of an array substrate according to a second embodiment of the present disclosure.

As shown in fig. 9, the second embodiment of the present application further provides an array substrate 1, which has a similar structure to the array substrate 1 of the first embodiment, except that the conductive line includes a data line D, the structure of the repeating pixel unit PU of the array substrate 1 is different, and the layout of two switching elements T shared by the same data line D is also different.

Specifically, as shown by a dashed-line frame in fig. 9, the repeating pixel unit PU includes two subpixels Px sequentially distributed in the row direction X and corresponding P-type thin film transistors or N-type thin film transistors, the conductive line includes a data line D extending in the column direction Y, and the data line D is located between two adjacent columns of repeating pixel units PU.

The P-type thin film transistor and the N-type thin film transistor of two adjacent subpixels Px in two adjacent repeating pixel units PU in the row direction X are electrically connected to the same data line D, respectively.

As shown in fig. 9, two adjacent sub-pixels Px of the repeating pixel unit PU along the row direction X may be symmetrically distributed with respect to the column direction Y, but in other examples, the two adjacent sub-pixels Px may also be asymmetrically distributed with respect to the column direction Y, which is within the protection scope of the present application. In addition, the data line D is located between two adjacent columns of the repeating pixel units PU, and the drain electrodes of the P-type thin film transistors and the N-type thin film transistors of two adjacent sub-pixels Px in two adjacent repeating pixel units PU share the same data line D, so that the number of the data line D is halved, the wiring space is more compact correspondingly, more layout spaces are reserved for the pixel electrodes 11, the aperture ratio and the light transmittance of the display panel are improved, and the competitiveness of the product is improved.

In addition, the array substrate further comprises a scanning line G extending along the row direction X, the scanning line G is located between two adjacent rows of the repeating pixel units PU, and gates of the P-type thin film transistors and the N-type thin film transistors in the repeating pixel units PU are respectively electrically connected with the two scanning lines G in the adjacent rows. When the P-type thin film transistor or the N-type thin film transistor is turned on, the liquid crystal capacitor corresponding to the subpixel Px in a certain row is charged through the data line D, then the P-type thin film transistor or the N-type thin film transistor is turned off, and the potential of the liquid crystal capacitor is maintained, so that charge and discharge control is realized.

Accordingly, the structure of the light-shielding layer 22 on the counter substrate 2 side opposite to the array substrate 1 is also adjusted accordingly.

Specifically, the light-shielding layer 22 is provided on the counter substrate 2, and an orthographic projection of the light-shielding layer 22 on the array substrate 1 covers the conductive lines and the device region P1 of each sub-pixel Px. Wherein the conductive line includes a data line D.

The light transmitting portion 22a of the light shielding layer 22 corresponds to the pixel electrode 11 of each sub-pixel Px of the array substrate 1, and the light shielding portion 22b can shield the data line D and each switching element T. In the second embodiment of the present application, by optimizing the layout of the switching elements T, the number of the data lines D is halved, and the corresponding wiring space is more compact, so that the area of the light shielding portion 22b that shields the data lines D and each switching element T can be reduced, the area of the light transmission portion 22a can be increased, the aperture opening ratio and the light transmittance of the display panel can be improved, and the competitiveness of the product can be improved.

Third embodiment

Fig. 10 is a schematic view illustrating a pixel structure of an array substrate according to a third embodiment of the present disclosure.

As shown in fig. 10, an array substrate 1 provided in the third embodiment of the present application has a similar structure to the array substrate 1 of the first embodiment or the second embodiment, except that the conductive lines include a scan line G and a data line D, and the number of sub-pixels Px of the repeating pixel unit PU of the array substrate 1 and the layout of the corresponding switching elements T are also different.

Specifically, as shown by the dashed line box in fig. 10, the repeating pixel unit PU includes four sub-pixels Px arranged in rows and columns and P-type thin film transistors or N-type thin film transistors respectively corresponding to the sub-pixels Px, the conductive line includes a scanning line G extending in the row direction X and a data line D extending in the column direction Y, the scanning line G is located between two rows of the repeating pixel units PU adjacent to each other in the column direction Y, and the data line D is located between two columns of the repeating pixel units PU adjacent to each other in the row direction X.

The two P-type thin film transistors or the two N-type thin film transistors are diagonally arranged, and the P-type thin film transistors and the N-type thin film transistors of two adjacent subpixels Px in two adjacent repeated pixel units PU in the column direction Y are electrically connected with the same scanning line G respectively.

The P-type thin film transistor and the N-type thin film transistor of two adjacent subpixels Px in two repeat pixel units PU adjacent in the row direction X are electrically connected to the same data line D, respectively.

As shown in fig. 10, the four subpixels Px of the repeating pixel unit PU may be distributed symmetrically with respect to the central point, or may be distributed asymmetrically with respect to the central point, which is within the protection scope of the present application. In addition, the scanning line G is located between two adjacent rows of the repeated pixel units PU along the column direction Y, the data line D is located between two adjacent columns of the repeated pixel units PU, and the P-type thin film transistors and the N-type thin film transistors of two adjacent sub-pixels Px in the two adjacent repeated pixel units PU share the same data line D and the same scanning line G, so that the number of the data line D and the number of the scanning line G are respectively halved, the wiring space is further reduced correspondingly, more arrangement spaces are reserved for the pixel electrodes 11, the aperture ratio and the light transmittance of the display panel are further improved, and the competitiveness of products is further improved.

When the P-type thin film transistor or the N-type thin film transistor is turned on, the liquid crystal capacitor corresponding to the subpixel Px in a certain row is charged through the data line D, then the P-type thin film transistor or the N-type thin film transistor is turned off, and the potential of the liquid crystal capacitor is maintained, so that charge and discharge control is realized.

Accordingly, the structure of the light-shielding layer 22 on the counter substrate 2 side facing the array substrate 1 is also adjusted accordingly.

Specifically, the counter substrate 2 is provided with a light-shielding layer 22, and an orthogonal projection of the light-shielding layer 22 on the array substrate 1 covers the conductive lines and the device region P1 of each sub-pixel Px. The conductive line includes a scan line G and a data line D.

The light transmitting portion 22a of the light shielding layer 22 corresponds to the pixel electrode 11 of each sub-pixel Px of the array substrate 1, and the light shielding portion 22b can shield the scanning line G, the data line D, and each switching element T. In the third embodiment of the present application, by optimizing the layout of the switch element T, the number of the scanning lines G and the number of the data lines D are respectively halved, and the corresponding wiring space is more compact, so that the area of the light shielding portion 22b shielding the scanning lines G, the data lines D and each switch element T can be reduced, the area of the light transmitting portion 22a can be increased, the aperture opening ratio and the light transmittance of the display panel can be further improved, and the competitiveness of the product can be improved.

It can be understood that the technical solution of the array substrate provided In the embodiments of the present application can be widely applied to various liquid crystal display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel.

It should be readily understood that "on 8230; \8230on", "on 8230;," on 82308230; \823030jaabove "and" on 8230; \8230on "in this application should be interpreted in the broadest manner so that" on 8230on "not only means" directly on something "but also includes the meaning of" on something "with intermediate features or layers in between, and" over "\8230: \8230or \8230: \8230, above" includes not only the meaning of "over" or "on" something, but also the meaning of "over" or "on" with no intervening features or layers therebetween (i.e., directly on something).

The term "substrate" as used herein refers to a material upon which subsequent layers of material are added. The substrate base plate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. Further, the base substrate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. An array substrate comprises a plurality of repeated pixel units distributed in an array and a plurality of conductive lines,

the repeating pixel unit comprises at least two sub-pixels and at least two switch elements with opposite polarities, the conductive line is located between two adjacent repeating pixel units, and two adjacent sub-pixels in the two adjacent repeating pixel units are respectively and electrically connected with the same conductive line through the two switch elements with opposite polarities.

2. The array substrate of claim 1, wherein one of the two switching elements with opposite polarities is a P-type thin film transistor and the other is an N-type thin film transistor, and the P-type thin film transistor and the N-type thin film transistor are disposed adjacent to each other on two sides of the conductive line.

3. The array substrate of claim 2, wherein the drains of the P-type thin film transistor and the N-type thin film transistor are both U-shaped with openings in opposite directions.

4. The array substrate of claim 2, wherein the P-type thin film transistor is operated in a low-level signal on state and a high-level signal off state; the working state of the N-type thin film transistor is that a high level signal is conducted and a low level signal is cut off.

5. The array substrate of any one of claims 2 to 4, wherein the N-type thin film transistor is turned on when the level signal of the conductive line is a first voltage; when the level signal of the conducting wire is a second voltage, the P-type thin film transistor is conducted; when the level signal of the conductive wire is a third voltage, the P-type thin film transistor and the N-type thin film transistor are both turned off, and the absolute values of the first voltage, the second voltage and the third voltage are sequentially reduced.

6. The array substrate of claim 5, wherein the repeating pixel unit comprises two sub-pixels and a corresponding P-type thin film transistor or N-type thin film transistor, the two sub-pixels are sequentially distributed along a column direction, the conductive line comprises a scan line extending along a row direction, and the scan line is located between two adjacent rows of the repeating pixel unit;

the P-type thin film transistor and the N-type thin film transistor of two adjacent sub-pixels in two adjacent repeated pixel units in the column direction are respectively and electrically connected with the same scanning line.

7. The array substrate of claim 5, wherein the repeating pixel unit comprises two sub-pixels and a corresponding P-type thin film transistor or N-type thin film transistor, the sub-pixels and the corresponding P-type thin film transistors or N-type thin film transistors are sequentially distributed along a row direction, the conductive line comprises a data line extending along a column direction, and the data line is located between two adjacent columns of the repeating pixel units;

the P-type thin film transistor and the N-type thin film transistor of two adjacent sub-pixels in two adjacent repeated pixel units in the row direction are respectively and electrically connected with the same data line.

8. The array substrate of claim 5, wherein the repeating pixel unit comprises four sub-pixels arranged in rows and columns and corresponding P-type or N-type thin film transistors, the conductive line comprises a scan line extending in a row direction and a data line extending in a column direction, the scan line is located between two adjacent rows of the repeating pixel units in the column direction, and the data line is located between two adjacent columns of the repeating pixel units in the row direction;

the two P-type thin film transistors or the two N-type thin film transistors are arranged diagonally, and the P-type thin film transistors and the N-type thin film transistors of two adjacent sub-pixels in two adjacent repeated pixel units in the column direction are electrically connected with the same scanning line respectively;

and the P-type thin film transistor and the N-type thin film transistor of two adjacent sub-pixels in two adjacent repeated pixel units in the row direction are respectively electrically connected with the same data line.

9. An opposite substrate arranged opposite to the array substrate according to any one of claims 1 to 8, wherein a light shielding layer is arranged on the opposite substrate, the light shielding layer comprises a plurality of light transmitting portions distributed in an array and a light shielding portion positioned between the light transmitting portions, the light transmitting portions correspond to sub-pixels of a repeating pixel unit of the array substrate, and an orthographic projection of the light shielding portion on the array substrate covers at least a conductive line and a switching element.

10. A display panel, comprising:

an array substrate according to any one of claims 1 to 8;

the counter substrate of claim 9; and

and the liquid crystal layer is positioned between the array substrate and the opposite substrate.

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