CN115763444A - Capacitor and chip - Google Patents

Abstract

The embodiment of the application provides a condenser and chip, and the condenser includes: the capacitor comprises a substrate, a well region, a first active region, a second active region, a first polycrystalline silicon region, a second polycrystalline silicon region, a third polycrystalline silicon region and a capacitor body. The substrate is doped with ions of a first type, the well region is formed on the surface of the substrate and extends from the surface of the substrate to the inside of the substrate, and the well region is doped with ions of a second type. The first type of ions is of opposite polarity to the second type of ions. The first active region is formed in a partial region above the well region, the first polycrystalline silicon region is deposited above the first active region, the second polycrystalline silicon region is deposited between the first active region and the second active region, and the third polycrystalline silicon region is deposited between two adjacent second active regions. The capacitor body is arranged in the upper area of the first polysilicon area. The capacitor is applied to a chip, so that the density of an active region and polycrystalline silicon of a capacitor region arranged in the chip can be improved, and the reliability of the chip is further improved.

Description

Capacitor and chip

Technical Field

The embodiment of the application relates to the field of chip design, in particular to a capacitor and a chip.

Background

MIM capacitors are widely used in various integrated circuits in semiconductor manufacturing because they provide better frequency and temperature dependent characteristics, reducing the difficulty and complexity of integration with CMOS front-end processes.

In the prior art, a MIM capacitor mainly includes a top metal, a first plate, and a second plate. The second polar plate is arranged between the first polar plate and the top metal layer, and the second polar plate is also connected with the top metal layer through the through hole.

However, such MIM capacitors are used in chips, which affects the reliability of the chips.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide a capacitor and a chip, which overcome the above problems or at least partially solve the problems that the MIM capacitor is applied to a chip, which affect the reliability of the chip.

According to a first aspect of embodiments of the present application, there is provided a capacitor including: the capacitor comprises a substrate, a well region, a first active region, a second active region, a first polycrystalline silicon region, a second polycrystalline silicon region, a third polycrystalline silicon region and a capacitor body. Wherein the substrate is doped with ions of a first type. The well region is formed on the surface of the substrate and extends from the surface of the substrate to the interior of the substrate. The well region is doped with a second type of ions, the first type of ions being of opposite polarity to the second type of ions. The first active region is formed on a part of the region above the well region. The first region of polycrystalline silicon is deposited above the first active region, the second region of polycrystalline silicon is deposited between the first active region and the second active region, and the third region of polycrystalline silicon is deposited between two adjacent second active regions. The capacitor body is arranged in the upper area of the polysilicon first area.

The capacitor provided by the embodiment of the application comprises a substrate, a well region, a first active region, a second active region, a first polycrystalline silicon region, a second polycrystalline silicon region, a third polycrystalline silicon region and a capacitor body. The capacitor is applied to a chip, so that the density of an active area of a capacitor area in the chip and the density of polycrystalline silicon can be improved, and the reliability of the chip is further improved.

In an alternative form, the capacitor body includes: a first polar plate, a second polar plate and a top metal. The second polar plate is arranged between the first polar plate and the top metal, and the top metal is electrically connected with the second polar plate.

In an alternative form, the capacitor further includes: the isolation structure is a hollow structure, and the capacitor body is accommodated in the isolation structure.

In the embodiment, the etching precision of the capacitor can be improved by arranging the isolation structure, and unnecessary parasitic capacitance generated between the peripheral device of the capacitor and the capacitor body can be reduced.

In an alternative mode, the isolation structure includes a first metal layer, the second active region is connected to the first metal layer through a first contact hole, and the third polysilicon region is connected to the first metal layer through a second contact hole.

Through the first contact hole and the second contact hole, the active region and the polycrystalline silicon can be connected together through the first metal layer, and the trap resistance is reduced.

In an alternative form, the sum of the area of the second region of polysilicon and the area of the third region of polysilicon is equal to the area of the second active region.

The first polysilicon region is deposited above the first active region, and the area of the first polysilicon region is equal to that of the first active region. When the sum of the area of the second region of the polysilicon and the area of the third region of the polysilicon is equal to the area of the second active region, the capacitor is used in a chip, the area of the polysilicon in the region where the capacitor is located in the chip can be equal to the area of the active region, the proportion of the polysilicon to the active region in the chip can be balanced, and therefore the performance of the chip is improved.

In an alternative mode, shallow trench isolation regions are formed below the polysilicon second region and the polysilicon third region.

In an optional manner, the isolation structure further includes a second metal layer, and the first metal layer in the isolation structure is connected to the second metal layer through the first via. The first metal layer and the first pole plate are formed on the basis of the same mask, and the second metal layer and the top metal layer are formed on the basis of the same mask.

The first metal layer and the second metal layer are formed on the side face of the capacitor body, and can surround the capacitor body from the side face, so that the whole noise resistance of the capacitor is enhanced. Moreover, the first metal layer and the first pole plate are formed on the basis of the same mask, and the second metal layer and the top metal layer are formed on the basis of the same mask, so that the etching precision of the capacitor can be improved, and the production cost of the capacitor is reduced.

In an optional manner, the isolation structure further includes a second metal layer and a third metal layer. The first metal layer in the isolation structure is connected with the second metal layer through the first through hole, and the second metal layer is connected with the third metal layer through the second through hole. The second metal layer and the first pole plate are formed on the basis of the same mask, and the third metal layer and the top metal layer are formed on the basis of the same mask.

The first metal layer, the second metal layer and the third metal layer are formed on the side face of the capacitor body, and can surround the capacitor body from the side face, so that the whole noise resistance of the capacitor is enhanced. And the second metal layer and the first pole plate are formed on the basis of the same mask, and the third metal layer and the top metal layer are formed on the basis of the same mask, so that the etching precision of the capacitor is improved, the first pole plate of the capacitor body can be far away from the substrate below, and the parasitic capacitance formed between the first pole plate and the substrate below can be reduced.

In an optional manner, the isolation structure further includes a fourth metal layer, the third metal layer is connected to the fourth metal layer through a third via, and the fourth metal layer is higher than the top metal layer.

By making the fourth metal layer higher than the top metal layer, the parasitic capacitance generated between other devices adjacent to the capacitor and higher than the capacitor body and the top metal layer can be reduced, and the overall noise immunity of the capacitor is further enhanced.

In an optional mode, a projection area of the third metal layer on the plane of the substrate is located in a projection area of the fourth metal layer on the plane of the substrate, and an area of the projection area of the fourth metal layer on the plane of the substrate is larger than an area of the projection area of the third metal layer on the plane of the substrate.

Therefore, the fourth metal layer can better surround the capacitor body, and the whole noise resistance of the capacitor is enhanced.

In an alternative mode, the projection of the fourth metal layer on the plane of the substrate and the projection of the capacitor body on the plane of the substrate have no overlapping area.

Therefore, the fourth metal layer does not exist right above the capacitor body, and when the overall noise resistance of the capacitor is enhanced, the parasitic capacitance generated between the top metal layer and the fourth metal layer can be greatly reduced.

In an alternative, the first type is P-type and the second type is N-type.

In an alternative, the first type is N-type and the second type is P-type.

The second aspect of the present application also provides a chip including the capacitor provided in the first aspect of the present application.

The chip provided by the application improves the density of the active area of the capacitor and the density of the polycrystalline silicon, and improves the reliability of the chip.

The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and the embodiments of the present application can be implemented according to the content of the description in order to make the technical means of the embodiments of the present application more clearly understood, and the detailed description of the present application is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic layout diagram of a polysilicon and an active region disposed below a capacitor body according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view of a capacitor provided in an embodiment of the present application.

Description of reference numerals:

01. a substrate; 02. a well region; 03. a first active region; 04. a second active region; 05. a first region of polycrystalline silicon; 06. a second region of polycrystalline silicon; 07. a third region of polysilicon; 08. a first metal layer; 09. a first contact hole; 10. shallow slot isolation area; 11. a first electrode plate; 12. a top metal layer; 13. a second polar plate; 14. a metal via; 15. a second metal layer; 16. a first through hole; 17. a third metal layer; 18. a second through hole; 19. a fourth metal layer; 20. and a third through hole.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

The terms "comprising" and "having," and any variations thereof, in the description and claims of this application and the description of the drawings are intended to cover, but not to exclude, other elements. The word "a" or "an" does not exclude a plurality.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The following description is given with the directional terms as they are used in the drawings and is not intended to limit the specific structure of a capacitor and a chip of the present application. For example, in the description of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, merely for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, are not to be considered limiting of the present application.

Further, expressions of directions indicated for explaining the operation and construction of each member of a capacitor and a chip of the present embodiment, such as the X direction, the Y direction, and the Z direction, are not absolute but relative, and although these indications are appropriate when each member of the capacitor and the chip is in the position shown in the drawings, when the position is changed, the directions should be interpreted differently to correspond to the change.

Furthermore, the terms "first," "second," and the like in the description and claims of this application or in the foregoing drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential order, either explicitly or implicitly, including one or more of the features.

In the description of the present application, unless otherwise specified, "plurality" means two or more (including two), and similarly, "plural" means two or more (including two).

In the description of the present application, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., "connected" or "connected" of a mechanical structure may refer to a physical connection, e.g., a physical connection may be a fixed connection, e.g., a fixed connection by a fastener, such as a screw, bolt, or other fastener; the physical connection can also be a detachable connection, such as a mutual clamping or clamping connection; the physical connection may also be an integral connection, for example, a connection made by welding, gluing or integrally forming the connection. "connected" or "connected" of circuit structures may mean not only physically connected but also electrically connected or signal-connected, for example, directly connected, i.e., physically connected, or indirectly connected through at least one intervening component, as long as the circuits are in communication, or communication between the interiors of two components; signal connection in addition to signal connection through circuitry, may also refer to signal connection through a media medium, such as radio waves. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

In the prior art, with the development of the semiconductor industry, capacitors are widely used in various integrated circuits. The inventor finds that, in the chip manufacturing process, it is necessary to achieve a certain ratio of the density of the active region to the density of the polysilicon in the entire chip, and also to achieve a certain ratio of the density of the active region to the density of the polysilicon in each region of the chip. However, in a partial region of the chip where the capacitor is disposed, the density of the active region and the density of the polysilicon in the region are low due to the large volume of the capacitor, which affects the reliability of the chip.

Therefore, some embodiments of the present application provide a capacitor, which can improve the reliability of a chip when applied to the chip. Referring to fig. 1 and fig. 2, fig. 1 is a schematic layout diagram of a polysilicon and an active region disposed below a capacitor body according to an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional diagram of a capacitor according to an embodiment of the present disclosure.

As shown in fig. 1 and fig. 2, a capacitor provided in an embodiment of the present application includes: the capacitor comprises a substrate 01, a well region 02, a first active region 03, a second active region 04, a polysilicon first region 05, a polysilicon second region 06, a polysilicon third region 07 and a capacitor body. Wherein the substrate 01 is doped with ions of a first type. The well region 02 is formed on the surface of the substrate 01 and extends from the surface of the substrate 01 to the inside of the substrate 01. The well region 02 is doped with ions of a second type, the first type of ions being of opposite polarity to the second type of ions. The first active region 03 is formed in a portion of the region above the well 02. A polysilicon first region 05 is deposited over the first active region 03, as shown in fig. 1, the polysilicon first region 05 has the same area as the first active region 03, and the polysilicon first region 05 completely covers the first active region 03. A second region 06 of polysilicon is deposited between the first active region 03 and the second active region 04 and a third region 07 of polysilicon is deposited between two adjacent second active regions 04. The capacitor body is disposed in an area above the polysilicon first region 05. For example, as shown in fig. 1, the polysilicon second region 06 includes 4 rectangular regions having the same shape, the polysilicon third region 07 includes 4 rectangular regions having the same shape, and the second active region 04 includes 4 rectangular regions having the same shape.

In practical applications, the first type of ions may be P-type ions, such as boron, gallium, indium, etc., or N-type ions, such as phosphorus, arsenic, etc. The second type of ions may be either N-type or P-type ions. If the first type is P-type ions, the substrate 01 is a P-type substrate; accordingly, the second type of ions are N-type ions and the well 02 is an N-type well. If the first type is N-type ions, the substrate 01 is an N-type substrate; accordingly, the second type of ions are P-type ions and the well 02 is a P-type well.

Referring to fig. 2, the capacitor body includes: a first plate 11, a second plate 13 and a top metal 12. The second plate 13 is disposed between the first plate 11 and the top metal 12, the first plate 11 and the second plate 13 are disposed in parallel, and the top metal 12 is electrically connected to the second plate 13. For example, the top metal layer 12 is electrically connected to the second plate 13 through a metal via 14, and the number of the metal vias 14 may be plural.

The capacitor provided by the embodiment of the application comprises a substrate 01, a well region 02, a first active region 03, a second active region 04, a first polysilicon region 05, a second polysilicon region 06, a third polysilicon region 07 and a capacitor body. When the capacitor is applied to a chip, the density of an active area of a capacitor area arranged in the chip and the density of polycrystalline silicon can be improved, and the reliability of the chip is further improved. In addition, polysilicon is filled between the capacitor body and the substrate 01, and noise coupling between the capacitor body and the substrate 01 can be well isolated.

In practical applications, the inventors have also found that the performance of the chip is not only related to the respective densities of the polysilicon and the active region, but also to the density ratio of the polysilicon and the active region.

Based on this, in this embodiment, referring to fig. 1, a polysilicon first region 05 is deposited over the first active region 03, wherein an area of the polysilicon first region 05 may occupy 70% to 90% of the total area of the layout, for example, an area of the polysilicon first region 05 may occupy 75% of the total area of the layout. Therefore, the percentage of the area of the polycrystalline silicon first region 05 and the area of the first active region 03 in the total area of the layout is large enough, so that the influence of the area of the polycrystalline silicon second region 06, the area of the polycrystalline silicon third region 07 and the area of the second active region 04 on the proportion of the total polycrystalline silicon and the total active region in the layout is smaller, and the proportion of the total polycrystalline silicon and the total active region in the layout is more easily balanced. The mode of arranging the polycrystalline silicon and the active region in the layout is arranged below the capacitor body, and the capacitor is used in a chip, so that the proportion of the polycrystalline silicon and the active region in the chip can be balanced, and the performance of the chip is improved.

On the basis of the above embodiment, the sum of the area of the polysilicon second region 06 and the area of the polysilicon third region 07 may be made equal to the area of the second active region 04.

Since the polysilicon first region 05 is deposited over the first active region 03, the area of the polysilicon first region 05 is equal to the area of the first active region 03. When the sum of the area of the second polysilicon region 06 and the area of the third polysilicon region 07 is also equal to the area of the second active region 04, the area of the polysilicon in the layout and the area of the active region can be made equal, so that the ratio of the polysilicon to the active region in the layout is more balanced. Furthermore, when the capacitor is used in a chip, the area of the polycrystalline silicon in the area where the capacitor is located in the chip can be equal to the area of the active area, so that the proportion of the polycrystalline silicon in the chip to the active area is balanced, and the performance of the chip is improved.

In some embodiments, shallow trench isolation regions 10 are formed beneath both the polysilicon second region 06 and the polysilicon third region 07.

In some embodiments, to reduce unnecessary parasitic capacitance generated between devices surrounding the capacitor and the capacitor body, the capacitor provided by the present application may further include an isolation structure. The isolation structure is a hollow structure, and the capacitor body can be accommodated in the isolation structure.

In the embodiment, the etching precision of the capacitor can be improved by arranging the isolation structure, and unnecessary parasitic capacitance generated between the peripheral device of the capacitor and the capacitor body can be reduced.

In the above embodiments, the capacitor includes the well region 02, and in order to prevent the well resistance from affecting the performance of the capacitor, the isolation structure provided in this embodiment may include the first metal layer 08. The second active region 04 is connected to the first metal layer 08 via a first contact hole 09, and the polysilicon third region 07 is connected to the first metal layer 08 via a second contact hole. The number of the first contact holes 09 and the number of the second contact holes can be multiple, so that the active region and the polycrystalline silicon are connected together through the first metal layer 08, and the trap resistance is reduced.

In one embodiment, the isolation structure may further include a second metal layer 15 to improve the overall noise immunity of the capacitor, considering that the capacitor may be affected by other devices. The first metal layer 08 in the isolation structure is connected to the second metal layer 15 through a first via 16, where the second metal layer 15 is higher than the first metal layer 08, a projection of the second metal layer 15 on the plane of the substrate 01 may completely coincide with a projection of the first metal layer 08 on the plane of the substrate 01, and there may be a plurality of first vias 16. The first metal layer 08 and the first electrode plate 11 are formed on the basis of the same mask, and the second metal layer 15 and the top metal layer 12 are formed on the basis of the same mask.

At this time, the first metal layer 08 and the second metal layer 15 are formed on the side surfaces of the capacitor body, and may surround the capacitor body from the side surfaces, enhancing the overall noise immunity of the capacitor. Moreover, the first metal layer 08 and the first electrode plate 11 are formed on the basis of the same mask, and the second metal layer 15 and the top metal layer 12 are formed on the basis of the same mask, so that the etching precision of the capacitor can be improved, and the production cost of the capacitor can be reduced.

It is to be noted that the capacitor provided in the above embodiment includes a metal material under the capacitor body, and the first plate 11 of the capacitor also includes a metal material, so that a parasitic capacitance that adversely affects the performance of the capacitor is liable to be generated therebetween.

Therefore, in an alternative manner, the isolation structure may further include the second metal layer 15 and the third metal layer 17. Wherein, the third metal layer 17 is higher than the second metal layer 15, and the projection of the third metal layer 17 on the plane of the substrate 01 is completely coincident with the projection of the second metal layer 15 on the plane of the substrate 01. The first metal layer 08 in the isolation structure is connected to the second metal layer 15 through a first via 16, the second metal layer 15 is connected to the third metal layer 17 through a second via 18, and the number of the first via 16 and the number of the second via 18 may be multiple. The second metal layer 15 is formed on the same mask as the first plate 11, and the third metal layer 17 is formed on the same mask as the top metal layer 12, in which case the second via 18 and the metal via 14 may be formed together.

The first metal layer 08, the second metal layer 15 and the third metal layer 17 are formed on the side surface of the capacitor body, and can surround the capacitor body from the side surface, so that the whole noise resistance of the capacitor is enhanced. Moreover, the second metal layer 15 and the first electrode plate 11 are formed on the basis of the same mask, and the third metal layer 17 and the top metal layer 12 are formed on the basis of the same mask, so that the etching precision of the capacitor is improved, the first electrode plate 11 of the capacitor body can be further away from the lower substrate 01, and the parasitic capacitance formed between the first electrode plate 11 and the lower substrate 01 can be reduced.

In an alternative way, referring to fig. 2, the isolation structure may further include a fourth metal layer 19, wherein the fourth metal layer 19 is higher than the third metal layer 17. The third metal layer 17 is connected to the fourth metal layer 19 through a third via 20, the number of the third vias 20 may be multiple, and the fourth metal layer 19 is higher than the top metal layer 12.

By making the fourth metal layer 19 higher than the top metal 12, the parasitic capacitance generated between other devices adjacent to the capacitor and higher than the capacitor body and the top metal 12 can be reduced, further enhancing the overall noise immunity of the capacitor.

In practical applications, in order to make the fourth metal layer 19 better surround the capacitor body, referring to fig. 2, a projection area of the third metal layer 17 on the plane of the substrate 01 may be located in a projection area of the fourth metal layer 19 on the plane of the substrate 01, and an area of the projection area of the fourth metal layer 19 on the plane of the substrate 01 is larger than an area of the projection area of the third metal layer 17 on the plane of the substrate 01. Therefore, the fourth metal layer 19 can better surround the capacitor body, and the whole noise resistance of the capacitor is enhanced.

It should be noted that, because the fourth metal layer 19 and the top metal layer 12 are both made of metal materials, parasitic capacitance is also generated between the two, and based on this, in this embodiment, there is no overlapping area between the projection of the fourth metal layer 19 on the plane of the substrate 01 and the projection of the capacitor body on the plane of the substrate 01. In this way, the fourth metal layer 19 does not exist right above the capacitor body, and the parasitic capacitance generated between the top metal layer 12 and the fourth metal layer 19 can be greatly reduced while enhancing the overall noise immunity of the capacitor.

It should be noted that, in practical applications, the isolation structure of the capacitor provided in this embodiment may include more metal layers according to actual requirements, and the first plate 11, the top metal 12 and the several metal layers are formed on the basis of the same mask, or may be changed. The present embodiment does not specifically limit this.

For example, the isolation structure of the capacitor may further include a fifth metal layer and a sixth metal layer, the sixth metal layer being higher than the fifth metal layer, the fifth metal layer being higher than the fourth metal layer 19. For example, the first plate 11 and the third metal layer 17 are formed on the basis of the same mask, and the top metal 12 and the fourth metal layer 19 are formed on the basis of the same mask. At this time, the sixth metal layer is the highest metal layer, and referring to the description of the foregoing embodiment, projections of the first metal layer 08, the second metal layer 15, the third metal layer 17, the fourth metal layer 19, and the fifth metal layer on the plane where the substrate 01 is located may all completely coincide, a projection area of the sixth metal layer on the plane where the substrate 01 is located may be larger than a projection area of the fifth metal layer on the plane where the substrate 01 is located, and a projection of the sixth metal layer on the plane where the substrate 01 is located and a projection of the capacitor body on the plane where the substrate 01 is located do not have an overlapping area.

That is, one skilled in the art may select the most suitable number of metal layers by combining the noise immunity of the capacitor, the size of the parasitic capacitance that may be generated, and the manufacturing cost, and the first plate 11, the top metal 12 and the several metal layers are formed on the same mask, which is not limited in the embodiment of the present application.

Another embodiment of the present application further provides a chip including the capacitor provided in any one of the above embodiments, and details described in the above embodiments are still applicable to this embodiment and are not described herein again.

The chip provided by the embodiment improves the density of the active area of the capacitor and the density of the polysilicon, and improves the reliability of the chip.

Those of skill in the art will understand that while some embodiments herein include certain features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims (14)

1. A capacitor, comprising: the capacitor comprises a substrate, a well region, a first active region, a second active region, a first polycrystalline silicon region, a second polycrystalline silicon region, a third polycrystalline silicon region and a capacitor body, wherein the substrate is provided with a first electrode and a second electrode;

the substrate is doped with ions of a first type;

the well region is formed on the surface of the substrate and extends from the surface of the substrate to the interior of the substrate; the well region is doped with ions of a second type; the first type of ions is of opposite polarity to the second type of ions;

the first active region is formed in a partial region above the well region;

the first polycrystalline silicon area is deposited above the first active area, the second polycrystalline silicon area is deposited between the first active area and the second active area, and the third polycrystalline silicon area is deposited between two adjacent second active areas;

the capacitor body is arranged in the upper area of the first polysilicon area.

2. The capacitor of claim 1, wherein the capacitor body comprises: the first polar plate, the second polar plate and the top metal;

the second polar plate is arranged between the first polar plate and the top layer metal, and the top layer metal is electrically connected with the second polar plate.

3. The capacitor of claim 2, further comprising:

the isolation structure is a hollow structure, and the capacitor body is accommodated in the isolation structure.

4. A capacitor according to claim 3, wherein the isolation structure comprises a first metal layer, the second active region is connected to the first metal layer through a first contact hole, and the polysilicon third region is connected to the first metal layer through a second contact hole.

5. The capacitor of claim 1 wherein the sum of the area of said second region of polysilicon and the area of said third region of polysilicon is equal to the area of said second active region.

6. The capacitor of claim 1 wherein shallow trench isolation regions are formed beneath both the polysilicon second region and the polysilicon third region.

7. The capacitor of claim 4, wherein the isolation structure further comprises a second metal layer, wherein the first metal layer in the isolation structure is connected to the second metal layer by a first via;

the first metal layer and the first polar plate are formed on the basis of the same mask;

the second metal layer and the top metal layer are formed on the basis of the same mask.

8. The capacitor of claim 4, wherein the isolation structure further comprises a second metal layer, a third metal layer, the first metal layer in the isolation structure being connected to the second metal layer through a first via, the second metal layer being connected to the third metal layer through a second via;

the second metal layer and the first polar plate are formed on the basis of the same mask;

the third metal layer and the top metal layer are formed on the basis of the same mask.

9. The capacitor of claim 8, wherein the isolation structure further comprises a fourth metal layer, the third metal layer connected to the fourth metal layer by a third via;

the fourth metal layer is higher than the top metal layer.

10. The capacitor according to claim 9, wherein a projection area of the third metal layer on the plane of the substrate is located within a projection area of the fourth metal layer on the plane of the substrate, and an area of the projection area of the fourth metal layer on the plane of the substrate is larger than an area of the projection area of the third metal layer on the plane of the substrate.

11. The capacitor of claim 10 wherein a projection of said fourth metal layer onto a plane of said substrate and a projection of said capacitor body onto a plane of said substrate are free of an overlap region.

12. The capacitor of claim 1, wherein the first type is P-type and the second type is N-type.

13. The capacitor of claim 1 wherein said first type is N-type and said second type is P-type.

14. A chip comprising a capacitor according to any one of claims 1 to 13.

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