CN115763421A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The electrical fuse element has a first portion, a second portion arranged at one end of the first portion, and a third portion arranged at the other end of the first portion. The resistor element is arranged separately from the electric fuse element. The material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and a lower layer of the second wiring. The wiring width of the second portion and the wiring width of the third portion are larger than the wiring width of the first portion.

Description

Semiconductor device and method for manufacturing the same

Cross Reference to Related Applications

The disclosure of japanese patent application No. 2021-143192, which was filed on 9/2/2021 and includes the specification, drawings and abstract, is incorporated herein by reference in its entirety.

Background

The present embodiment relates to a semiconductor device and a method of manufacturing the same.

The disclosed techniques are listed below.

[ patent document 1] Japanese patent application laid-open No. 2011-155192

For example, patent document 1 discloses a semiconductor device having a configuration in which resistivity does not change even when stress is applied. In patent document 1, a metal resistor element layer is formed in a region between a passivation film and an uppermost aluminum wiring. Therefore, a high-precision resistor element with less fluctuation in resistance value due to die stress after the packaging process can be realized, and a high-precision analog circuit can be formed.

Disclosure of Invention

However, in a semiconductor device in which various elements are mixed, further stabilization and miniaturization of characteristics are required.

Other objects and novel features will become apparent from the description of the specification and the drawings.

According to a semiconductor device according to an embodiment, a first metal film includes: a first portion, a second portion, and a third portion; the second portion is disposed at one end of the first portion; the third portion is disposed at the other end of the first portion. The second metal film is arranged separately from the first metal film. The material of each of the first metal film and the second metal film includes silicon metal or nickel chromium. The first metal film and the second metal film are arranged in an upper layer of the first wiring and a lower layer of the second wiring. Each of at least a part of the second portions and at least a part of the third portions has a wiring width larger than that of the first portions.

According to the semiconductor device according to the other embodiment, the material of the electrical fuse element that may become a fuse removal target when a specific circuit portion is replaced with a redundant circuit portion includes a silicon metal film or nickel chromium.

According to a method of manufacturing a semiconductor device according to an embodiment, it includes the following steps. A first wiring is formed. A first metal film is formed in an upper layer of the first wiring, the first metal film having a first portion, a second portion and a third portion, the second portion being disposed at one end of the first portion, the third portion being disposed at the other end of the first portion. A second metal film is formed in an upper layer of the first wiring, the second metal film being separated from the first metal film. A second wiring is formed in an upper layer of the first metal film and the second metal film. The material of each of the first metal film and the second metal film includes silicon metal or nickel chromium. The first metal film is formed such that each of at least a part of the second portion and at least a part of the third portion has a wiring width larger than a wiring width of the first portion. The first metal film and the second metal film are simultaneously formed.

According to the above embodiments, a semiconductor device having stable characteristics and suitable for miniaturization and a manufacturing method thereof can be realized.

Drawings

Fig. 1 is a plan view showing a configuration of a semiconductor device in a chip state according to an embodiment.

Fig. 2 is a plan view schematically showing the configuration of a semiconductor chip in which a redundant circuit is formed.

Fig. 3 is a diagram showing a circuit configuration with an electric fuse.

Fig. 4A is a sectional view taken along line IVA-IVA of fig. 5A, and fig. 4B is a sectional view taken along line IVB-IVB of fig. 5B.

Fig. 5A is a plan view showing the configuration of the resistor element, and fig. 5B is a plan view showing the configuration of the electrical fuse element.

Fig. 6A is a plan view showing the configuration of the resistor element, and fig. 6B is a plan view showing the configuration of the electric fuse element, in which the second wiring is omitted and the first wiring FI8 is added.

Fig. 7 is a plan view showing a configuration in which resistor elements are connected in parallel.

Fig. 8A is a sectional view showing a configuration in which the resistor element is electrically connected to the second wiring, and fig. 8B is a sectional view showing a configuration in which the electric fuse element is electrically connected to the second wiring.

Fig. 9A is a sectional view showing a first step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and fig. 9B is a sectional view showing a first step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

Fig. 10A is a sectional view showing a second step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and fig. 10B is a sectional view showing a second step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

Fig. 11A is a sectional view showing a third step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and fig. 11B is a sectional view showing a third step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

Fig. 12A is a sectional view showing a fourth step in the method of manufacturing a semiconductor device including a resistor element according to one embodiment, and fig. 12B is a sectional view showing a fourth step in the method of manufacturing a semiconductor device including an electric fuse element according to one embodiment.

Fig. 13A is a sectional view showing a fifth step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and fig. 13B is a sectional view showing a fifth step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the specification and the drawings, the same or corresponding components are denoted by the same reference numerals, and repeated description thereof will not be repeated. In the drawings, the configuration or manufacturing method may be omitted or simplified for convenience of explanation. Also, at least some embodiments and each modified example may be arbitrarily combined with each other.

The semiconductor device of the embodiment described below is not limited to the semiconductor chip, and may be a semiconductor wafer before being divided into semiconductor chips, or may be a semiconductor package in which semiconductor chips are sealed with resin. Further, a plan view in this specification refers to a viewpoint viewed from a direction perpendicular to the surface of the semiconductor substrate.

Arrangement of semiconductor devices in chip state

First, a configuration in a chip state will be described with reference to fig. 1 as a configuration of the semiconductor device in the present embodiment.

As shown in fig. 1, the semiconductor device SC in the present embodiment is, for example, a microcomputer. The semiconductor device SC is, for example, in a chip state, and has a semiconductor substrate. The electrical element is arranged on and above the semiconductor substrate. The semiconductor device SC includes, for example, a RAM (random access memory) region RA, a redundant circuit region RB, a power supply circuit region RC, a CPU (central processing unit) region RD, and a peripheral circuit region RE. The power supply circuit region RC has, for example, an oscillation circuit region RF. The semiconductor device SC has a plurality of pad electrodes PD. Each of the plurality of pad electrodes PD is electrically connected to an electric element arranged in the semiconductor device SC.

The oscillation circuit is arranged in the oscillation circuit region RF. For example, the oscillation circuit generates an output signal of a predetermined oscillation period by an oscillation operation of repeated charging and discharging of the capacitive element. The oscillation circuit is, for example, a HOCO (high speed on-chip oscillator) circuit, but may also be a LOCO (low speed on-chip oscillator) circuit, and may include both the HOCO circuit and the LOCO circuit.

The oscillation circuit has a constant current circuit for outputting a signal of a constant voltage level, the constant current circuit including a resistor element. The oscillation circuit has a differential amplifier circuit in which a resistor element is further included. Resistor elements are also included in other circuits.

The spare redundancy circuit part is arranged in the redundancy circuit region RB. The spare redundant circuit part has the same function as the specific circuit part having the predetermined function. In order to replace a specific circuit portion among the redundant circuit portions, an electrical fuse to be blown and removed is provided.

Configuration and function of redundant circuit portion and electric fuse

Next, the configuration and function of the redundancy circuit portion and the electric fuse will be described with reference to fig. 2 and 3.

As shown in fig. 2, a plurality of blocks (specific circuit portions) N1, N2. Each of the plurality of blocks N1, N2. Each of the plurality of blocks N1, N2, ·, nm is configured, for example, by a plurality of memory cells in the RAM area RA (fig. 1).

A fusible link H1, H2,. And Hm is formed to disable each of the plurality of blocks N1, N2,. And Nm. Spare redundant blocks RED having the same function are arranged so as to be able to replace any of the inactive blocks N1, N2. The redundancy block RED is arranged in the redundancy circuit region RB shown in fig. 1.

The potential of the ground power supply GD is applied to a gate electrode of a MOS (metal oxide semiconductor) transistor TR via a fuse Hs. Therefore, the MOS transistor TR is kept in a non-conductive state. Therefore, the redundant blocks RED are electrically separated in the semiconductor device SC.

In addition, the test pad electrodes PDa, PDb are arranged to detect defects in each of the plurality of blocks N1, N2.

Next, a functional test of the semiconductor device configured as described above will be described. Here, a case where the fuse is blown and removed by energization will be described.

First, an electric signal from a not-shown function test apparatus (hereinafter also referred to as a tester) is applied via the test pad electrodes PDa, PDb. If the semiconductor device SC is normal, an expected signal for the applied electric signal is output from the test pad electrodes PDa, PDb. At this time, the tester determines whether the semiconductor device SC is good or defective based on the relationship between the electrical signal applied to the semiconductor device SC and the electrical signal output. If any of the blocks N1, N2,. And Nm is determined to be defective, the defective block and the redundant block RED are replaced. This ensures the possibility that the semiconductor device SC satisfies the function that it should realize, thereby creating a good product to which the semiconductor device SC will be.

The replacement of the defective block and the redundant block RED is performed as follows. When a defect of the block N1 is detected by the above-described functional test, for example, the fuses H1 and Hs are blown and removed by power-on. The defective block N1 is electrically separated in the semiconductor device SC due to the blown fuse H1.

On the other hand, with the fuse Hs blown, the voltage of the power supply PV is applied to the gate electrode of the MOS transistor TR via the resistor RR. This causes the MOS transistor TR to become on state and the defective block N1 is replaced by the redundant block RED.

Next, the fuse removal of the electrical fuse element that is blown and removed by power-on will be described with reference to fig. 3.

As shown in fig. 3, the electric fuse element EH is a fuse that is cut by flowing a current, not by irradiating a laser beam. As a switching element for causing a current to flow to the electric fuse element EH, a cut transistor CT is provided.

One end of the electric fuse element EH is electrically connected to the power supply voltage (Vdd). The other end of the electric fuse element EH is electrically connected to the drain D of the cut transistor CT. The source S of the cut-off transistor CT is connected to the ground potential (GND).

The level shifter LS is electrically connected to the gate G of the cut-off transistor CT. The level shifter LS inputs a signal for turning on and off the cut-off transistor CT to the gate G of the cut-off transistor CT. The core portion CO is electrically connected to each of the other end of the electric fuse element EH and the drain of the cut-off transistor CT.

If any of the blocks N1, N2,. -, nm (fig. 2) is determined to be defective, the cut-off transistor CT is turned on by the level shifter LS. Accordingly, a current flows through the electric fuse element EH, and the electric fuse element EH is blown and removed. The core portion CO is a determination circuit for determining the state of the electrical fuse element EH, and if it is determined that the electrical fuse element EH has been blown and removed, replacement is performed based on the determination result.

Arrangement of resistor element and electric fuse element

Next, the configuration of the resistor element and the electric fuse element included in the semiconductor device of the present embodiment will be described with reference to fig. 4A to 8B. As described above, the resistor element is arranged, for example, in the oscillation circuit region RF in fig. 1, but the resistor element is not limited thereto, and may be arranged in another region.

As shown in fig. 4A and 4B, the first wiring FI is disposed on an interlayer dielectric layer (not shown). The first wiring FI is made of a conductor such as a metal (including an alloy). The first wiring FI is made of, for example, aluminum (Al), copper (Cu), aluminum-copper (AlCu), or the like. The first wiring FI is an electric wire that transmits an electric signal. However, the first wiring FI may be a dummy wiring. The dummy wiring is a wiring that is electrically isolated from other electric elements and does not transmit an electric signal.

As shown in fig. 4A, the interlayer dielectric layer I1 is disposed to cover the first wiring FI. The upper surface of the interlayer dielectric layer I1 is planarized. The via Va1 is provided in the interlayer dielectric layer I1. The via Va1 reaches the first wiring FI from the upper surface of the interlayer dielectric layer I1. The via conductive layer Vca1 is embedded in the via Va 1. The via conductive layer Vca1 is made of, for example, tungsten (W).

A resistor element RS (second metal film) is arranged on the upper surface of the interlayer dielectric layer I1. The resistor element RS is made of, for example, metal (including alloy), such as silicon metal, nickel chromium (NiCr), or the like. The silicon metal is, for example, silicon chromium (SiCr) or carbon-doped silicon chromium (SiCrC).

Each of one end and the other end of the resistor element RS is electrically connected to the first wiring FI via the via conductive layer Vca 1. Specifically, one end of the resistor element RS is electrically connected to the first wiring FI1 via the via conductive layer Vca1, and the other end of the resistor element RS is electrically connected to the first wiring FI4 via the via conductive layer Vca 1.

The interlayer dielectric layer I2 is arranged to cover the resistor element RS. The upper surface of the interlayer dielectric layer I2 is planarized. A via V2 is provided to reach the first wiring FI from the upper surface of the interlayer dielectric layer I2 through the interlayer dielectric layers I2, I1. The via conductive layer Vc2 is embedded in the via V2. The via conductive layer Vc2 is made of tungsten, for example.

The second wiring SI is arranged on the upper surface of the interlayer dielectric layer I2. The second wiring SI is made of a conductor such as a metal (including an alloy). The second wiring SI is made of, for example, aluminum, copper, aluminum-copper, or the like. The second wiring SI is an electric wire that transmits an electric signal. However, the second wiring SI may be a dummy wiring that is electrically isolated from other electrical elements and does not transmit an electrical signal.

One second wiring SI of the plurality of second wirings SI is electrically connected to the first wiring FI via the via conductive layer Vc 2. Specifically, the second wiring SI1 is electrically connected to the first wiring FI4 via the via conductive layer Vc 2. The interlayer dielectric layer I3 is arranged to cover the second wiring SI. The upper surface of the interlayer dielectric layer I3 is planarized.

As shown in fig. 4B, a via hole Vb1 is provided in the interlayer dielectric layer I1. The via Vb1 reaches the first wiring FI from the upper surface of the interlayer dielectric layer I1. The via conductive layer Vcb1 is embedded in the via Vb 1. The via conductive layer Vcb1 is made of tungsten, for example.

The electric fuse element EH (first metal film) is arranged on the upper surface of the interlayer dielectric layer I1. The electric fuse element EH is made of, for example, metal (including alloy), and is made of, for example, silicon metal, nickel chromium, or the like. The silicon metal is, for example, silicon chromium or silicon chromium with carbon incorporated therein.

Each of one end and the other end of the electric fuse element EH is electrically connected to the first wiring FI via the via conductive layer Vcb 1. Specifically, one end of the electric fuse element EH is electrically connected to the first wiring FI6 via the via conductive layer, and the other end of the electric fuse element EH is electrically connected to the first wiring FI7 via the via conductive layer Vcb 1.

The interlayer dielectric layer I2 is arranged to cover the electric fuse element EH. The upper surface of the interlayer dielectric layer I2 is planarized. The second wiring SI may be disposed on an upper surface of the interlayer dielectric layer I2. However, preferably, the second wiring SI is not arranged in a region directly above the electric fuse element EH. Because if the electric fuse element EH is blown and removed, the second wiring SI located directly above the electric fuse element EH may be damaged by the blowing removal. The interlayer dielectric layer I3 is disposed on the interlayer dielectric layer I2. As described above, the upper surface of the interlayer dielectric layer I3 is planarized.

As shown in fig. 4A and 4B, each of the resistor element RS and the electric fuse element EH is arranged in an upper layer of the first wiring FI and a lower layer of the second wiring SI. The resistor element RS and the electric fuse element EH are arranged in the same layer, and have the same composition.

As shown in fig. 5A, the resistor element RS may include, for example, a plurality of resistor portions RSa, RSb, RSc, and RSd (a plurality of metal portions). Each of the plurality of resistor portions RSa to RSd is made of, for example, metal (including alloy), and is made of, for example, silicon metal, nickel chromium, or the like. The silicon metal is for example silicon chromium or silicon chromium into which carbon has been introduced. The resistor element RS is not limited to the four resistor sections RSa to RSd, and may have two, three, or five or more resistor sections.

The plurality of resistor parts RSa to RSd may be connected in series. In this case, the plurality of resistor sections RSa to RSd are connected in the order of the resistor section RSa, the resistor section RSb, the resistor section RSc, and the resistor section RSd.

Specifically, one end of the resistor portion RSa in the longitudinal direction is electrically connected to one end of the resistor portion RSb in the longitudinal direction via the first wiring FI 1. The other end of the resistor portion RSb in the longitudinal direction is electrically connected to one end of the resistor portion RSc in the longitudinal direction via the first wiring FI 2. The other end of the resistor portion RSc in the longitudinal direction is electrically connected to one end of the resistor portion RSd in the longitudinal direction via the first wiring FI 3.

Preferably, the resistor element RS is arranged to bend in a plan view. The longitudinal direction of each of the plurality of resistor sections RSa to RSd is, for example, along the same direction, and is parallel to each other. In this arrangement, the resistor element RS is configured to be bent in a plan view by the ends of the resistor portions adjacent to each other in the longitudinal direction being electrically connected via the above-described first wirings FI1 to FI 3.

If the resistor element RS is bent in a plan view, the longitudinal direction of each of the plurality of resistor portions RSa to RSd may not be in the same direction as each other.

In the plan view, the other end portion of the resistor portion RSa in the longitudinal direction is electrically connected to the second wiring SI1 via the first wiring FI4. Also in the plan view, the other end portion of the resistor portion RSd in the longitudinal direction is electrically connected to the second wiring SI2 via the first wiring FI 5.

As shown in fig. 5B, the electric fuse element EH is arranged separately from the resistor element RS. The electric fuse element EH has a first portion P1, a second portion P2, and a third portion P3. The second portion P2 is disposed at one end of the first portion P1. The third portion P3 is disposed at the other end of the first portion P1. The first portion P1 is sandwiched between the second portion P2 and the third portion P3.

At least a part of each of the second portion P2 and the third portion P3 has a wiring width W2, W3 larger than the wiring width W1 of the first portion P1. In the present embodiment, each of the maximum wiring width W2 of the second portion P2 and the maximum wiring width W3 of the third portion P3 is larger than the wiring width W1 of the first portion P1.

The second portion P2 has a taper portion TP2 and a pad portion PD2 in a plan view. The tapered portion TP2 is connected to the first portion P1. The pad portion PD2 is connected to the taper portion TP2. The taper portion TP2 is disposed between the first portion P1 and the pad portion PD2. The tapered portion TP2 is configured such that the wiring width gradually increases from the first portion P1 toward the pad portion PD2 in a plan view. The pad portion PD2 has, for example, a rectangular shape in plan view.

The third portion P3 has a taper portion TP3 and a pad portion PD3 in a plan view. The tapered portion TP3 is connected to the first portion P1. The pad portion PD3 is connected to the taper portion TP3. The taper portion TP3 is disposed between the first portion P1 and the pad portion PD3. The tapered portion TP3 is configured such that the wiring width gradually increases from the first portion P1 toward the pad portion PD3 in a plan view. The pad portion PD3 has, for example, a rectangular shape in plan view. The pad portions PD2, PD3 may be directly connected to the first portion P1 without the taper portions TP2, TP3.

The pad portion PD2 is electrically connected to the first wiring FI6 via the via hole Vb 1. The pad part PD3 is electrically connected to the first wiring FI7 via the via hole Vb 1.

As shown in fig. 5A and 5B, the wiring width W1 of the first portion P1 in the electric fuse element EH is smaller than the wiring width WB of each of the plurality of resistor portions RSa to RSd. Preferably, the wiring widths WB of the plurality of resistor portions RSa to RSd are the same, but they may be different from each other.

As shown in fig. 4A and 4B, the wiring length LB of the electric fuse element EH is smaller than the wiring length LA of the resistor element RS. As shown in fig. 5A and 5B, when the resistor element RS is formed of the plurality of resistor portions RSa to RSd connected in series, the wiring length LB of the electric fuse element EH is smaller than the sum of the wiring lengths LA of the plurality of resistor portions RSa to RSd.

In the plan view shown in fig. 6B, the area of a region (hatched region in the drawing) where the first wiring FI and the electric fuse element EH overlap is smaller than the area of a region (hatched region in the drawing) where the first wiring FI and the resistor element RS overlap in the plan view shown in fig. 6A. By thus reducing the area of the first wiring FI8 overlapping the electric fuse element EH in a plan view, the electric fuse element EH is less likely to be radiated, and it is likely to be blown.

Incidentally, as shown in fig. 6A, when there are a plurality of regions where the resistor element RS overlaps the first wiring FI, the sum of the areas of the plurality of overlapping regions is compared with the area of the overlapping region between the first wiring FI and the electric fuse element EH. Similarly, when there are a plurality of overlapping regions of the first wiring FI and the electric fuse element EH, the sum of the areas of the plurality of overlapping regions is compared with the area of the overlapping region of the first wiring FI and the resistor element RS.

Further, in fig. 6B, in order to clarify an overlapping region between the electric fuse element EH and the first wiring FI, a configuration is shown in which the first wiring FI8 is provided below the electric fuse element EH. However, in a region directly below the electric fuse element EH, the first wiring FI8 may not be provided as shown in fig. 4B and 5B.

As shown in fig. 7, when the resistor element RS is formed of the plurality of resistor portions RSa to RSd, the plurality of resistor portions RSa to RSd may be connected in parallel with each other. In this case, the longitudinal directions of each of the plurality of resistor portions RSa to RSd are parallel to each other, for example, along the same direction. In this arrangement, one end portions of the plurality of resistor portions RSa to RSd are electrically connected to each other via the via V1 through the first wiring FI11. The other end portions of the plurality of resistor portions RSa to RSd are electrically connected to each other through the via V1 by another first wiring FI12. The second wiring SI11 is electrically connected to the first wiring FI11 via the via hole V2. The second wiring SI12 is electrically connected to the first wiring FI12 via the via V2.

If the plurality of resistor portions RSa to RSd are connected in parallel with each other, the longitudinal directions of the plurality of resistor portions RSa to RSd may not be along the same direction.

As shown in fig. 8A and 8B, each of the resistor element RS and the electric fuse element EH may be electrically connected to the second wiring SI. In this case, the resistor element RS is electrically connected to the second wiring SI through the via conductive layer Vca3 embedded in the via Va3, the via Va3 being provided in the interlayer dielectric layer I2. The electric fuse element EH is electrically connected to the second wiring SI through a via conductive layer Vcb3 embedded in a via Vb3, the via Vb3 being provided in the interlayer dielectric layer I2.

Method for manufacturing semiconductor device

Next, a method of manufacturing a semiconductor device of the present embodiment will be described with reference to fig. 4A and 9A to 13B.

First, a semiconductor substrate (not shown) is prepared. Electrical elements (not shown), such as MOS transistors (not shown), are formed on the surface of the semiconductor substrate. An interlayer dielectric layer is formed on a surface of the semiconductor substrate to cover the electrical elements formed on the surface of the semiconductor substrate. The wiring is formed on the interlayer dielectric layer. By repeatedly forming the interlayer dielectric layer and the wiring, a multilayer wiring structure is formed.

As shown in fig. 9A and 9B, the first wiring FI is formed as one wiring of the multilayer wiring structure. The first wiring FI is formed, for example, by forming a metal (aluminum, copper, aluminum-copper, or the like) on an interlayer dielectric layer and patterning using a photolithography technique, an etching technique, or the like.

As shown in fig. 10A and 10B, an interlayer dielectric layer I1 is formed to cover the first wiring FI. The interlayer dielectric layer I1 is made of, for example, silicon oxide (SiO) ₂ ) And (4) preparing. Thereafter, CMP (chemical mechanical polishing) is performed. Accordingly, the upper surface of the interlayer dielectric layer I1 is planarized.

Thereafter, vias Va1, vb1 are formed in the interlayer dielectric layer I1 by a photolithography technique. Each of the vias Va1, vb1 is formed to reach the first wiring FI from the upper surface of the interlayer dielectric layer I1.

Thereafter, a conductive layer for embedding is formed on the upper surface of the interlayer dielectric layer I1 to embed each of the vias Va1, vb 1. The conductive layer used for embedding is, for example, tungsten. A barrier metal layer may be formed between the conductive layer for embedding and the interlayer dielectric layer. The barrier metal layer is, for example, titanium nitride (TiN).

Thereafter, CMP is performed on the upper surface of the conductive layer for embedding. Accordingly, the upper surface of the interlayer dielectric layer I1 is exposed, and a conductive layer for embedding remains inside each of the vias Va1, vb 1. The via conductive layers Vca1, vcb1 are formed of conductive layers for embedding that remain inside each of the vias Va1, vb 1.

As shown in fig. 11A and 11B, a metal layer SM is formed on the upper surface of the interlayer dielectric layer I1 by, for example, sputtering. The metal layer SM is formed of, for example, metal silicon (SiCr, siCrC), nickel chromium, or the like.

As shown in fig. 12A and 12B, a photoresist (organic photosensitive film) PR is applied on the metal layer SM. The photoresist PR is patterned into a predetermined shape by exposure and development. The metal layer SM is etched using the patterned photoresist PR as a mask.

The metal layer SM is patterned by this etching, and the resistor element RS and the electric fuse element EH from the metal layer SM are simultaneously formed. The resistor element RS and the electric fuse element EH are formed separately from each other. Therefore, the resistor element RS and the electric fuse element EH are arranged in the same layer, and have the same composition.

The resistor element RS is formed to be electrically connected to the first wiring FI via the via conductive layer Vca1 embedded in the via Va 1. The electric fuse element EH is formed to be electrically connected to the first wiring FI via the via conductive layer Vcb1 embedded in the via Vb 1. Thereafter, the photoresist PR is removed by ashing or the like.

As shown in fig. 13A and 13B, thereafter, an interlayer dielectric layer I2 is formed on the interlayer dielectric layer I1 to cover the resistor element RS and the electric fuse. The interlayer dielectric layer I2 is formed of, for example, silicon oxide. Then, CMP is performed on the upper surface of the interlayer dielectric layer I2. Then, the upper surface of the interlayer dielectric layer I2 is planarized.

Thereafter, vias V2 are formed in the interlayer dielectric layers I1, I2 by photolithography and etching techniques. The via hole V2 is formed to reach the first wiring FI from the upper surface of the interlayer dielectric layer I2.

Thereafter, a conductive layer for embedding is formed on the upper surface of the interlayer dielectric layer I2 due to the embedded via V2. The conductive layer used for embedding is, for example, tungsten. A barrier metal layer may be formed between the conductive layer for embedding and the interlayer dielectric layer. The barrier metal layer is, for example, titanium nitride.

Thereafter, CMP is performed on the upper surface of the conductive layer for embedding. Accordingly, the upper surface of the interlayer dielectric layer I2 is exposed, and the conductive layer for embedding remains inside the via hole V2. The via conductive layer Vc2 is formed of a conductive layer for embedding remaining within the via V2.

As shown in fig. 4A and 4B, as one wiring of the multilayer wiring structure, a second wiring SI is formed on the upper surface of the interlayer dielectric layer I2. The second wiring SI is formed by forming a metal (aluminum, copper, aluminum-copper, or the like) on the interlayer dielectric layer I2 and patterning by a photolithography technique, an etching technique, or the like.

The interlayer dielectric layer I3 is formed to cover the second wiring SI. The interlayer dielectric layer I3 is formed of, for example, silicon oxide. Then, CMP is performed on the upper surface of the interlayer dielectric layer I3. Accordingly, the upper surface of the interlayer dielectric layer I3 is planarized.

As described above, the semiconductor device of the present embodiment shown in fig. 4A and 4B is manufactured.

Effect

In the present embodiment, the sheet resistance value of metallic silicon (silicon chrome) used as the material of the metal films EH and RS is 300 to 1300 Ω/sq. The sheet resistance value of nickel chromium used as a material for the metal films EH and RS is 5 to 200 Ω/sq. On the other hand, the sheet resistance value of polysilicon was 360 Ω/sq. Due to the above characteristics, silicon metal (silicon chrome) and nickel chrome may be fused with a cutting current smaller than that of polysilicon.

According to the present embodiment, as shown in fig. 5B, each of the second portion P2 and the third portion P3 of the metal film EH has a width wider than the first portion P1. Therefore, the metal film EH can be used as the electric fuse element EH, for example. As described above, metallic silicon or nickel chromium may be fused at a lower cutting current than polysilicon. Therefore, for example, by using the metal film EH as the electric fuse element EH, the cut transistor CT (fig. 3) can be miniaturized. Therefore, the semiconductor device SC of the present embodiment is suitable for miniaturization.

As also shown in fig. 5A and 5B, the metal film RS is separated from the metal film EH. Therefore, the metal film RS can be used as an element other than the electric fuse element EH. Compared to polysilicon, silicon metal or nickel chromium has a smaller temperature dependence of the resistance. Therefore, for example, by using the metal film RS as the resistor element RS, characteristics such as resistance are stabilized.

Silicon metal has a greater sheet resistance than polysilicon. Therefore, a large resistance can be obtained with a short wiring length, and miniaturization is possible in this respect, for example, by using the metal film RS as the resistor element RS.

The metal film EH and the metal film RS are arranged between the first wiring FI and the second wiring SI. At the time of resin sealing, although stress acts on the metal film EH and the metal film RS due to a difference in thermal expansion coefficient between the sealing resin and the semiconductor substrate, the first wiring FI and the second wiring SI function as buffers for relaxing the stress. Therefore, stress caused by a difference in thermal expansion coefficient between the sealing resin and the semiconductor substrate at the time of resin sealing hardly acts on the metal films RS and EH. For this reason, it is possible to suppress a change in characteristics of the element formed of the metal film RS and the element formed of the metal film EH due to the influence of stress, thereby obtaining stable characteristics.

Therefore, a semiconductor device having stable characteristics and suitable for miniaturization can be realized.

According to the present embodiment, the metal film EH is the electric fuse element EH, and the metal film RS is the resistor element RS. Therefore, in the semiconductor device SC having the electric fuse element EH and the resistor element RS, stable characteristics and miniaturization can be achieved.

Further, according to the present embodiment, as shown in fig. 5A or fig. 7, the resistor element RS has a plurality of resistor sections RSa to RSd, and the plurality of resistor sections RSa to RSd are connected in series or in parallel.

Further, according to the present embodiment, as shown in fig. 5A, the plurality of resistor portions RSa to RSd are connected in series, and the resistor element RS is arranged to be bent in a plan view. Therefore, in a smaller planar footprint, a long resistance length can be ensured while reducing the wiring width.

Further, according to the present embodiment, as shown in fig. 6A and 6B, in a plan view, an area where the first wiring FI8 and the electric fuse element EH overlap is smaller than an area where the first wirings FI9, FI10 and the resistor element RS overlap. The electric fuse element EH is a portion to be blown and removed. Therefore, by reducing the area of the first wiring FI8 overlapping with the electric fuse element EH in a plan view, the electric fuse element EH is less likely to be radiated, which is likely to be blown.

Further, according to the present embodiment, as shown in fig. 4A and 4B, the wiring length LB of the electric fuse element EH is smaller than the wiring length LA of the resistor element RS. This makes it easy to increase the wiring resistance of the resistor element RS. In addition, it becomes easy to specify a portion to be blown and removed in the electric fuse element EH.

Further, according to the present embodiment, as shown in fig. 5A and 5B, the wiring length W1 of the electric fuse element EH is smaller than the wiring length WB of the resistor element RS. This facilitates the blowing removal of the electric fuse element EH.

According to the present embodiment, as shown in fig. 5A and 5B, the electric fuse element EH and the resistor element RS are arranged in the same layer, and have the same composition. Therefore, the electric fuse element EH and the resistor element RS can be simultaneously formed from the same layer. Therefore, the manufacturing process can be simplified as compared with the case where each of the electric fuse element EH and the resistor element RS is formed separately.

Although the present invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and needless to say, various modifications may be made without departing from the gist thereof.

Claims (10)

1. A semiconductor device, comprising:

a first wiring;

a second wiring;

a first metal film having a first portion, a second portion and a third portion, the second portion being disposed at one end of the first portion, the third portion being disposed at the other end of the first portion; and

a second metal film disposed apart from the first metal film,

wherein a material of each of the first metal film and the second metal film comprises silicon metal or nickel chromium,

wherein the first metal film and the second metal film are arranged in an upper layer of the first wiring and a lower layer of the second wiring, and

wherein each of at least a portion of the second portion and at least a portion of the third portion has a wiring width greater than a wiring width of the first portion.

2. The semiconductor device as set forth in claim 1,

wherein the first metal film is a fuse element and the second metal film is a resistor element.

3. The semiconductor device as set forth in claim 2,

wherein the resistor element has a plurality of resistor portions, an

Wherein the plurality of resistor sections are connected in series or in parallel.

4. The semiconductor device as set forth in claim 3,

wherein the plurality of resistor parts are connected in series and arranged such that the resistor element is bent in a plan view.

5. The semiconductor device as set forth in claim 1,

wherein an area in which the first wiring and the first metal film overlap is smaller than an area in which the first wiring and the second metal film overlap.

6. The semiconductor device as set forth in claim 1,

wherein a wiring length of the first metal film is smaller than a wiring length of the second metal film.

7. The semiconductor device as set forth in claim 1,

wherein a wiring width of the first metal film is smaller than a wiring width of the second metal film.

8. The semiconductor device as set forth in claim 1,

wherein the first metal film and the second metal film are disposed in the same layer and have the same composition.

9. A semiconductor device, comprising:

a specific circuit portion;

a spare redundant circuit part having the same function as the specific circuit part; and

an electric fuse element capable of being a target of fuse removal when the specific circuit portion is replaced with the redundant circuit portion,

wherein the material of the electrical fuse element comprises silicon metal or nickel chromium.

10. A method of manufacturing a semiconductor device, comprising:

forming a first wiring;

forming a first metal film in an upper layer of the first wiring, the first metal film having a first portion, a second portion arranged at one end of the first portion, and a third portion arranged at the other end of the first portion;

forming a second metal film in an upper layer of the first wiring, the second metal film being separated from the first metal film; and

forming a second wiring in an upper layer of the first metal film and the second metal film,

wherein a material of each of the first metal film and the second metal film comprises silicon metal or nickel chromium,

wherein the first metal film is formed such that each of at least a part of the second portion and at least a part of the third portion has a wiring width larger than that of the first portion, and

wherein the first metal film and the second metal film are formed simultaneously.

Images