CN115763241A - Preparation method of semiconductor structure and semiconductor structure - Google Patents
Preparation method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN115763241A CN115763241A CN202211348877.0A CN202211348877A CN115763241A CN 115763241 A CN115763241 A CN 115763241A CN 202211348877 A CN202211348877 A CN 202211348877A CN 115763241 A CN115763241 A CN 115763241A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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Abstract
The embodiment of the disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the preparation method comprises the following steps: the substrate at least comprises mark areas and blank areas positioned between the mark areas; sequentially forming a target layer and a mask layer, wherein the target layer and the mask layer cover the substrate in a conformal manner; forming a core pattern; etching the mask layer by taking the core pattern as a mask to obtain a plurality of first patterns positioned in the mark area and a plurality of first dummy patterns positioned in the blank area; forming a first dielectric layer at least covering the sidewalls of the first pattern and the first dummy pattern; forming a filling layer, wherein the filling layer at least covers the side wall of the first dielectric layer and fills gaps between the adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns; forming a barrier layer, and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask so as to form a second pattern in the marking area; the target layer is etched to transfer the second pattern onto the target layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
As the size of semiconductor structures is further reduced, in order to increase the integration density of semiconductor structures, self-aligned Double Patterning (SADP), self-aligned quad Patterning (SAQP), and the like are introduced into the manufacturing process of semiconductor structures.
However, in the process of performing the patterning process, there may be a large difference in the pattern density of different regions, and the difference is likely to cause a loading effect, so that defects such as voids exist in the semiconductor structure.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps:
providing a substrate, wherein the substrate at least comprises mark areas and blank areas positioned between the mark areas; sequentially forming a target layer and a mask layer on the substrate, wherein the target layer and the mask layer cover the substrate in a conformal manner; forming a core pattern on the mask layer;
etching the mask layer by taking the core pattern as a mask to obtain a plurality of first patterns positioned in the mark area and a plurality of first dummy patterns positioned in the blank area;
forming a first dielectric layer at least covering the sidewalls of the first pattern and the first dummy pattern;
forming a filling layer, wherein the filling layer at least covers the side wall of the first dielectric layer and fills gaps between the adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns;
forming a barrier layer positioned in the blank area, and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask so as to form a second pattern positioned in a mark area;
and etching the target layer to transfer the second pattern to the target layer.
In some embodiments, forming a core pattern on the mask layer includes:
forming a core layer, wherein the core layer covers the mask layer;
forming an anti-reflection layer covering the core layer;
etching the anti-reflection layer and the core layer to form an initial pattern;
forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the top of the initial pattern and the surface of the mask layer between the initial patterns;
and removing the second dielectric layer positioned at the top of the initial pattern and the part of the second dielectric layer positioned between the initial patterns and positioned on the surface of the mask layer, simultaneously removing the initial pattern, and retaining the second dielectric layer positioned on the side wall of the initial pattern to form the core pattern.
In some embodiments, sequentially forming a target layer and a mask layer on the substrate includes:
forming a target layer overlying the substrate;
forming a first mask layer, wherein the first mask layer covers the target layer;
forming a second mask layer, wherein the second mask layer covers the first mask layer;
etching the mask layer by using the core pattern as a mask, comprising:
etching the second mask layer and the first mask layer by taking the core pattern as a mask to form a plurality of initial first patterns located in the mark area and a plurality of initial first dummy patterns located in the blank area;
and removing the second mask layer, wherein the first mask layer remained in the mark area forms the first pattern, and the first mask layer remained in the blank area forms the first dummy pattern.
In some embodiments, forming a first dielectric layer comprises:
forming a first dielectric layer covering the sidewalls and tops of the first patterns and the first dummy patterns and covering the surface of the target layer between the first patterns, between the first dummy patterns, and between the first patterns and the first dummy patterns.
In some embodiments, forming a fill layer comprises:
forming a filling material layer on the first dielectric layer, wherein the filling material layer fills gaps among the adjacent first patterns, among the first dummy patterns and among the first patterns and the first dummy patterns and covers the surface of the substrate;
and performing a thinning process on the filling material layer to form the filling layer, wherein the filling layer exposes the part of the first dielectric layer positioned at the top of the first pattern and the first dummy pattern.
In some embodiments, forming a barrier layer in the void region comprises:
forming a barrier material layer, wherein the barrier material layer covers the filling layer and the part of the first dielectric layer exposed by the filling layer;
performing a patterning process to form an initial barrier layer, wherein the initial barrier layer is located in the blank area;
and performing a thinning process on the initial barrier layer to form the barrier layer.
In some embodiments, etching the first dielectric layer along sidewalls of the first pattern using the barrier layer as a mask includes:
and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask, wherein the first pattern and the filling layer which are remained in the marking area form the second pattern.
In some embodiments, the outermost one of the first dummy patterns includes a first boundary, and a boundary of the barrier layer on the same side as the first boundary defines a second boundary;
the blank area has a first width W1, the barrier layer has a second width W2, the variation value of the critical dimension of the barrier layer is defined as A, and the offset value between the orthographic projections of the first boundary and the second boundary on the substrate is defined as B; the first width W1 and the second width W2 satisfy the following relation:
W1-W2≥A+B (1)。
in some embodiments, the outermost one of the first dummy patterns includes a first boundary, and a boundary of the barrier layer on the same side as the first boundary defines a second boundary;
the blank area has a first width W1, the barrier layer has a second width W2, a variation value of a critical dimension of the barrier layer is defined as A, an offset value between orthographic projections of the first boundary and the second boundary on the substrate is defined as B, and a width of a single first dummy pattern is defined as W3; the first width W1 and the second width W2 satisfy the following relation:
A+B≤W1-W2＜2W3 (2)。
in some embodiments, etching the target layer comprises:
etching the target layer by taking the second pattern and the first dummy pattern, the filling layer and the first dielectric layer which are positioned in the blank area as masks so as to transfer the second pattern to the part of the target layer positioned in the mark area; and the part of the target layer, which is positioned in the blank area, is in an un-etched state.
In some embodiments, after etching the target layer to transfer the second pattern onto the target layer, the method further comprises:
and removing the second pattern, the first dummy pattern, the filling layer and the first dielectric layer on the target layer.
In some embodiments, sequentially forming a target layer and a mask layer on the substrate includes:
forming a target layer overlying the substrate;
forming a first mask layer, wherein the first mask layer covers the target layer;
forming a second mask layer, wherein the second mask layer covers the first mask layer;
forming a third mask layer, wherein the third mask layer covers the second mask layer;
and forming a fourth mask layer, wherein the fourth mask layer covers the third mask layer.
In some embodiments, etching the mask layer using the core pattern as a mask includes:
etching the fourth mask layer and the third mask layer by taking the core pattern as a mask to form an initial third pattern located in the mark area and an initial second dummy pattern located in the blank area;
removing the fourth mask layer, forming a third pattern by the third mask layer remained in the mark area, and forming a second dummy pattern by the third mask layer remained in the blank area;
forming a third dielectric layer, wherein the third dielectric layer at least covers the third pattern and the side wall of the second dummy pattern;
and performing an etching process to remove the third pattern and the second dummy pattern, defining the third dielectric layer remained in the mark area as a fourth pattern, and defining the third dielectric layer remained in the blank area as a third dummy pattern.
The embodiment of the disclosure also provides a semiconductor structure, which is manufactured by adopting the method in any embodiment.
The preparation method of the semiconductor structure and the semiconductor structure provided by the embodiment of the disclosure include: providing a substrate, wherein the substrate at least comprises mark areas and blank areas positioned between the mark areas; sequentially forming a target layer and a mask layer on the substrate, wherein the target layer and the mask layer conformally cover the substrate; forming a core pattern on the mask layer; etching the mask layer by taking the core pattern as a mask to obtain a plurality of first patterns positioned in the mark area and a plurality of first dummy patterns positioned in the blank area; forming a first dielectric layer at least covering the sidewalls of the first pattern and the first dummy pattern; forming a filling layer, wherein the filling layer at least covers the side wall of the first dielectric layer and fills gaps between the adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns; forming a barrier layer positioned in the blank area, and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask so as to form a second pattern positioned in a mark area; and etching the target layer to transfer the second pattern to the target layer. In the process step before the target layer is etched, the pattern structures are formed on the mark area and the blank area between the mark areas, so that the pattern densities in the two areas are kept consistent as much as possible, the generation of a load effect caused by a concave area at a position with low pattern density in the subsequent step of forming the filling layer is prevented, and the possibility of damage to a material layer below the pattern structure in the subsequent operation is greatly reduced. Then, in the step of etching the first dielectric layer, the barrier layer is arranged on the blank area, so that after the step of finally etching the first dielectric layer is finished, the second pattern which can be used for subsequent pattern transfer is generated only at the position of the mark area, and on the blank area, the first dummy patterns, the filling layer positioned among the first dummy patterns and the first dielectric layer positioned on the side wall of the first dummy patterns are still in a continuous state and do not generate pattern structures separated from each other. Therefore, at the end of the step of etching the target layer, the transferred pattern can be obtained only at the position of the target layer in the mark area, and the pattern transfer does not occur at the position of the target layer in the blank area. In summary, the method for fabricating a semiconductor structure according to the embodiments of the disclosure can obtain a desired complete pattern on a target layer while preventing a loading effect, and can significantly improve a yield of the semiconductor structure during a fabrication process.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flow chart diagram of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure;
fig. 2-13 are process flow diagrams of semiconductor structures provided by some embodiments of the present disclosure during fabrication;
fig. 14-19 are process flow diagrams of semiconductor structures provided in further embodiments of the present disclosure during fabrication.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to increase the integration density of the semiconductor structure, during the processes of performing the self-aligned double patterning and the self-aligned quadruple patterning, it is generally required to form a plurality of core layers on a target material layer to be etched, and then a plurality of core patterns may be formed on the core layers by etching the core layers, and the core patterns may be used as masks in the subsequent pattern transfer process.
However, the distribution of the core patterns is usually not uniform, and in the area where the distribution of the core patterns is sparse, the upper surface of the material filled between the core patterns is usually recessed, which is very likely to cause a loading effect, and thus the reliability and yield of the finally obtained semiconductor structure are seriously reduced.
Based on this, the following technical scheme of the embodiment of the disclosure is proposed:
the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in fig. 1, the method includes the following steps:
step S101: providing a substrate, wherein the substrate at least comprises mark areas and blank areas positioned between the mark areas; sequentially forming a target layer and a mask layer on the substrate, wherein the target layer and the mask layer cover the substrate in a conformal manner; forming a core pattern on the mask layer;
step S102: etching the mask layer by taking the core pattern as a mask to obtain a plurality of first patterns positioned in the mark area and a plurality of first dummy patterns positioned in the blank area;
step S103: forming a first dielectric layer at least covering the sidewalls of the first pattern and the first dummy pattern;
step S104: forming a filling layer, wherein the filling layer at least covers the side wall of the first dielectric layer and fills gaps between the adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns;
step S105: forming a barrier layer positioned in the blank area, and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask so as to form a second pattern positioned in the mark area;
step S106: the target layer is etched to transfer the second pattern onto the target layer.
In the process step before the etching target layer, the pattern structures are formed on the mark area and the blank area between the mark areas, so that the pattern densities in the two areas are kept consistent as much as possible, the generation of the load effect caused by the occurrence of the sunken area at the position with low pattern density in the subsequent step of forming the filling layer is prevented, and the possibility of damage to the material layer below the pattern structures in the subsequent operation is greatly reduced. Then, in the step of etching the first dielectric layer, the barrier layer is arranged on the blank area, so that after the step of finally etching the first dielectric layer is finished, the second pattern which can be used for subsequent pattern transfer is generated only at the position of the mark area, and on the blank area, the first dummy patterns, the filling layer positioned among the first dummy patterns and the first dielectric layer positioned on the side wall of the first dummy patterns are still in a continuous state and do not generate pattern structures separated from each other. Therefore, at the end of the step of etching the target layer, the transferred pattern can be obtained only at the position of the target layer in the mark area, and the pattern transfer does not occur at the position of the target layer in the blank area. In summary, the method for fabricating a semiconductor structure according to the embodiments of the disclosure can obtain a desired complete pattern on a target layer while preventing a loading effect, and can significantly improve a yield of the semiconductor structure during a fabrication process.
In order to make the aforementioned objects, features and advantages of the present disclosure more comprehensible, embodiments accompanying the present disclosure are described in detail below. In describing the embodiments of the present disclosure in detail, the drawings are not to be taken as a general scale, and are for illustrative purposes only, and should not be taken as limiting the scope of the present disclosure.
Fig. 1 is a flow chart diagram of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure; fig. 2 to 13 are process flow diagrams of a semiconductor structure provided in some embodiments of the present disclosure during a manufacturing process.
The following describes a method for fabricating a semiconductor structure according to an embodiment of the present disclosure in further detail with reference to the accompanying drawings.
Firstly, step S101 is executed, as shown in fig. 2 to 5, providing a substrate 10, where the substrate 10 at least includes mark regions 21 and blank regions 22 located between the mark regions 21; sequentially forming a target layer 11 and a mask layer 12 on a substrate 10, wherein the target layer 11 and the mask layer 12 cover the substrate 10 in a conformal manner; a core pattern 152a is formed on the mask layer 12.
Here, the substrate may be a semiconductor substrate; the material of the semiconductor substrate specifically includes an elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate is a silicon substrate.
In some embodiments, the mark area and the blank area may be located in the peripheral area, but not limited thereto, and the mark area and the blank area may also be located in other areas, such as a cutting track or any other area where a pattern transfer is required.
With continued reference to fig. 2, in some embodiments, sequentially forming a target layer 11 and a mask layer 12 on a substrate 10 includes:
forming a target layer 11, wherein the target layer 11 covers the substrate 10;
forming a first mask layer 121, wherein the first mask layer 121 covers the target layer 11;
a second mask layer 122 is formed, and the second mask layer 122 covers the first mask layer 121.
In practice, the target layer material includes, but is not limited to, a dielectric layer, a semiconductor layer, a conductive layer (e.g., a metal layer), and the like. In some embodiments, the material of the target layer may be an oxide layer, such as silicon oxide or the like. It is understood that the mask layer may include two parts, i.e., a first mask layer and a second mask layer, wherein the material of the first mask layer includes, but is not limited to, advanced Patterning Film (APF) material, and the like, and the material of the second mask layer includes, but is not limited to, oxynitride, such as silicon oxynitride, and the like, and in some embodiments, the material of the second mask layer may also be other suitable materials.
Optionally, the formation of the target layer, the first mask layer, and the second mask layer may be formed using one or more thin film deposition processes; in particular, the thin film deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.
With continued reference to fig. 2-5, in some embodiments, forming core pattern 152a on masking layer 12 includes:
forming a core layer 13, wherein the core layer 13 covers the mask layer 12;
forming an anti-reflection layer 14, the anti-reflection layer 14 covering the core layer 13;
etching the anti-reflection layer 14 and the core layer 13 to form an initial pattern 13b;
forming a second dielectric layer 152, wherein the second dielectric layer 152 covers the sidewalls and the tops of the initial patterns 13b and the surface of the mask layer 12 between the initial patterns 13b;
the second dielectric layer 152 on top of the preliminary patterns 13b and the portion of the second dielectric layer 152 between the preliminary patterns 13b and on the surface of the masking layer 12 are removed, and simultaneously the preliminary patterns 13b are removed, leaving the second dielectric layer 152 on the sidewalls of the preliminary patterns 13b to form core patterns 152a.
Here, the core pattern 152a is formed on both the mark area 21 and the space area 22 in such a manner that there is no difference (or only a small difference) in the pattern density in the mark area 21 and the space area 22. The absence of pattern density differences (or only small pattern density differences) between the mark region 21 and the blank region 22 can effectively prevent the occurrence of a loading effect in the subsequent pattern transfer process, thereby effectively avoiding or reducing the occurrence of local damage of a pattern structure or void defects in a material layer in a finally formed semiconductor structure, and facilitating the improvement of the stability and yield of the semiconductor structure. It can be understood that the improvement of the stability and yield of the semiconductor structure by the method provided by the embodiment of the present disclosure becomes more obvious when the core pattern 152a is used as a mask for performing the subsequent pattern transfer.
In some embodiments, the pattern density in the mark region 21 and the pattern density in the blank region 22 can be kept consistent, and the finally obtained semiconductor structure can have better stability and yield.
However, in practice, the pattern densities provided in the mark area and the space area may be slightly different in consideration of the size limitation in the mark area and the space area or the size limitation of the individual pattern itself or the pattern pitch. However, compared with the conventional art in which the pattern transfer is performed without disposing a pattern structure in the blank area, the pattern structure is disposed in the blank area to prevent the generation of the loading effect and the generation of defects in the finally formed semiconductor structure to a great extent, which is beneficial to the improvement of the stability and yield of the semiconductor structure.
Alternatively, in some embodiments, the material of the core layer includes, but is not limited to, a spin-on hard mask layer, which may include an amorphous carbon layer or an amorphous silicon layer, etc. The material of the anti-reflective layer includes, but is not limited to, an oxynitride, such as silicon oxynitride, and the like.
It is understood that the formation process of the core layer and the anti-reflection layer may be the same as or different from the formation process of the target layer and the mask layer, and is not limited herein.
It will be appreciated that in practice, before etching the anti-reflection layer 14 and the core layer 13 to form the initial pattern 13b, the method further comprises:
a first mask pattern M1 is formed on the core layer 13.
Here, the material of the first mask pattern includes, but is not limited to, photoresist, etc.
It can be understood that when the material of the first mask pattern includes photoresist, a photolithography process is usually required to complete the definition of the first mask pattern, and the material (such as metal layer and dielectric layer) under the photoresist has a high reflection coefficient, so that the exposure light source is easily reflected on the surface of the material layers, and the first mask pattern is deformed or has a dimensional deviation, so that the mask pattern cannot be correctly transferred. In the preparation method of the embodiment of the disclosure, the anti-reflection layer is formed below the first mask pattern before the first mask pattern is formed, so that the phenomenon that the first mask pattern is deformed or has dimension deviation caused by the reflection of the material surface in the photoetching process can be effectively avoided, the pattern on the mask plate can be correctly transferred to obtain the first mask pattern, and favorable conditions are provided for obtaining a better pattern structure in the subsequent process.
Next, step S102 is performed, as shown in fig. 6 and 7, the mask layer 12 is etched by using the core pattern 152a as a mask, so as to obtain a plurality of first patterns 12a located in the mark region 21 and a plurality of first dummy patterns 12d located in the blank region 22.
In some embodiments, etching mask layer 12 with core pattern 152a as a mask includes:
as shown in fig. 6, the second mask layer 122 and the first mask layer 121 are etched by using the core pattern 152a as a mask to form a plurality of initial first patterns 12b in the mark region 21 and a plurality of initial first dummy patterns 12c in the blank region 22;
as shown in fig. 7, the second mask layer 122 is removed, the first mask layer 121 remaining in the mark region 21 forms the first pattern 12a, and the first mask layer 121 remaining in the blank region 22 forms the first dummy pattern 12d.
Alternatively, the etching process used in forming the first pattern 12a and the first dummy pattern 12d may be a dry etching process, but is not limited thereto, and in some embodiments, the first pattern 12a and the first dummy pattern 12d may also be obtained by a wet etching process. In actual operation, a specific etching method can be flexibly selected according to actual conditions, and no specific limitation is made herein.
Next, step S103 is performed, as shown in fig. 7, a first dielectric layer 151 is formed, and the first dielectric layer 151 covers at least sidewalls of the first patterns 12a and the first dummy patterns 12d.
In some embodiments, forming the first dielectric layer 151 includes:
a first dielectric layer 151 is formed, the first dielectric layer 151 covering sidewalls and tops of the first patterns 12a and the first dummy patterns 12d, and covering a surface of the target layer 11 between the first patterns 12a, between the first dummy patterns 12d, and between the first patterns 12a and the first dummy patterns 12d.
Here, the material of the first dielectric layer includes, but is not limited to, an oxide material, such as silicon oxide, etc.
Then, step S104 is performed, as shown in fig. 8 and 9, a filling layer 17 is formed, in which the filling layer 17 covers at least the sidewalls of the first dielectric layer 151 and fills gaps between the adjacent first patterns 12a, between the first dummy patterns 12d, and between the first patterns 12a and the first dummy patterns 12d.
In some embodiments, forming the fill layer 17 includes:
forming a filling material layer 17a on the first dielectric layer 151, wherein the filling material layer 17a fills gaps between the adjacent first patterns 12a, between the first dummy patterns 12d, and between the first patterns 12a and the first dummy patterns 12d, and covers the surface of the substrate 10;
a thinning process is performed on the filling material layer 17a to form the filling layer 17, and the filling layer 17 exposes a portion of the first dielectric layer 151 on top of the first patterns 12a and the first dummy patterns 12d.
In practice, the material of the filling material layer includes, but is not limited to, a spin-on hard mask layer, which may include an amorphous carbon layer or an amorphous silicon layer, etc.
Next, step S105 is performed, as shown in fig. 9, 10 and 11, forming the barrier layer 18 located in the blank region 22, and etching the first dielectric layer 151 along the sidewall of the first pattern 12a by using the barrier layer 18 as a mask to form a second pattern 12e located in the mark region 21.
In some embodiments, forming the barrier layer 18 in the void 22 includes:
forming a barrier material layer (not shown) covering the filling layer 17 and the exposed portion of the first dielectric layer 151 by the filling layer 17;
as shown in fig. 9, a patterning process is performed to form an initial barrier layer 18a, where the initial barrier layer 18a is located in the blank region 22;
as shown in fig. 10, a thinning process is performed on the initial barrier layer 18a to form the barrier layer 18.
In some embodiments, as shown in fig. 11, etching the first dielectric layer 151 along the sidewalls of the first pattern 12a using the barrier layer 18 as a mask includes:
the first dielectric layer 151 is etched along the sidewalls of the first patterns 12a using the barrier layer 18 as a mask, and the first patterns 12a remaining in the mark region 21 and the filling layer 17 constitute second patterns 12e.
It can be understood that, by disposing the blocking layer on the blank region, after the step of etching the first dielectric layer is completed, the second pattern for subsequent pattern transfer is generated only at the position of the mark region, and at the position of the blank region, due to the presence of the blocking layer, the first dummy pattern, the filling layer between the first dummy patterns, and the first dielectric layer on the sidewall of the first dummy pattern are still in a continuous state, that is, there are no pattern structures separated from each other on the blank region, that is, no pattern structure with a pattern transfer function is obtained in the blank region, so that in the step of performing the subsequent pattern transfer on the etching target layer (step S106), the pattern transfer phenomenon does not occur at the position of the blank region of the target layer.
In an actual process, as shown in fig. 11, after the process step of etching the first dielectric layer 151 is completed, the barrier layer 18 with a certain thickness still remains at the position of the blank region 22, and at this time, the remaining barrier layer 18 does not need to be removed, which can further prevent the first dummy pattern 12d and the filling layer 17 located between the first dummy patterns 12d from being transferred downward at the position of the blank region 22 of the target layer 11 in the subsequent process of performing pattern transfer on the etching target layer 11 (step S106).
In summary, it can be seen that, in the embodiments of the present disclosure, the generation of the pattern structure having the transfer function in the blank area can be blocked by disposing the blocking layer before the etching of the first dielectric layer, and meanwhile, after the etching of the first dielectric layer, the situation that the first dielectric layer in the blank area is etched through to generate the pattern structure having the transfer function and the pattern structure is transferred to the target layer can be further prevented by leaving the blocking layer with a certain thickness. Therefore, in the embodiment of the present disclosure, the manner of disposing the barrier layer on the blank region is beneficial to obtaining a desired complete pattern after the step of subsequently etching the target layer is finished.
In an actual process, the material of the barrier layer includes, but is not limited to, a photoresist, etc., and the thickness of the barrier layer can be flexibly selected according to the required etching time and the type and thickness of the material layer located thereunder, which is not specifically limited herein.
It will be appreciated that in some embodiments, the position of the barrier layer on the blank area and the width relationship between the barrier layer and the blank area may satisfy certain conditions to help obtain a complete pattern on the target layer desired for transfer.
In some embodiments, the width information of the blocking layer may refer to a width between two outermost boundaries in an orthographic projection of the first dummy patterns in the blank area on the substrate when the blocking layer is disposed, but in actual operation, due to various factors such as equipment or process influences, the actual width of the blocking layer may have a certain deviation value compared to the set width value, for example, a larger or smaller deviation value occurs.
It should be noted that, in some other embodiments, the determination of the width information of the blocking layer may refer to other structures besides the first dummy pattern, for example, the filling layer located in the blank area, that is, the width information of the blocking layer may be determined by obtaining the width value information between two outermost boundaries of the filling layer in the orthographic projection of the substrate, which may be specifically selected according to actual situations, and is not limited specifically herein.
Next, the position of the barrier layer on the blank area and the width relationship between the barrier layer and the blank area will be described in further detail with the above-described factors and other possible influencing factors being sufficiently taken into consideration.
In some embodiments, as shown in fig. 10, the outermost first dummy pattern 12d of the plurality of first dummy patterns 12d includes a first boundary S1, and a boundary of the barrier layer 18 on the same side as the first boundary S1 is defined as a second boundary S2;
the blank region 22 has a first width W1, the barrier layer 18 has a second width W2, a variation value of a critical dimension of the barrier layer 18 is defined as a, and an offset value between orthographic projections of the first boundary S1 and the second boundary S2 on the substrate 10 is defined as B; the first width W1 and the second width W2 satisfy the following relation:
W1-W2≥A+B (1)。
it can be understood that by setting the width difference between the blank area and the blocking layer to be greater than the sum of the variation value of the critical dimension of the blocking layer and the offset value between the two boundaries, the two end portions of the blocking layer can be offset in the blank area along the direction from the mark area to the blank area, so that the blocking layer can only play a blocking role in the blank area, and the blocking layer can be ensured not to have adverse effects on the normal transfer of the patterns in the mark area.
It will be appreciated that in some other embodiments, the difference in width between the blank region and the barrier layer may be further defined to help achieve a desired pattern transfer. For example:
in other embodiments, as shown in fig. 10, the outermost first dummy pattern 12d of the plurality of first dummy patterns 12d includes a first boundary S1, and a boundary of the barrier layer 18 on the same side as the first boundary S1 is defined as a second boundary S2;
the blank region 22 has a first width W1, the barrier layer 18 has a second width W2, a variation value of a critical dimension of the barrier layer 18 is defined as a, an offset value between orthographic projections of the first boundary S1 and the second boundary S2 on the substrate 10 is defined as B, and a width of a single first dummy pattern 12d is defined as W3; the first width W1 and the second width W2 satisfy the following relation:
A+B≤W1-W2＜2W3 (2)。
it can be understood that when the end portion of the barrier layer is too far away from the inside of the blank region, the first dielectric layer on the sidewall of the first dummy pattern in the blank region is exposed, and at this time, during the etching of the first dielectric layer, pattern structures having a pattern transfer function and separated from each other appear in the blank region. In this case, when the subsequent step of etching the target layer (step S106) is performed, the target layer is located at the blank area, so that the pattern transfer condition which is not expected occurs, and should be avoided.
In the embodiment of the disclosure, in addition to setting a lower limit value for ensuring that the barrier layer does not affect the process execution of the mark region while the blank region performs the barrier function, the information about the width difference between the blank region and the barrier layer also sets an upper limit value, that is, the width difference between the blank region and the barrier layer is smaller than a doubled width value of a single first dummy pattern, so as to prevent the first dielectric layer in the blank region from being etched through and a structure having the pattern transfer function from occurring. Therefore, the limitation of the width difference range between the blank region and the barrier layer in this embodiment can ensure that the barrier layer only plays a role in blocking the blank region, and further has the beneficial effect of preventing the pattern structure with the pattern transfer function from appearing in the blank region, so that the semiconductor structure is greatly beneficial to obtaining the expected complete pattern.
Finally, step S106 is performed, as shown in fig. 12, to etch the target layer 11 to transfer the second pattern 12e onto the target layer 11.
In some embodiments, the etch target layer 11 includes:
etching the target layer 11 by using the second pattern 12e and the first dummy pattern 12d, the filling layer 17 and the first dielectric layer 151 located in the blank region 22 as masks, so as to transfer the second pattern 12e to the portion of the target layer 11 located in the mark region 21; wherein, the part of the target layer 11 located in the blank region 22 is in an un-etched state.
In the embodiment of the present disclosure, when the second pattern 12e is formed, the first dummy patterns 12d located in the blank region 22, the filling layer 17 located between the first dummy patterns 12d, and the first dielectric layer 151 are still in a continuous state, and the barrier layer 18 with a certain thickness still remains on the blank region 22, so that after the process step of etching the target layer 11 is completed, the first dielectric layer 151 located above the blank region 22 of the target layer 11 is not etched through. At this time, neither the first dummy pattern 12d located in the blank region 22 nor the filling layer 17 has the capability of pattern transfer, so that after the etching process is finished, the pattern transfer phenomenon does not occur at the position of the target layer 11 located in the blank region 22, and the transferred fifth pattern 11a can be obtained only at the position of the target layer 11 located in the mark region 21.
In some embodiments, as shown in fig. 13, after etching the target layer 11 to transfer the second pattern 12e onto the target layer 11, the preparation method further includes:
the second pattern 12e, the first dummy pattern 12d, the filling layer 17 and the first dielectric layer 151 on the target layer 11 are removed.
It is understood that the manufacturing method provided by the embodiments of the present disclosure can be applied to the fabrication of various semiconductor structures, for example, when the above method is applied to a dynamic random access memory, the above manufacturing method for obtaining a desired pattern in a target layer can obtain structures including, but not limited to, an active region, a bit line, a capacitor structure, and the like.
It should be noted that, although only the case where the substrate includes the mark region and the blank region is shown in the drawings, the substrate may include other regions, such as the array region and the peripheral region, in an actual process.
Alternatively, in actual practice, the pitch of the pattern in the mark region may follow the pitch design size between the pattern structures in the array region, while the extending direction of the pattern in the mark region may be kept parallel to the array lines of the array region.
Further, alternatively, the pattern pitch of the dummy patterns in the blank area may follow the design rule of the dummy patterns in the peripheral area.
In the above embodiments, the case of performing pattern transfer on one mask layer after obtaining the core pattern is mentioned, it can be understood that in practical operation, the number of mask layers below the core pattern may also be multiple, for example: 2, 3, 4, 5, 6, dozens, or even more layers. The multi-layer mask layer is beneficial to realizing the effect of further increasing the pattern density or improving the effect of pattern transfer precision.
In other embodiments of the present disclosure, when the number of mask layers is increased, how to obtain a desired complete pattern on a target layer by using the method provided by the embodiments of the present disclosure will be described in detail below by taking a structure in which the number of mask layers is 2 as an example.
Fig. 14-19 are process flow diagrams of semiconductor structures during fabrication according to further embodiments of the present disclosure.
First, in some embodiments, sequentially forming a target layer 11 and a mask layer 12 on a substrate 10 as shown in fig. 14 includes:
forming a target layer 11, the target layer 11 covering the substrate 10;
forming a first mask layer 121, wherein the first mask layer 121 covers the target layer 11;
forming a second mask layer 122, wherein the second mask layer 122 covers the first mask layer 121;
forming a third mask layer 191, wherein the third mask layer 191 covers the second mask layer 122;
a fourth mask layer 192 is formed, and the fourth mask layer 192 covers the third mask layer 191.
In practical applications, the materials of the third mask layer and the first mask layer may be the same or different, and are not limited herein. Meanwhile, the materials of the second mask layer and the fourth mask layer may be the same or different, and are not limited specifically herein.
Next, as shown in fig. 14 to 16, in some embodiments, after forming the mask layer 12, the method further includes forming a core pattern 152a, and in this embodiment, the method for forming the core pattern 152a is substantially the same as the method for forming the core pattern 152a in fig. 2 to 5 of the previous embodiment, which will not be described herein. The difference is that the pattern density of the core pattern 152a in fig. 16 of this embodiment is smaller than that of the core pattern 152a in fig. 5 of the previous embodiment.
Next, as shown in fig. 17 to 19, in some embodiments, etching mask layer 12 with core pattern 152a as a mask includes:
etching the fourth mask layer 192 and the third mask layer 191 by using the core pattern 152a as a mask to form an initial third pattern 19b in the mark region 21 and an initial second dummy pattern 19c in the blank region 22;
removing the fourth mask layer 192, forming a third pattern 19a by the third mask layer 191 remaining in the mark region 21, and forming a second dummy pattern 19d by the third mask layer 191 remaining in the blank region 22;
forming a third dielectric layer 153, wherein the third dielectric layer 153 covers at least the sidewalls of the third pattern 19a and the second dummy pattern 19d;
and performing an etching process to remove the third pattern 19a and the second dummy pattern 19d, and defining the third dielectric layer 153 remained in the mark region 21 as a fourth pattern 153a and defining the third dielectric layer 153 remained in the blank region 22 as a third dummy pattern 153d.
Then, in some embodiments, after forming the fourth pattern 153a and the third dummy pattern 153d, the method further includes:
steps similar to those shown in fig. 6 and 7 are performed, at this time, the second mask layer 122 and the first mask layer 121 are etched by using the fourth pattern 153a and the third dummy pattern 153d as masks, and then the second mask layer 122 located above the first mask layer 121 is removed, so that the first pattern 12a and the first dummy pattern 12d consistent with those in fig. 7 can be obtained.
Thereafter, on the basis of the structure shown in fig. 7, the fifth pattern 11a shown in fig. 13 can be obtained on the target layer 11 by performing the same or similar steps as those in fig. 7 to 13.
It can be seen that, in this embodiment, even if the core pattern has a lower pattern density, a pattern structure of the same density can be obtained on the target layer through the process of two pattern transfers. The last pattern density increase occurs on the mask layer at the bottommost layer, so that after the filling layer is formed and before the first dielectric layer is etched, a barrier layer is only required to be introduced on the blank area of the mask layer at the bottommost layer, and the structure with the pattern transfer function can be prevented from appearing in the blank area of the layer.
It can be understood that when the number of mask layers is increased (in the case of 3, 4, 5, 6, dozens or even more), the pattern transfer process in the upper mask layer can be performed normally during the pattern transfer process, and the introduction of the barrier layer structure on the blank area can avoid the pattern transfer phenomenon in the position where the target layer is located in the blank area in the finally formed semiconductor structure only when the last pattern density increasing operation is performed. Therefore, the embodiments of the present disclosure are applicable to a case where a multi-layer mask is used for pattern transfer, and in the pattern transfer process, a desired complete pattern can be obtained only by introducing the blocking layer in the last operation of increasing the pattern density, so that the complexity of the process steps is hardly increased, and the stability and yield of the semiconductor structure can be significantly improved.
The embodiment of the present disclosure also provides a semiconductor structure, as shown in fig. 11, the semiconductor structure includes:
a substrate 10, wherein the substrate 10 at least comprises mark regions 21 and blank regions 22 located between the mark regions 21;
a target layer 11 on the substrate 10;
a plurality of second patterns 12e on the target layer 11, a plurality of first dummy patterns 12d in the blank region 22, a filling layer 17 between the first dummy patterns 12d, and a first dielectric layer 151 on sidewalls of the first dummy patterns 12 d; wherein, the first dummy patterns 12d on the blank region 22, the filling layer 17 between the first dummy patterns 12d and the first dielectric layer 151 on the sidewalls of the first dummy patterns 12d are in a continuous state;
and a barrier layer 18, the barrier layer 18 being positioned on the first dummy patterns 12d of the blank area 22.
The embodiment of the present disclosure further provides another semiconductor structure, as shown in fig. 13, the semiconductor structure includes:
a substrate 10, wherein the substrate 10 at least comprises mark regions 21 and blank regions 22 located between the mark regions 21;
a target layer 11 on the substrate 10, the target layer 11 being provided with a fifth pattern 11a only at positions located at the mark regions 21.
It will be appreciated that the semiconductor body structure may be fabricated using the method provided in any of the embodiments described above.
It should be noted that the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure may be applied to a DRAM structure or other semiconductor devices, and is not limited herein. The embodiment of the semiconductor device preparation method provided by the disclosure and the embodiment of the semiconductor device belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict.
The above description is only exemplary of the present disclosure and should not be taken as limiting the scope of the present disclosure, which is intended to cover any variations, modifications, equivalents, and improvements included within the spirit and scope of the present disclosure.
Claims (14)
1. A method for fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein the substrate at least comprises mark areas and blank areas positioned between the mark areas; sequentially forming a target layer and a mask layer on the substrate, wherein the target layer and the mask layer conformally cover the substrate; forming a core pattern on the mask layer;
etching the mask layer by taking the core pattern as a mask to obtain a plurality of first patterns positioned in the mark area and a plurality of first dummy patterns positioned in the blank area;
forming a first dielectric layer at least covering the sidewalls of the first pattern and the first dummy pattern;
forming a filling layer, wherein the filling layer at least covers the side wall of the first dielectric layer and fills gaps between the adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns;
forming a barrier layer positioned in the blank area, and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask so as to form a second pattern positioned in a mark area;
and etching the target layer to transfer the second pattern to the target layer.
2. The method of claim 1, wherein forming a core pattern on the mask layer comprises:
forming a core layer, wherein the core layer covers the mask layer;
forming an anti-reflection layer covering the core layer;
etching the anti-reflection layer and the core layer to form an initial pattern;
forming a second dielectric layer, wherein the second dielectric layer covers the side wall and the top of the initial pattern and the surface of the mask layer between the initial patterns;
and removing the second dielectric layer positioned at the top of the initial pattern and the part of the second dielectric layer positioned between the initial patterns and positioned on the surface of the mask layer, simultaneously removing the initial pattern, and remaining the second dielectric layer positioned on the side wall of the initial pattern to form the core pattern.
3. The method of claim 1, wherein sequentially forming a target layer and a mask layer on the substrate comprises:
forming a target layer overlying the substrate;
forming a first mask layer, wherein the first mask layer covers the target layer;
forming a second mask layer, wherein the second mask layer covers the first mask layer;
etching the mask layer by using the core pattern as a mask, comprising:
etching the second mask layer and the first mask layer by taking the core pattern as a mask to form a plurality of initial first patterns located in the mark area and a plurality of initial first dummy patterns located in the blank area;
and removing the second mask layer, wherein the first mask layer remained in the mark area forms the first pattern, and the first mask layer remained in the blank area forms the first dummy pattern.
4. The method of claim 1 or 3, wherein forming a first dielectric layer comprises:
forming a first dielectric layer covering the sidewalls and tops of the first patterns and the first dummy patterns and covering the surface of the target layer between the first patterns, between the first dummy patterns, and between the first patterns and the first dummy patterns.
5. The method of claim 4, wherein forming a fill layer comprises:
forming a filling material layer on the first dielectric layer, wherein the filling material layer fills gaps among the adjacent first patterns, among the first dummy patterns and among the first patterns and the first dummy patterns and covers the surface of the substrate;
and performing a thinning process on the filling material layer to form the filling layer, wherein the filling layer exposes the part of the first dielectric layer positioned at the top of the first pattern and the first dummy pattern.
6. The method of claim 5, wherein forming a barrier layer in the blank area comprises:
forming a barrier material layer, wherein the barrier material layer covers the filling layer and the part of the first dielectric layer exposed by the filling layer;
performing a patterning process to form an initial barrier layer, wherein the initial barrier layer is located in the blank area;
and performing a thinning process on the initial barrier layer to form the barrier layer.
7. The method of claim 6, wherein etching the first dielectric layer along sidewalls of the first pattern using the barrier layer as a mask comprises:
and etching the first dielectric layer along the side wall of the first pattern by taking the barrier layer as a mask, wherein the first pattern and the filling layer which are remained in the marking area form the second pattern.
8. The method for manufacturing according to claim 1, wherein the outermost one of the first dummy patterns includes a first boundary, and a boundary of the barrier layer on a same side as the first boundary is defined as a second boundary;
the blank area has a first width W1, the barrier layer has a second width W2, the variation value of the critical dimension of the barrier layer is defined as A, and the offset value between the orthographic projections of the first boundary and the second boundary on the substrate is defined as B; the first width W1 and the second width W2 satisfy the following relation:
W1-W2≥A+B (1)。
9. the method for manufacturing according to claim 1, wherein the outermost one of the first dummy patterns includes a first boundary, and a boundary of the barrier layer on a same side as the first boundary is defined as a second boundary;
the blank area has a first width W1, the barrier layer has a second width W2, a variation value of a critical dimension of the barrier layer is defined as A, an offset value between orthographic projections of the first boundary and the second boundary on the substrate is defined as B, and a width of a single first dummy pattern is defined as W3; the first width W1 and the second width W2 satisfy the following relation:
A+B≤W1-W2＜2W3 (2)。
10. the method of claim 1, wherein etching the target layer comprises:
etching the target layer by taking the second pattern and the first dummy pattern, the filling layer and the first dielectric layer which are positioned in the blank area as masks so as to transfer the second pattern to the part of the target layer positioned in the mark area; and the part of the target layer, which is positioned in the blank area, is in an un-etched state.
11. The method of claim 10, wherein after etching the target layer to transfer the second pattern onto the target layer, the method further comprises:
and removing the second pattern, the first dummy pattern, the filling layer and the first dielectric layer on the target layer.
12. The method of claim 1, wherein sequentially forming a target layer and a mask layer on the substrate comprises:
forming a target layer overlying the substrate;
forming a first mask layer, wherein the first mask layer covers the target layer;
forming a second mask layer, wherein the second mask layer covers the first mask layer;
forming a third mask layer, wherein the third mask layer covers the second mask layer;
and forming a fourth mask layer, wherein the fourth mask layer covers the third mask layer.
13. The method of claim 12, wherein etching the mask layer using the core pattern as a mask comprises:
etching the fourth mask layer and the third mask layer by taking the core pattern as a mask to form an initial third pattern located in the mark area and an initial second dummy pattern located in the blank area;
removing the fourth mask layer, forming a third pattern by the third mask layer remained in the mark area, and forming a second dummy pattern by the third mask layer remained in the blank area;
forming a third dielectric layer, wherein the third dielectric layer at least covers the third pattern and the side wall of the second dummy pattern;
and performing an etching process to remove the third pattern and the second dummy pattern, defining the third dielectric layer remained in the mark area as a fourth pattern, and defining the third dielectric layer remained in the blank area as a third dummy pattern.
14. A semiconductor structure, wherein the semiconductor structure is formed using the method of any of claims 1-13.
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| CN116031145A (en) * | 2023-03-27 | 2023-04-28 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| WO2024093190A1 (en) * | 2022-10-31 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method, and semiconductor structure |
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| CN105826193A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN108231770B (en) * | 2016-12-22 | 2021-05-04 | 联华电子股份有限公司 | Method for forming pattern |
| CN114823295A (en) * | 2021-01-27 | 2022-07-29 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN113643966B (en) * | 2021-08-09 | 2023-05-02 | 长鑫存储技术有限公司 | Mask structure and preparation method thereof and preparation method of semiconductor structure |
| CN115763241A (en) * | 2022-10-31 | 2023-03-07 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
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| WO2024093190A1 (en) * | 2022-10-31 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method, and semiconductor structure |
| CN116031145A (en) * | 2023-03-27 | 2023-04-28 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
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