CN115762622A - Method and device for chip repair, computer equipment and readable storage medium - Google Patents

Abstract

The embodiment of the disclosure provides a method and a device for chip repair, computer equipment and a readable storage medium. The method for repairing the chip comprises the following steps: determining target fault groups in a chip to be repaired, wherein each target fault group comprises at least one fault unit; obtaining a target path of a target fault group; obtaining a target repair mode of a target fault group according to the target path; and obtaining a target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group. The method of the embodiment of the disclosure can efficiently and accurately repair the fault unit in the chip to be repaired.

Description

Method and device for chip repair, computer equipment and readable storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for chip repair, a computer device, and a readable storage medium.

Background

With the increase of the capacity and density of the memory chip, the number of failed cells on the memory chip increases, and in order to ensure the yield of the memory chip, the failed cells on the memory chip need to be repaired. However, the repair methods in the prior art do not achieve efficient and accurate repair.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present disclosure, and thus it may include information that does not constitute related art known to those of ordinary skill in the art.

Disclosure of Invention

The embodiment of the disclosure provides a method and a device for repairing a chip, computer equipment and a computer readable storage medium, which can efficiently and accurately repair a fault unit in the chip.

The embodiment of the disclosure provides a method for repairing a chip, which comprises the following steps: determining target fault groups in a chip to be repaired, wherein each target fault group comprises at least one fault unit; obtaining a target path of the target fault group; obtaining a target repair mode of the target fault group according to the target path; and obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group.

According to an exemplary embodiment of the present disclosure, determining a target failure group in a chip to be repaired includes: obtaining a fault unit in the chip to be repaired; determining a must-repair failed cell from the failed cells; adopting standby resources to repair the necessary repair fault unit to obtain residual standby resources; and grouping the remaining fault units except the necessary repair fault unit to obtain the target fault group.

According to an exemplary embodiment of the present disclosure, determining a must-repair failed cell from among the failed cells includes: obtaining a standby row and a standby column in the standby resource; if the number of the spare rows is larger than that of the spare rows, acquiring repair-indispensable fault rows in the chip to be repaired, wherein the repair-indispensable fault units comprise fault units in the repair-indispensable fault rows, and the number of the fault units in the repair-indispensable fault rows is larger than that of the spare rows; and if the number of the standby rows is larger than that of the standby columns, acquiring repair-required fault rows in the chip to be repaired, wherein the repair-required fault units comprise fault units in the repair-required fault rows, and the number of the fault units in the repair-required fault rows is larger than that of the standby columns.

According to an exemplary embodiment of the present disclosure, grouping remaining faulty units other than the repair-mandatory faulty unit to obtain the target faulty group includes: dividing the remaining fault units with the same row address or the same column address into a group to obtain a non-standardized fault group; normalizing the non-normalized fault group to obtain the target fault group.

According to an exemplary embodiment of the disclosure, grouping the remaining faulty cells with the same row address or the same column address into a group, obtaining a non-standardized set of faults comprises: constructing a first non-standardized fault group, and determining a first grouping information list of the first non-standardized fault group; acquiring a row address and a column address of the first residual fault unit; if the first grouping information list is empty or the row address or the column address of a second remaining fault unit existing in the first grouping information list is the same as the row address or the column address of the first remaining fault unit, adding the row address and the column address of the first remaining fault unit into the first grouping information list; if the row address and the column address of the second residual fault unit are different from those of the first residual fault unit, a second non-standardized fault group is newly established, and a second grouping information list of the second non-standardized fault group is determined; wherein the non-standardized fault group includes the first non-standardized fault group and the second non-standardized fault group, and the remaining fault cells include the first remaining fault cells and the second remaining fault cells.

According to an exemplary embodiment of the present disclosure, normalizing the non-normalized fault group to obtain the target fault group includes: and respectively arranging the row addresses and the column addresses of the fault units in the non-standardized fault group in the row direction and the column direction of the target fault group in an ascending order to generate the target fault group, wherein the first value in the target fault group represents the fault units, and the second value represents the normal units.

According to an exemplary embodiment of the present disclosure, normalizing the non-normalized fault group to obtain the target fault group includes: determining a minimum required backup resource for the non-standardized fault group; normalizing the non-normalized fault group to obtain the target fault group if the remaining spare resources are greater than or equal to the minimum required spare resources.

According to an exemplary embodiment of the present disclosure, obtaining a target path of the target failure group includes: if the total number of the fault units in the target fault group is greater than 1, sequentially searching the associated fault units for each fault unit in the target fault group according to a preset direction from an initial fault unit in the target fault group, and calculating the step length from the current fault unit to the associated next fault unit until all fault units in the target fault group are completely traversed; and obtaining the target path of the target fault group according to the direction and the step length of the next fault unit which is searched from the current fault unit and is associated with the current fault unit.

According to an exemplary embodiment of the present disclosure, obtaining a target repair manner of the target fault group according to the target path includes: obtaining a matching library, wherein the matching library comprises candidate paths and candidate repairing modes corresponding to the candidate paths; and searching the candidate paths according to the target path, and determining the target repairing mode from the candidate repairing modes.

According to an exemplary embodiment of the present disclosure, the target paths include a first target path that does not match the candidate path, the first target path corresponds to a first target failure group, and the target failure group includes the first target failure group; obtaining a target repair mode of the target fault group according to the target path, further comprising: obtaining the number m 'of fault rows and the number n' of fault columns of the first target fault group, wherein m 'and n' are both positive integers; if the number of the fault columns of the first target fault group is larger than the number of the fault rows, repairing the fault columns in the first target fault group by using the spare columns in the spare resources, wherein the number of the spare columns is decreased from n' to 0 according to the repair times, and after repairing by using the spare columns every time, repairing the residual fault units in the first target fault group which are not repaired by the spare columns by using the spare rows in the spare resources.

According to an exemplary embodiment of the present disclosure, the target failure group includes a first target failure group and a second target failure group, the target repair manner of the first target failure group includes a first-level target repair manner, and the repair manner of the second target failure group includes a second-level target repair manner; the quantity of the standby resources required in the first-level target repair mode is the same, and the quantity of the standby resources required in the second-level target repair mode is the same; obtaining a target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group, wherein the step of obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group comprises the following steps: combining the first-stage target repairing mode and the second-stage target repairing mode to obtain the first required spare row resource quantity and the first required spare column resource quantity of the chip to be repaired; obtaining the quantity of the remaining standby row resources and the quantity of the remaining column resources in the remaining standby resources; if the number of the first required spare row resources is less than or equal to the number of the remaining spare row resources and the number of the first required spare column resources is less than or equal to the number of the remaining spare column resources, determining that the target repair mode comprises the first-level target repair mode and the second-level target repair mode.

According to an exemplary embodiment of the present disclosure, the first target fault group further includes a third-level target repair manner, the number of the required standby resources in the third-level target repair manner is the same, and the required standby resources in the third-level target repair manner are greater than the required standby resources in the first-level target repair manner; wherein, obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group further comprises: if the number of the first required spare row resources is larger than the number of the remaining spare row resources, or the number of the first required spare column resources is larger than the number of the remaining spare column resources, combining the third-stage target repair mode and the second-stage target repair mode to obtain the number of the second required spare row resources and the number of the second required spare column resources of the chip to be repaired; and if the second required spare row resource quantity is less than or equal to the residual spare row resource quantity and the second required spare column resource quantity is less than or equal to the residual spare column resource quantity, determining that the target repair mode comprises the third-stage target repair mode and the second-stage target repair mode.

The embodiment of the disclosure also provides a device for repairing a chip, which comprises a determining module and a processing module. The determining module is used for determining target fault groups in the chip to be repaired, wherein each target fault group comprises at least one fault unit; the processing module is used for obtaining a target path of the target fault group; the processing module is further used for obtaining a target repair mode of the target fault group according to the target path; the processing module is further configured to obtain a target repair mode of the chip to be repaired according to the target repair mode of the target fault group.

The embodiment of the present disclosure also provides a computer device, which includes a processor, a memory, and an input/output interface; the processor is connected to the memory and the input/output interface, respectively, where the input/output interface is configured to receive data and output data, the memory is configured to store a computer program, and the processor is configured to call the computer program, so that the computer device executes the method in any of the above embodiments.

The embodiments of the present disclosure also provide a computer-readable storage medium, which stores a computer program, the computer program being suitable for being loaded and executed by a processor, so as to enable a computer device with the processor to execute the method described in any one of the above embodiments.

According to the technical scheme, the method for repairing the chip, provided by the embodiment of the disclosure, has at least one of the following advantages and positive effects:

in the embodiment of the disclosure, by obtaining the target path of the target fault group and the target repair mode matched with the target path, the repair scheme can be efficiently and accurately found out under limited standby resources, the time cost of analysis is reduced, and the productivity is improved.

Drawings

The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a flow diagram illustrating a method for chip repair according to some embodiments of the present disclosure;

FIG. 2 is a flow diagram illustrating the determination of a target failure group according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram illustrating a faulty cell in a chip to be repaired according to some embodiments of the present disclosure;

FIG. 4 is a block diagram illustrating a determination that a failed cell must be repaired in accordance with some embodiments of the present disclosure;

FIG. 5 is a schematic diagram illustrating determining a must-repair failure unit in accordance with some embodiments of the present disclosure;

FIG. 6 is a schematic diagram illustrating grouping of remaining failed units in accordance with some embodiments of the present disclosure;

FIG. 7 is a schematic diagram illustrating the acquisition of a two-dimensional matrix binary map of each normalized fault group according to some embodiments of the present disclosure;

FIG. 8 is a framework diagram illustrating the determination of the relationship of remaining standby resources to required standby resources according to some embodiments of the present disclosure;

FIG. 9 is a schematic diagram illustrating obtaining a target path for a target failure group according to some embodiments of the present disclosure;

FIG. 10 is a flow diagram illustrating obtaining a target path for a target failure group according to some embodiments of the present disclosure;

fig. 11 is a diagram illustrating candidate paths and candidate repair manners in a matching library obtained according to a preset region according to some embodiments of the present disclosure;

FIG. 12 is a schematic diagram illustrating a target restoration method for determining a target path according to a candidate path according to some embodiments of the present disclosure;

FIG. 13 is a schematic diagram illustrating an acquisition of candidate repair approaches according to some embodiments of the present disclosure;

FIG. 14 illustrates a target fix for different fault groups in accordance with certain embodiments of the present disclosure;

FIG. 15 is a flow chart illustrating a method for chip repair according to some embodiments of the present disclosure;

FIG. 16 is a block diagram of an apparatus for chip repair shown in some embodiments of the present disclosure;

FIG. 17 is a schematic diagram of a computer device shown in some embodiments of the present disclosure;

FIG. 18 is a schematic diagram of a computer-readable storage medium illustrating some embodiments of the present disclosure.

Detailed Description

The preset drawings will now be described more fully with reference to the example embodiments. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

In the following description of various exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be utilized and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various example features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the orientation of the examples in the figures. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not numerical limitations of their objects.

The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.

In addition, in the description of the present disclosure, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

As the capacity and density of the memory chip increase, the number of failed cells on the memory chip increases, and in order to repair the failed cells to improve the yield of the chip, a spare circuit architecture and a repair analysis algorithm are used for repair in the related art. The standby circuit architecture comprises standby rows and standby columns, and due to the limited number of the standby rows and the standby columns in the standby circuit architecture, the standby circuit architecture can be implemented by an RA (Redundancy Analysis) algorithm, the number of the fault units is counted respectively for the rows and the columns with faults, and the standby rows and the standby columns in the standby circuit architecture are allocated in a descending order for repair. However, in the case of a real solution, the assignment result of the spare rows and the spare columns fails to successfully repair all the faulty cells, and the chip is still faulty and becomes a waste product, resulting in a reduced yield.

Based on this, the disclosed embodiment provides a method for chip repair, and as shown in fig. 1, the method for chip repair of the disclosed embodiment includes the following steps: s110 to S140.

S110: and determining target fault groups in the chip to be repaired, wherein each target fault group comprises at least one fault unit.

The chip to be repaired is a failed chip, and the chip may be a Memory chip, such as a Dynamic Random Access Memory (DRAM) chip, which is not particularly limited herein. The target fault group is a fault group which is repaired by the method of the embodiment of the disclosure after fault units in the chip to be repaired are grouped.

In some embodiments, as shown in fig. 2, the determining of the target failure group in the chip to be repaired in S110 includes the following steps: s210 to S240.

S210: and obtaining a fault unit in the chip to be repaired.

A fault counter (col-error counter) is installed in advance in the chip, and the fault counter can count the number and address of fault units. As shown in fig. 3, a faulty cell in a chip to be repaired in some embodiments is shown. Where the filled circles represent faulty cells.

S220: and determining the necessary repair fault unit from the fault units.

FIG. 4 illustrates a block diagram of determining that a failed cell must be repaired according to some embodiments of the present disclosure. In the embodiment of the present disclosure, determining a necessary repair failure unit from the failure units includes: s410 to S430.

S410: spare rows and spare columns in the spare resources are obtained.

As shown in fig. 3, the spare resources are a predetermined number of spare circuits, including spare rows and columns, previously arranged in the memory array area of the chip, for repairing the failed cells in the chip. Wherein, in the disclosed embodiment, the spare rows are represented by ASR and the spare columns are represented by ASC.

S420: if the number of the ASCs in the standby columns is larger than that of the ASRs in the standby rows, acquiring necessary repair fault columns in the current chip to be repaired, wherein the necessary repair fault units comprise fault units in the necessary repair fault columns, and the number of the fault units in the necessary repair fault columns is larger than that of the standby rows.

S430: if the number of the spare rows ASR is larger than that of the spare columns ASC, a necessary repair fault row in the current chip to be repaired is obtained, the necessary repair fault unit comprises a fault unit in the necessary repair fault row, and the number of the fault unit in the necessary repair fault row is larger than that of the spare columns.

In S420, after acquiring the necessary repair fault column in the current chip to be repaired, the method may further include S421: and judging whether to trigger acquisition of the row which needs to be repaired. That is, after the repair-required faulty column is obtained in S420, the faulty column and the spare column are updated, and then the relation between the number of ASRs and ASCs is determined, if the number of spare rows ASR in S430 is greater than the number of spare columns ASC, S430 is executed. After performing S430, S431 may be further included: and judging whether to trigger acquisition of the necessary repair fault column. That is, after acquiring the necessary repair failure row in S430, the failure row and the backup failure row are updated, and the relationship between the ASR and the ASC is determined after the updating, if the number of backup columns ASC in S420 is greater than the number of backup rows ASR, S420 is executed until the above conditions are not met, and then the process is terminated.

Specifically, in some embodiments, as shown in fig. 4 and fig. 5, in S420, the number relationship between the spare row ASR and the spare column ASC in the spare resource is determined, and if the number of the spare column ASC is greater than the number of the spare row ASR, the repair to the repair chip is considered by columns first, that is, the repair-necessary fault column is obtained first, and the number of fault units in the repair-necessary fault column is greater than the number of the spare row ASR.

And after the necessary repair fault column is determined, updating the number of the fault units and the number of the spare columns ASCs, and judging whether to acquire the necessary repair fault row. In S430, if the number of the current spare lines ASR is less than or equal to the number of the current spare columns ASC (updated spare columns ASC), the process ends; if the number of the current spare rows ASR is greater than the current spare columns ASC (updated spare columns ASC), repairing the chip to be repaired by rows is considered, that is, at this time, the rows that must be repaired are obtained, and the number of the fault units in the rows that must be repaired is greater than the number of the current spare columns ASC. And after the fault line which needs to be repaired is determined, updating the quantity of the fault units and the spare line ASR, judging whether the condition of S420 is met again, if so, continuing to execute the step S420, and if not, ending.

For example, as shown in fig. 5, if the area to be repaired of the chip to be repaired has 8 rows and 8 columns, the spare rows ASR are 4, the spare columns ASC are 3, and the number of spare rows ASR is greater than the number of spare columns ASC, then the necessary repair faulty row is determined first, and the number of faulty cells in the necessary repair faulty row needs to be greater than the number of spare columns ASC, as can be seen from fig. 5, the number of faulty cells in the first row (row address 0) is 4, and the number of faulty cells in the sixth row (row address 5) is 5, which are both greater than the number of spare columns ASC 3, so that the first row and the sixth row are determined to be the necessary repair faulty row. And updating the number of the fault units and the number of the spare rows, namely removing the fault units in the necessary fault rows and simultaneously removing two spare rows. At this time, the number of the current spare rows ASR is 2, the number of the spare columns ASC is 3, and it is determined that the number of the current spare columns ASC is greater than the number of the spare rows ASR, a repair-indispensable failure column is determined, it is found that 4 failure units exist in the sixth column (column address is 5), and if the number is greater than the number of the current spare rows ASR 2, the sixth column is determined to be a repair-indispensable failure column, and the number of the failure units and the number of the spare columns ASC are updated, at this time, the number of the current spare columns ASC is 2, and the number of the current spare rows ASR is 2. And judging that the quantity of the ASC is equal to that of the ASR, and ending. Through the above method, the repair-mandatory fault row in the chip to be repaired in fig. 5 is determined as the first row and the sixth row, and the repair-mandatory fault column is the sixth column.

S230: and adopting the standby resources to repair the necessary fault unit to obtain the residual standby resources.

After the must-repair failed rows and must-repair failed columns are determined, the must-repair failed rows and must-repair failed columns may be repaired first using the spare rows ASR and spare columns ASC, as shown by the dashed lines in fig. 5. Therefore, the fault units in the chip to be repaired are reduced, and the complexity is reduced for subsequent repair.

S240: and grouping the remaining fault units except the necessary repair fault unit to obtain a target fault group.

After removing the necessary repair failure unit, remaining failure units still exist in the chip to be repaired, and grouping the remaining failure units may include: dividing the residual fault units with the same row address or the same column address into a group to obtain a non-standardized fault group; the non-normalized fault groups are normalized to obtain a target fault group.

Specifically, grouping the remaining faulty cells with the same row address or the same column address into a group to obtain a non-standardized set of faults includes the following steps: a1 to A4.

Wherein the non-normalized fault group includes a first non-normalized fault group and a second non-normalized fault group and the remaining fault cells include a first remaining fault cell and a second remaining fault cell.

A1: a first non-standardized fault group is constructed, and a first grouping information list of the first non-standardized fault group is determined.

Specifically, the first non-standardized fault group may be G0, and the first grouping information list is used to store row addresses and column addresses of remaining fault units divided into the first non-standardized fault group.

A2: the row address and the column address of the first remaining faulty cell are obtained.

Wherein the addresses of the remaining faulty cells include a row address and a column address.

A3: and if the first grouping information list is empty or the row address or the column address of the second remaining fault unit existing in the first grouping information list is the same as the row address or the column address of the first remaining fault unit, adding the row address and the column address of the first remaining fault unit into the first grouping information list.

In one case, when the first information list has no remaining defective cell divided yet, and the first grouping information list is empty, the row address and the column address of the first remaining defective cell may be added to the first grouping information list, and if the second remaining defective cell has the same row address or column address as the first remaining defective cell, the second remaining defective cell may also be divided into the first information list. In another case, the first grouping information list is not empty, the second remaining defective cell already exists in the first information list, and the first remaining defective cell having the same row address or column address as the second remaining defective cell is divided into the first information list.

A4: and if the row address and the column address of the second residual fault unit are different from those of the first residual fault unit, establishing a second non-standardized fault group and determining a second grouping information list of the second non-standardized fault group.

Certainly, in the embodiment of the present disclosure, the non-standardized fault group is not limited to only have the first non-standardized fault group and the second non-standardized fault group, and may also have a third non-standardized fault group, a fourth non-standardized fault group, and the like, where the grouping is performed by taking the first non-standardized fault group, the second non-standardized fault, the first remaining fault unit, and the second remaining fault unit as examples, for example, other non-standardized fault groups and remaining fault units are provided, and the grouping method is the same as that described above, and is not described again here.

For example, obtaining a non-standardized set of faults may include the following method. Traversing the residual fault units according to the addresses of the initial residual fault units, adding the addresses of the residual fault units with the same row address or column address as the initial residual fault units into the same grouping information list, and updating the residual fault units.

Specifically, the initialization fault packet number is zero, such as G0 for the first group. An information packet list is initialized for storing addresses of remaining faulty cells of each non-standardized faulty group, including row addresses and column addresses. The initial remaining fault unit can be understood as the remaining fault unit which is added to each information packet list first, when traversing the remaining fault units, the addresses of the remaining fault units with the same row address or the same column address as the initial remaining fault unit can be added to the information packet list according to the addresses of the initial remaining fault units, after the addresses of the remaining fault units are added to the information packet list, the current remaining fault units are grouped, and then updating is performed, so that the remaining fault units are not traversed again, and unnecessary workload is reduced.

And if the address of the current residual fault unit exists in the existing grouping information list, updating the residual fault unit.

If the address of the current remaining fault unit exists in the existing grouping information list, which indicates that the current remaining fault unit has been grouped, i.e. when the current remaining fault unit is grouped, the updating is not successful, and the current remaining fault unit is updated after the traversal. Of course, the number Nf of remaining fault units, the number Nfr of fault rows and the number Nfc of fault columns in the current non-standardized fault group obtained from the current information grouping list, and the number Nmr of multi-fault rows and the number Nmc of multi-fault columns in the current non-standardized fault group may also be updated simultaneously, so as to update all information of each non-standardized fault group synchronously, thereby facilitating subsequent analysis and repair.

And if the address of the current residual fault unit cannot be added into the existing grouping information list, establishing another grouping information list, adding the address of the current residual fault unit into the other grouping information list, taking the current residual unit as the initial residual fault unit of the other grouping information list, and updating the residual fault unit.

Specifically, if the addresses of the traversed current remaining faulty units cannot be added to the existing grouping information list, which indicates that the current remaining faulty units and the remaining faulty units in the existing grouping information list do not have the same row address or column address, the current remaining faulty units need to be divided into another new faulty group. And newly building another grouping information list, adding the address of the current residual fault unit into the another grouping information list, taking the current residual fault unit as the residual fault unit at the beginning of the another grouping information list, and dividing the traversed residual fault unit into a group when the traversed residual fault unit and the current residual fault unit have the same row address or the same column address.

After all the residual fault units are completely traversed, grouping is finished, the number of the non-standardized fault groups is determined according to the number of the grouping information lists, the grouping information lists and the grouping information lists are in one-to-one correspondence, and the residual fault units in each grouping information list are the residual fault units in the non-standardized fault groups.

After obtaining the non-normalized fault group, normalizing the non-normalized fault group to obtain a target fault group, comprising: and performing ascending arrangement according to the row address and the column address of the fault unit in the non-standardized fault group in the row direction and the column direction of the target fault group respectively to generate the target fault group, wherein the first value in the target fault group represents the fault unit, and the second value represents the normal unit.

That is, the fault units in the non-normalized fault group are arranged in ascending order of row address and column address, and the non-normalized fault group is normalized to obtain the target fault group.

Each of the failure groups shown in fig. 6 is a standardized failure group, and in order to display more failure groups for convenience of describing the embodiment of the present disclosure, the number of remaining failure units in fig. 6 is not the same as that shown in fig. 5, and it can be understood that fig. 6 is a remaining failure unit on a chip to be repaired, which is different from fig. 5. As an example, three target failure groups G0, G1, G2 are shown in fig. 6. After standardization, each fault group can be more compact, the problem that subsequent operation is differentiated due to different address information and spatial position relations of fault units in the fault groups is solved, uniqueness of each target path generated in the subsequent operation can be guaranteed, and generation and matching of the subsequent target paths are facilitated.

In some embodiments, after normalizing the non-normalized fault group, the method may further include: and processing the normalized fault group to generate a minimum two-dimensional matrix binary image so as to obtain a target fault group.

As shown in fig. 7, in the minimum two-dimensional matrix binary map, the numbers of the uppermost region and the leftmost region represent index values, the regions other than the index value region are to-be-repaired regions, where 1 may be a first value to represent a faulty cell, 0 may be a second value to represent a normal cell, the minimum two-dimensional matrix binary map is represented by B, and the three minimum two-dimensional matrix binary maps corresponding to the three target fault groups G0, G1, and G2 are B0, B1, and B2, respectively. And a minimum two-dimensional matrix binary diagram is generated, so that the fault rows and fault columns in the standardized fault group can be arranged more compactly, and the subsequent analysis is facilitated.

In some embodiments, as shown in fig. 8, normalizing the non-normalized fault group to obtain the target fault group further comprises: a required minimum spare resource for the non-standardized fault group is determined. If the remaining spare resources are greater than or equal to the minimum required spare resources, the non-standardized fault group is standardized to obtain a target fault group.

That is, before the target failure group is obtained, the minimum required spare resource for repairing the non-standardized failure group is determined, and if the remaining spare resource (i.e., the spare resource remaining after the repair of the necessary repair failure unit in the spare resource) is greater than or equal to the minimum required spare resource, which indicates that the remaining spare resource is sufficient to repair the failure unit in the non-standardized failure group in the chip to be repaired, the process can be continued, so as to obtain the target failure group. And if the residual standby resources are less than the minimum required standby resources, indicating that the residual standby resources are insufficient for repairing the fault unit in the chip to be repaired, and stopping the repairing work on the chip to be repaired so as to save energy consumption.

As an example, as shown in fig. 8, a block diagram for obtaining the required minimum standby resource Nmsc is shown. The method can comprise the following steps: s810 to S8150.

S810: for each non-standard fault group, judging the number Nmr of multi-fault rows of the current non-standard fault group

(i.e., a failed row having a plurality of failed cells) or the number of multiple failed columns Nmc (i.e., a failed column having a plurality of failed cells) is zero; if yes, go to step S820; if not, then execute S830.

S820: the minimum number of standby resources needed for output, nmsc, is 1.

When Nmr or Nmc is zero, all the faulty cells are on a faulty column or a faulty column, and at this time, a spare column or a spare row is needed to repair, so the minimum number of required spare resources Nmsc is 1.

S830: judging whether the number Nmr of the multiple fault rows is smaller than the number Nmc of the multiple fault columns or not; if yes, go to S840; if not, S870 is executed.

S840: continuously judging whether the number Nfr of the fault lines of the current non-standard fault group is greater than the number Nmr of the multiple fault lines; if yes, executing S850; if not, go to S860.

S850: the minimum number of spare resources needed, nmsc, may be output as the number of multiple failed rows, nmr, plus 1.

S860: the minimum number of standby resources needed for output, nmsc, is the number of multiple failed rows, nmr.

S870: continuously judging whether Nmr is equal to Nmc; if yes, executing S880; if not, S890 is executed.

S880: continuously judging whether the number Nfr of the fault rows of the current non-standard fault group is equal to the number Nmr of the multiple fault rows or whether the number Nfc of the fault columns of the current non-standard fault group is equal to the number Nmc of the multiple fault columns; if yes, go to S860; if not, go to S850.

S890: judging whether the number Nfc of the fault columns of the current non-standard fault group is greater than the number Nmc of the multiple fault columns; if yes, executing S8100; if not, S8110 is executed.

S8100: the minimum number of spare resources needed for output, nmsc, is the number of multiple failed columns, nmc, plus 1.

S8110: the minimum number of standby resources needed for output, nmsc, is the number of multiple failed columns, nmc.

S8120: after obtaining the required minimum number of spare resources Nmsc for each non-standard failure group, the required minimum number of spare resources for all non-standard failure groups are summed, as in the following equation (1),

wherein M represents the number of nonstandard fault groups in the chip to be repaired and is a positive integer; c represents the ordinal number of the current nonstandard fault group and is a positive integer.

And obtaining the total quantity N of the minimum standby resources required by the whole chip to be repaired according to the summation formula.

S8130: whether the total number N of the minimum required standby resources is greater than the number (ASR + ASC) of the remaining standby resources, if yes, performing step S8140; if not, go to step 8150.

S8140: the output is not repairable and ends.

S8150: the output is repairable.

By the method, the minimum number of the standby resources required for repairing all fault units of the chip to be repaired can be obtained, and if the number of the remaining standby resources is insufficient, the repair can be stopped as soon as possible by comparing the minimum number of the standby resources with the number of the remaining standby resources, so that the follow-up invalid repair work is avoided, and the energy consumption is saved.

S120: a target path of the target failure group is obtained.

After the target failure group is obtained, a target path of the target failure group may be further obtained. As shown in fig. 9 and 10, the target failure group G (G0, G1, G2) and the corresponding minimum two-dimensional matrix binary map B (B0, B1, B2), the target path P (P0, P1, P2) are exemplarily shown. Obtaining a target path of a target failure group, comprising the steps of: s1010 to S1020.

S1010: if the total number of the fault units in the target fault group is larger than 1, starting from an initial fault unit in the target fault unit, sequentially searching the associated fault units for each fault unit in the target fault group according to a preset direction, and calculating the step length from the current fault unit to the associated next fault unit until all fault units in the target fault group are completely traversed.

S1020: and obtaining a target path of the target fault group according to the direction and the step length from the current fault unit to the associated next fault unit.

In the embodiment of the present disclosure, when the fault unit is traversed, the fault unit is traversed in four directions, i.e., up, down, left, and right, to search for a next fault unit associated with the current fault unit in the current target fault group. The preset direction refers to traversing the current fault unit according to the sequence of the four directions, which is preset in advance. In some embodiments, from the current faulty cell, first looking up, the path may be represented by U, then looking right, the path may be represented by R, then looking left, the path may be represented by L, and finally looking down, the path may be represented by B. Of course, other sequences are possible, and are not particularly limited herein. The first direction of the preset directions may be any one of four directions.

After traversing to the next fault unit, if the next fault unit can not traverse to the fault unit according to the preset direction, returning to the current fault unit; and continuously traversing from the current fault unit according to a second direction in the preset directions until all fault units in the target fault group are completely traversed to obtain a target path of the target fault group.

When the next fault unit cannot traverse to the fault unit according to the preset direction, it can be understood that the fault unit cannot be searched from the next fault unit according to the four directions, and the path at this time is from the next fault unit to the current fault unit, and the path can be represented by N. That is, when any faulty cell passes through in the above four directions, the next faulty cell cannot be found, and the path returns, or when there is only one faulty cell in the faulty group, the path is also N. In addition, the second direction refers to any one of the preset directions except the first direction.

As shown in fig. 9, in the target failure group, each failure unit is traversed in a first direction (which may be, in the above embodiment, first U, then R, then L, and finally B) of the preset directions from the starting point (0, 0), and the step size from the current failure unit to the next failure unit is calculated. And then repeating the steps for the next fault unit, namely traversing the next fault unit according to the preset direction, if other fault units can not be searched according to the preset direction, returning (indicated by N), and then continuing traversing along a second direction in the preset direction until all fault units are completely traversed to generate a target path. As in fig. 9, the target path of the target failure group G0 is R2NB1R1, the target path of the target failure group G1 is R1B1L1NB1R1, and the target path of the target failure group G2 is N. In the figure, G denotes a target failure group, B denotes a minimum two-dimensional matrix binary diagram, and P denotes a path.

The step size may be understood as a relative offset position of a current fault unit and a next fault unit in any one of preset directions in a minimum two-dimensional matrix binary diagram of a normalized target fault group, for example, in the minimum two-dimensional matrix binary diagram, a two-dimensional address of one fault unit is (0, 0), a two-dimensional address of another fault unit is (2, 0), and then the step sizes of the two fault units are 2. The two-dimensional addresses are the column address and the row address in the minimum two-dimensional matrix binary diagram shown in fig. 9. By calculating the step length, the uniqueness of the target path of each target fault group can be ensured, and the repair accuracy is improved.

S130: and obtaining a target repair mode of the target fault group according to the target path.

In some embodiments, obtaining a target repair manner for a target failure group according to a target path includes: obtaining a matching library, wherein the matching library comprises candidate paths and candidate repairing modes corresponding to the candidate paths; and searching candidate paths according to the target path, and determining a target restoration mode from the candidate restoration modes.

The matching library has different candidate paths and corresponding candidate repairing modes which are obtained in advance. The repair method is the number of spare rows and the number of spare columns required to repair a path corresponding to the repair method.

As shown in fig. 11, a predetermined region is selected, and the predetermined region may be, for example, a matrix of q × q, where q may be a positive integer greater than 1. A plurality of candidate failure groups may be included in the preset area (refer to fig. 9).

And acquiring any candidate fault group, wherein the number of fault rows of the candidate fault group is m, the number of fault columns of the candidate fault group is n, and m and n are positive integers. And obtaining the candidate path of the candidate fault group according to the method for obtaining the target path in the embodiment.

And acquiring the candidate repairing mode of the candidate fault group. Specifically, the sizes of the number m of faulty rows and the number n of faulty columns are judged, and the smaller one is repaired. According to permutation combination C ^j _min(m，n) ，j∈[0,min(m，n)]Allocating spare rows/columns to repair the selected j rows/columns, wherein j is the number of the fault rows or the number of the fault columns needing to be repaired in the candidate fault group in one repair; then, repairing the remaining fault units by using the spare columns/rows, recording the number of the spare rows and the spare rows which need to be used, and acquiring the current candidate repairing mode; where C is a permutation combination, min (m, n) is a minimum number value of the number of faulty columns and the number of faulty rows in the candidate faulty group, and j is 0 and a positive integer from 0 to min (m, n). And repairing the candidate fault group for multiple times according to the permutation and combination to obtain multiple candidate repairing modes. And filtering repeated repairing modes and redundant repairing modes in the candidate repairing modes to obtain the final candidate repairing mode.

The above candidate repair method for obtaining the candidate fault group may be further expressed as: and if the number of the fault columns of the candidate fault group is greater than the number of the fault rows, namely m is less than n, repairing the fault columns in the candidate fault group by using the spare columns, wherein the number of the spare columns is decreased from n to 0 according to the repairing times, and after repairing by using the spare columns every time, repairing the residual fault units in the candidate fault group which are not repaired by using the spare columns by using the spare rows in the repairing resources. After repairing the candidate fault group, candidate repairing modes can be obtained, namely the number of required spare columns and the number of required spare rows are obtained. And storing the acquired candidate repairing modes and the candidate paths in a matching library.

It should be noted that the spare rows and the spare columns used for repairing the faulty rows and the faulty columns in the candidate faulty group are not the spare rows and the spare columns in the spare resources used for repairing the chip to be repaired, and do not occupy the spare resources.

As an exemplary embodiment, referring to fig. 12, assuming that the number m of failed rows and the number n of failed columns of the candidate failed group are both 3, the failed rows or failed columns may be repaired first. According to the distribution situation of the fault units, the candidate path P is R1B1L1NB1R1. Wherein, B in FIG. 12 _C And a minimum two-dimensional matrix binary diagram representing the current candidate fault group, wherein a solid line arranged in columns in the minimum two-dimensional matrix binary diagram represents that the candidate fault group is repaired by using spare columns, and a dotted line arranged in rows represents that the candidate fault group is repaired by using spare rows. The candidate repair methods may be obtained as follows.

A: the candidate fault group is repaired using three spare columns, and the repair is obtained in the manner (Nsr: 0, nsc. Where Nsr is the number of spare rows required and Nsc is the number of spare columns required. This step corresponds to C in the above permutation and combination ^j _min(m，n) ＝C ³ ₃ 。

B: and then, one spare column is cancelled according to the sequence of the fault columns {0,1,2}, and the fault unit for cancelling the spare column is repaired by using the spare row to obtain the number of the spare columns and the spare rows required to be used. Three candidate repair approaches were obtained (Nsr: 2, nsc. This step corresponds to C in the above permutation and combination ^j _min(m，n) ＝C ¹ ₃ 。

C: and then sequentially canceling two spare columns of the fault columns (0, 1), (0, 2) and (1, 2), wherein the fault unit for canceling the spare columns uses the spare columns for repair, and the number of the spare columns and the spare rows required to be used is acquired, and the acquired candidate repair modes are (Nsr: 2, nsc.

D: all spare columns are cancelled, only spare rows are used for repair, the number of the spare rows required to be used is obtained, and the candidate repair mode is obtained as (Nsr: 3, nsc.

E: and filtering repeated repairing modes and redundant repairing modes in the candidate repairing modes to obtain the final repairing mode of the candidate fault group.

The repeated repair method means that the number of the required spare rows is completely equal and the number of the required spare columns is completely equal in at least two repair methods. In order to simplify the process, repeated repair modes are filtered out, and only one repair mode is reserved. For example, in fig. 12, in the repeated repair mode, three (Nsr: 2, nsc. The redundant repair method is a repair method in which the number of required spare rows or the number of required spare columns is equal to the number of required spare rows or the number of required spare columns in another repair method, and the sum of the number of required spare rows and the number of spare columns in the redundant repair method is larger than the sum of the number of required spare rows and the number of required spare columns in another repair method. For example, in fig. 12, the redundant repair methods are (Nsr: 2, nsc. The repair approach of filtering out redundancy can reduce complexity and reduce the usage of spare rows and columns.

In fig. 12, the candidate path P of the candidate fault group is R1B1L1NB1R1, and the candidate repair manner corresponding to the candidate path is { (Nsr: 0, nsc. And storing the candidate path and the candidate repairing mode into a matching library.

By the method, the candidate repairing mode of each candidate fault group in the preset area can be obtained, and the candidate repairing mode corresponds to the candidate path of the candidate fault group. In a preset area, for example, in the q × q matrix in fig. 11, it may include multiple candidate fault groups, each fault group has one candidate path, according to the above method, a candidate repair manner corresponding to the candidate path is obtained, and the candidate paths and the candidate repair manners of all candidate fault groups are stored in the matching library, so as to be searched and obtained when the chip to be repaired is repaired.

As shown in fig. 13, after the target path P (P0, P1, P2) of the target fault group of the chip to be repaired is obtained, the candidate path corresponding to the target path is searched in the matching library, and the candidate repairing manner corresponding to the candidate path is the target repairing manner. Therefore, by setting the matching library in advance, when the chip to be repaired is repaired, the target repairing mode can be directly obtained according to the matching of the target path and the candidate path, so that the repairing time is greatly shortened, the analysis efficiency is improved, and the power consumption is saved.

In some embodiments, the target paths of the chip to be repaired include a first target path that does not match the candidate path, the first target path corresponds to a first target failure group, and the target failure group includes the first target failure group. The obtaining of the target repair method of the target fault group according to the target path further includes: acquiring the number m 'of fault rows and the number n' of fault columns of the first target fault group, wherein m 'and n' are positive integers; if the number of the fault columns of the first target fault group is larger than the number of the fault rows, repairing the fault columns in the first target fault group by using the spare columns in the spare resources, wherein the number of the spare columns is decreased from n' to 0 according to the repair times, and after repairing by using the spare columns every time, repairing the residual fault units in the first target fault group which are not repaired by the spare columns by using the spare rows in the spare resources.

That is, when a candidate path matching the target path cannot be searched in the matching library, the target repair method cannot be directly obtained, and at this time, the target repair method of the target failure group needs to be separately obtained to ensure that all the failure units can be completely repaired. The method for acquiring the target repair mode of the target fault is the same as the method for acquiring the candidate repair mode in the candidate fault group in the above embodiment, and details are not repeated here.

In other embodiments, the matching library may not be preset, and after the target path of the target failure group is obtained, the target repair method of the target failure group is obtained according to the method for obtaining the candidate repair method in the above embodiment, which is not described herein again.

S140: and obtaining a target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group.

And after the target repairing mode of each target fault group of the chip to be repaired is obtained, combining the repairing modes of all the target fault groups, and adding the combined repairing modes into the set to obtain the target repairing mode. That is, the target repair means is a set of all target repair means of the entire chip to be repaired.

As shown in fig. 13 and fig. 14, in some embodiments, in order to repair the failed unit in the chip to be repaired using the minimum spare resources, the target failure group in the chip to be repaired includes a first target failure group G0 and a second target failure group G1. The target restoration manner of the first target fault group G0 includes a first-stage target restoration manner [ (Nsr: 0, nsc. The number of the required standby resources in the first-level target repair mode is the same (the number of the required standby resources in fig. 14 is 2), the number of the required standby resources in the second-level target repair mode is the same (the number of the required standby resources in fig. 14 is 3), and the number before each target repair mode in the figure represents the number of the required standby resources. The same number of spare resources means that when a plurality of target repair modes exist in the target repair mode, the sum of the number of spare rows and spare columns in each target repair mode is equal.

Obtaining a target repairing mode of a chip to be repaired according to the target repairing mode of the target fault group, wherein the target repairing mode comprises the following steps: combining a first-stage target repair mode [ (Nsr: 0, nsc ] with a second-stage target repair mode [ (Nsr: 0, nsc; obtaining the quantity of the remaining standby row resources and the quantity of the remaining column resources in the remaining standby resources; and if the quantity of the first required spare row resources is less than or equal to the quantity of the residual spare row resources and the quantity of the first required spare column resources is less than or equal to the quantity of the residual spare column resources, determining that the target repairing modes comprise a first-stage target repairing mode and a second-stage target repairing mode. That is, the spare rows in the spare resources are sufficient to repair the failed rows in the chip to be repaired, the spare columns are sufficient to repair the failed columns in the chip to be repaired, and the target repair mode at this time is the mode using the least spare resources, and is determined as the final target repair mode of the chip to be repaired.

In some embodiments, the first target fault group further includes a third stage target repair manner [ (Nsr: 2, nsc. That is, in each target failure group, the target repair modes are classified according to grades, and the larger the grade number is, the larger the sum of the required spare rows and spare columns is, that is, the larger the required spare resources are.

The method for obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group further comprises the following steps: if the first required number of spare row resources is greater than the number of remaining spare row resources, or the first required number of spare column resources is greater than the number of remaining spare column resources, that is, the spare row or spare column is not sufficient to repair the faulty row or faulty column in the target faulty group, it is highly likely that the spare resources are not sufficient to repair the target faulty group. Combining the third-stage target repair mode [ (Nsr: 2, nsc 1), (Nsr: 3, nsc.

And if the number of the second required spare row resources is less than or equal to the number of the residual spare row resources and the number of the second required spare column resources is less than or equal to the number of the residual spare column resources, determining that the target repair mode comprises a third-stage target repair mode and a second-stage target repair mode. Otherwise, according to the method, other target repairing modes are combined continuously according to the ascending order of the grades. If the number of required spare resources (i.e., the sum of the number of required spare rows and required spare columns) in the resulting target patching mode is greater than the number of spare resources, the repair is ended. By the method, the number of the required standby resources is minimized, and the using amount of the standby resources is saved.

The above embodiment is described with reference to only two target failure groups in fig. 14, and for clarity, the following description is made with reference to three target failure groups in fig. 14 and fig. 15.

Specifically, as shown in fig. 15, obtaining the target repair method of the chip to be repaired according to the target repair method of the target fault group includes the following steps: h1 to H5.

The chip to be repaired comprises a first target fault group G0, a second target fault group G1 and a third target fault group G2. The list of target repair modes of the chip to be repaired is Lcs = [ x, y, z ], where x, y, z represent the level of the selected target repair mode in each target fault group.

H1: for each target failure group, the required spare resources (Nsr + Nsc) are arranged in ascending order, and then the required spare resources are graded, and the repair modes with the same required spare resources are divided into the same grade.

Where Nsr represents the number of spare rows and Nsc represents the number of spare columns. As shown in fig. 14, the target repair manner of the first target failure group G0 is divided into two levels, the target repair manner of the second target failure group G1 is divided into two levels, and the target repair manner of the third target failure group G2 is divided into one level. For ease of description, the first level of target repair in each target failure group is denoted by 0, the second level is denoted by 1, the third level is denoted by 2, \8230;, and so on.

H2: the list of the target fix-up solutions Lcs = [0, 0] is initialized.

Initializing the list of target repair solutions means initializing x, y, and z as 0, i.e., lcs = [0, 0], indicating that the first level target repair method of each target failure group will be combined first.

H3: and combining the target repairing modes in each target fault group according to the ascending order of the grade of the target repairing mode in each target fault group to obtain a repairing set, judging whether the repairing set meets the conditions that Nsr is less than or equal to ASR and Nsc is less than or equal to ASC, if so, executing a step H4, and if not, executing a step H5.

H4: and determining the patching set as a target patching mode.

Specifically, as shown in fig. 14, the target repair manner of the first target failure group G0 is as follows: first rank 0: [ (Nsr: 0, nsc 2) ], second grade 1: [ (Nsr: 2, nsc.

The target repair method of the second target fault group G1 is: first rank 0: [ (Nsr: 0, nsc: [ (Nsr: 2, nsc.

The target repair method of the third target failure group G2 is: first rank 0: [ (Nsr: 1, nsc. Wherein the number of required spare resources of the first level is 1.

And updating Lcs = [0, 0], and combining the first-level target repair modes in each target fault group to obtain a first repair set S1.

S ₁ ＝{[(N _sr ：0，N _sc ：2)，(N _sr ：0，N _sc ：3)，(N _sr ：1，N _sc ：0)][(N _sr ：0，N _sc ：2)，(N _sr ：0，N _sc ：3)，(N _sr ：0，N _sc ：1)]’[(N _sr ：0，N _sc ：2)，(N _sr ：2，N _sc ：1)，(N _sr ：1，N _sc ：0)]’[(N _sr ：0，N _sc ：2)，(N _sr ：2，N _sc ：1)，(N _sr ：0，N _sc ：1)]’[(N _sr ：0，N _sc ：2)，(N _sr ：3，N _sc ：0)，(N _sr ：1，N _sc ：0)]’[(N _sr ：0，N _sc ：2)，(N _sr ：3，N _sc ：0)，(N _sr ：0，N _sc ：1)]’}

The number of required spare rows and the number of required spare columns in any repair mode in the first repair set S1 are calculated. For example, in the repair manner [ (Nsr: 0, nsc.

H5: the list of target fix-ups Lcs = [1, 0] is updated and the target fix-ups for the target failure group are combined according to this list.

Specifically, the second-level target repair method in the first target failure group G0, the first-level target repair method in the second target failure group G1, and the second-level target repair method in the third target failure group G2 are combined to obtain the second repair set S2.

S ₂ ＝[(N _sr ：2，N _sc ：1)，(N _sr ：0，N _sc ：3)，(N _sr ：1，N _sc ：0)][(N _sr ：2，N _sc ：1)，(N _sr ：0，N _sc ：3)，(N _sr ：0，N _sc ：1)]’[(N _sr ：2，N _sc ：1)，(N _sr ：2，N _sc ：1)，(N _sr ：1，N _sc ：0)]’[(N _sr ：2，N _sc ：1)，(N _sr ：2，N _sc ：1)，(N _sr ：0，N _sc ：1)]’[(N _sr ：2，N _sc ：1)，(N _sr ：3，N _sc ：0)，(N _sr ：1，N _sc ：0)]’[(N _sr ：2，N _sc ：1)，(N _sr ：3，N _sc ：0)，(N _sr ：0，N _sc ：1)]’[(N _sr ：3，N _sc ：0)，(N _sr ：0，N _sc ：3)，(N _sr ：1，N _sc ：0)]’[(N _sr ：3，N _sc ：0)，(N _sr ：0，N _sc ：3)，(N _sr ：0，N _sc ：1)]’[(N _sr ：3，N _sc ：0)，(N _sr ：2，N _sc ：1)，(N _sr ：1，N _sc ：0)]’[(N _sr ：3，N _sc ：0)，(N _sr ：2，N _sc ：1)，(N _sr ：0，N _sc ：1)]’[(N _sr ：3，N _sc ：0)，(N _sr ：3，N _sc ：0)，(N _sr ：1，N _sc ：0)]’[(N _sr ：3，N _sc ：0)，(N _sr ：3，N _sc ：0)，(N _sr ：0，N _sc ：1)]’}

The number of required spare rows and the number of required spare columns in any of the repair manners in the second repair set S2 are calculated. For example, in the repair manner [ (Nsr: 2, nsc.

If the second patching set S2 still does not meet the condition, the step of continuously updating Lcs = [1, 0], and the judgment is carried out according to the steps until a patching set meeting the condition is obtained as a target patching way, so that the quantity of standby resources required by the target patching way is minimum.

In some embodiments, after each obtained repair set does not meet the condition that the number of the required spare rows is less than or equal to the number of the spare rows and the number of the required spare columns is less than or equal to the number of the spare columns, whether the sum of the number of the required spare rows and the number of the required spare columns is greater than the number of the remaining spare resources or not may be judged, if so, the repair is stopped if the sum indicates that the remaining spare resources are not enough to repair the faulty cell in the chip to be repaired. Therefore, subsequent processing is not needed, and the time and the power consumption are saved.

In some embodiments, as shown in fig. 15, the method for chip repair of an embodiment of the present disclosure includes the steps of: s10 to S101.

S10: and determining and repairing the necessary repair fault unit. The specific method may refer to S230 in the above embodiment, and details are not repeated here.

S20: and after the necessary repair fault units are repaired, grouping the rest fault units. The specific method can refer to S240 in the above embodiment.

S30: and judging whether the number of the required standby resources is larger than that of the remaining standby resources, if so, executing S40, and otherwise, executing S50.

S40: and (6) ending.

S50: a target failure group is generated. For the specific method, reference is made to S240 in the foregoing embodiment, which is not described herein again.

S60: a target path corresponding to the target failure group is generated. For the specific method, reference is made to S120 in the foregoing embodiment, which is not described herein again.

S70: and matching the target path with the candidate paths in the matching library, and acquiring a target repairing mode.

S80: and judging whether the target path is matched with the candidate path, if so, executing S100, and otherwise, executing S90.

S90: acquiring a target repairing mode for the unmatched target path, and then executing S100;

s100: and judging whether all the target fault groups acquire the target repairing modes, if so, executing S101, and if not, executing S50.

S101: and acquiring a target repairing mode of the required minimum standby resources.

As shown in fig. 15, the method for repairing a chip according to the embodiment of the present disclosure can stop in time when spare resources are insufficient to repair a faulty unit in a target faulty group, thereby avoiding subsequent processing and saving energy consumption. Under the condition that the standby resources are enough, the target repairing mode of the minimum standby resources can be obtained, the standby resources are saved, and meanwhile, the repairing accuracy is improved.

According to the method for repairing the chip, the target path of the target fault group is obtained, and then the space dimension information of the fault unit is obtained, the number of fault groups can be increased, for example, in the target fault group of 4 × 4, the number of target paths which can be generated can reach 40000, infinite expansion can be achieved in theory, the analysis and repair efficiency can be greatly increased, the time cost can be saved, the productivity can be increased, and meanwhile, the repair accuracy rate is greatly increased based on the target path.

In summary, according to the method for repairing the chip in the embodiment of the present disclosure, by obtaining the target path of the target fault group and the target repair manner matched with the target path, the repair scheme can be efficiently and accurately found out under limited standby resources, the time cost of analysis is reduced, and the productivity is improved.

The embodiment of the present disclosure further provides an apparatus 1600 for chip repair, which includes a determining module 1610 and a processing module 1620 as shown in fig. 16.

The determining module 1610 is configured to determine target fault groups in a chip to be repaired, where each target fault group includes at least one faulty unit.

The processing module 1620 is configured to obtain a target path of a target failure group; the processing module 1620 is further configured to obtain a target repair method of the target fault group according to the target path; the processing module 1620 is further configured to obtain a target repair method of the chip to be repaired according to the target repair method of the target fault group.

In some embodiments, the determining module 1610 is further configured to obtain a faulty unit in the chip to be repaired; determining a repair-necessary faulty unit from the faulty units; adopting the standby resources to repair the necessary fault units to obtain the residual standby resources; and grouping the rest fault units except the necessary repair fault unit to obtain a target fault group. Therefore, the fault units in the chip to be repaired are reduced, and the complexity is reduced for subsequent repair.

In some embodiments, the determining module 1610 is further configured to obtain spare rows and spare columns in the spare resource; if the number of the spare rows is larger than that of the spare rows, acquiring repair-indispensable fault rows in the chip to be repaired, wherein the repair-indispensable fault units comprise fault units in the repair-indispensable fault rows, and the number of the fault units in the repair-indispensable fault rows is larger than that of the spare rows; if the number of the standby rows is larger than that of the standby columns, acquiring a necessary repair fault row in the chip to be repaired, wherein the necessary repair fault unit comprises a fault unit in the necessary repair fault row, and the number of the fault unit in the necessary repair fault row is larger than that of the standby columns.

In some embodiments, the determining module 1610 is further configured to group the remaining faulty cells with the same row address or the same column address, obtaining a non-standardized faulty group; normalizing the non-normalized fault group to obtain the target fault group. Thus, the complexity of analysis and repair is reduced.

In some embodiments, the determining module 1610 is further configured to construct a first non-standardized fault group and determine a first grouping information list of the first non-standardized fault group; acquiring a row address and a column address of the first remaining fault unit; if the first grouping information list is empty or the row address or the column address of a second remaining fault unit existing in the first grouping information list is the same as the row address or the column address of the first remaining fault unit, adding the row address and the column address of the first remaining fault unit into the first grouping information list; if the row address and the column address of the second residual fault unit are different from those of the first residual fault unit, a second non-standardized fault group is newly established, and a second grouping information list of the second non-standardized fault group is determined; wherein the non-standardized fault group includes the first non-standardized fault group and the second non-standardized fault group, and the remaining fault cells include the first remaining fault cells and the second remaining fault cells.

In some embodiments, the determining module 1610 is further configured to sort the row addresses and the column addresses of the faulty cells in the non-standardized faulty group in an ascending order in the row direction and the column direction of the target faulty group, respectively, to generate the target faulty group, where the faulty cells are represented by a first value and the normal cells are represented by a second value in the target faulty group.

In some embodiments, the determining module 1610 is further configured to determine a minimum required backup resource for the non-standardized fault group; normalizing the non-normalized fault group to obtain the target fault group if the remaining spare resources are greater than or equal to the minimum required spare resources. And if the residual standby resources are less than the minimum required standby resources, indicating that the residual standby resources are not enough to repair the fault unit in the chip to be repaired, and stopping the repair work of the chip to be repaired so as to save energy consumption.

In some embodiments, the processing module 1620 is further configured to, if the total number of the fault units in the target fault group is greater than 1, sequentially search, starting from a starting fault unit in the target fault units, for each fault unit in the target fault group, associated fault units according to a preset direction, and calculate a step size from a current fault unit to an associated next fault unit until all fault units in the target fault group are completely traversed; and obtaining the target path of the target fault group according to the direction and the step length of the next relevant fault unit searched from the current fault unit.

In some embodiments, the processing module 1620 is further configured to obtain a matching library, where the matching library includes candidate paths and candidate repair methods corresponding to the candidate paths; and searching the candidate paths according to the target path, and determining the target repairing mode from the candidate repairing modes. Through setting up the matching library, when treating the restoration chip and restoreing, can match the direct target restoration mode of acquireing according to target route and candidate route for repair time reduces by a wide margin, improves analysis efficiency, and practice thrift the consumption.

In some embodiments, the target paths include a first target path that does not match the candidate path, the first target path corresponding to a first target failure group, the target failure group including the first target failure group; the processing module 1620 is further configured to obtain a number m 'of fault rows and a number n' of fault columns of the first target fault group, where m 'and n' are both positive integers; if the number of the fault columns of the first target fault group is larger than the number of the fault rows, repairing the fault columns in the first target fault group by using the spare columns in the spare resources, wherein the number of the spare columns is decreased from n' to 0 according to the repair times, and after repairing by using the spare columns every time, repairing the residual fault units in the first target fault group which are not repaired by the spare columns by using the spare rows in the spare resources. Ensuring that all faulty cells can be repaired completely.

In some embodiments, the target failure group includes a first target failure group and a second target failure group, the target repair manner of the first target failure group includes a first-level target repair manner, and the repair manner of the second target failure group includes a second-level target repair manner; the number of the required standby resources in the first-level target repair mode is the same, and the number of the required standby resources in the second-level target repair mode is the same. The processing module 1620 is further configured to combine the first-stage target repair method and the second-stage target repair method to obtain a first required spare row resource quantity and a first required spare column resource quantity of the chip to be repaired; obtaining the quantity of the remaining standby row resources and the quantity of the remaining column resources in the remaining standby resources; and if the number of the first required spare row resources is less than or equal to the number of the residual spare row resources and the number of the first required spare column resources is less than or equal to the number of the residual spare column resources, determining that the target repair mode comprises a first-stage target repair mode and a second-stage target repair mode. The quantity of the needed standby resources can be minimized, and the using amount of the standby resources is saved.

In some embodiments, the first target failure group further includes a third level target repair mode, the number of standby resources required in the third level target repair mode is the same, and the required standby resources in the third level target repair mode are greater than the required standby resources in the first level target repair mode. The processing module 1620 is further configured to, if the number of the first required spare row resources is greater than the number of the remaining spare row resources, or the number of the first required spare column resources is greater than the number of the remaining spare column resources, combine the third-level target repair method and the second-level target repair method to obtain the number of the second required spare row resources and the number of the second required spare column resources of the chip to be repaired; and if the quantity of the second required spare row resources is less than or equal to the quantity of the residual spare row resources and the quantity of the second required spare column resources is less than or equal to the quantity of the residual spare column resources, determining that the target repairing mode comprises a third-stage target repairing mode and a second-stage target repairing mode.

To sum up, the device for repairing a chip according to the embodiment of the present disclosure obtains the target path of the target fault group and the target repairing manner matched with the target path through the processing module 1620, and can efficiently and accurately find out the repairing scheme under limited standby resources, reduce the time cost of analysis, and improve the productivity.

The embodiment of the disclosure also provides computer equipment. As shown in fig. 17, a computer device in embodiments of the present disclosure may include one or more processors 1701, a memory 1702, and an input-output interface 1703. The processor 1701 is connected to the memory 1702 and the input/output interface 1703, respectively, and as shown in fig. 9, the processor 1701, the memory 1702, and the input/output interface 1703 are connected via the bus 1704. The memory 1702 is used for storing a computer program including program instructions, the input/output interface 1703 is used for receiving data and outputting data, such as data interaction between a host and a computer device, or data interaction between virtual machines in the host; the processor 1701 is used to execute program instructions stored in the memory 1702.

The processor 1701 may perform the following operations: determining target fault groups in a chip to be repaired, wherein each target fault group comprises at least one fault unit; obtaining a target path of a target fault group; obtaining a target repair mode of a target fault group according to the target path; and obtaining a target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group.

In some possible implementations, the processor 1701 may be a central processing unit 1620 (CPU), which may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 1702 may include both read-only memory and random-access memory, and provides instructions and data to the processor 1701 and the input/output interface 1703. A portion of memory 1702 may also include non-volatile random access memory. For example, the memory 1702 may also store device type information.

In a specific implementation, the computer device may execute, through each built-in functional module, an implementation manner provided in each step in any one of the above method embodiments, which may be specifically referred to as an implementation manner provided in each step in a diagram shown in the above method embodiments, and details are not described here again.

The disclosed embodiments perform the steps of the method shown in any of the above embodiments by providing a computer apparatus comprising a processor 1701, an input output interface 1703 and a memory 1702, and obtaining a computer program in the memory 1702 by the processor 1701.

The embodiment of the present disclosure further provides a computer-readable storage medium 1800, as shown in fig. 18, the computer-readable storage medium 1800 stores a computer program, and the computer program is suitable for being loaded by the processor 1701 and executing the method for repairing a chip provided in each step in any of the above embodiments, which may specifically refer to the implementation manner provided in each step in any of the above embodiments, and is not described herein again.

In addition, the beneficial effects of the same method are not described in detail. For technical details not disclosed in the embodiments of the computer-readable storage medium 1800 to which the present disclosure relates, refer to the description of the method embodiments of the present disclosure. By way of example, a computer program can be deployed to be executed on one computer device or on multiple computer devices at one site or distributed across multiple sites and interconnected by a communication network.

The computer-readable storage medium 1800 may be an internal storage unit of the computer device provided by any of the foregoing embodiments, such as a hard disk or a memory of the computer device. The computer-readable storage medium 1800 may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Memory Card (SMC), a Secure Digital (SD) card, a flash card (flash card), etc. provided on the computer device. Further, the computer-readable storage medium 1000 may also include both an internal storage unit and an external storage device of the computer device. The computer-readable storage medium 1800 is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium 1800 may also be used to temporarily store data that has been output or is to be output.

Embodiments of the present disclosure also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium 1800. The computer instructions are read by a processor of the computer device from the computer-readable storage medium 1800 and executed by the processor to cause the computer device to perform the method provided in the various alternatives of any of the embodiments described above.

The computer device, the computer readable storage medium, the computer program product or the computer program provided by the embodiment of the disclosure can obtain the target path of the target fault group of the chip to be repaired and the target repair mode matched with the target path, can efficiently and accurately find out the repair scheme under limited standby resources, reduce the time cost of analysis, and improve the productivity.

It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangements of the components set forth in the specification. The present disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the disclosure disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described herein explain the best modes known for practicing the disclosure and will enable others skilled in the art to utilize the disclosure.

Claims (15)

1. A method for chip repair, comprising:

determining target fault groups in a chip to be repaired, wherein each target fault group comprises at least one fault unit;

obtaining a target path of the target fault group;

obtaining a target repair mode of the target fault group according to the target path;

and obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group.

2. The method of claim 1, wherein determining a set of target faults in a chip to be repaired comprises:

obtaining a fault unit in the chip to be repaired;

determining a must-repair failed unit from the failed units;

adopting standby resources to repair the necessary repair fault unit to obtain residual standby resources;

and grouping the remaining fault units except the necessary repair fault unit to obtain the target fault group.

3. The method of claim 2, wherein determining a must-repair failed cell from the failed cells comprises:

obtaining a standby row and a standby column in the standby resource;

if the number of the standby columns is larger than that of the standby rows, acquiring a necessary repair fault column in the chip to be repaired, wherein the necessary repair fault unit comprises a fault unit in the necessary repair fault column, and the number of the fault unit in the necessary repair fault column is larger than that of the standby rows;

if the number of the standby rows is larger than that of the standby columns, acquiring a necessary repair fault row in the chip to be repaired, wherein the necessary repair fault unit comprises a fault unit in the necessary repair fault row, and the number of the fault unit in the necessary repair fault row is larger than that of the standby columns.

4. The method of claim 2, wherein grouping remaining faulty units other than the repair-mandatory faulty unit to obtain the target faulty group comprises:

dividing the remaining fault units with the same row address or the same column address into a group to obtain a non-standardized fault group;

normalizing the non-normalized fault group to obtain the target fault group.

5. The method of claim 4, wherein grouping the remaining faulty cells with the same row address or the same column address into a group, obtaining a non-standardized set of faults comprises:

constructing a first non-standardized fault group, and determining a first grouping information list of the first non-standardized fault group;

acquiring a row address and a column address of the first remaining fault unit;

if the first grouping information list is empty or the row address or the column address of a second remaining fault unit existing in the first grouping information list is the same as the row address or the column address of the first remaining fault unit, adding the row address and the column address of the first remaining fault unit into the first grouping information list;

if the row address and the column address of the second residual fault unit are different from those of the first residual fault unit, establishing a second non-standardized fault group, and determining a second group information list of the second non-standardized fault group;

wherein the non-normalized fault group includes the first non-normalized fault group and the second non-normalized fault group, and the remaining fault cells include the first remaining fault cells and the second remaining fault cells.

6. The method of claim 4, wherein normalizing the non-normalized fault group to obtain the target fault group comprises:

and respectively arranging the row addresses and the column addresses of the fault units in the non-standardized fault group in the row direction and the column direction of the target fault group in an ascending order to generate the target fault group, wherein the first value in the target fault group represents the fault units, and the second value represents the normal units.

7. The method of claim 6, wherein normalizing the non-normalized fault group to obtain the target fault group comprises:

determining a minimum required backup resource for the non-standardized fault group;

normalizing the non-normalized fault group to obtain the target fault group if the remaining spare resources are greater than or equal to the minimum required spare resources.

8. The method of claim 1, wherein obtaining the target path for the target failure group comprises:

if the total number of the fault units in the target fault group is greater than 1, sequentially searching the associated fault units for each fault unit in the target fault group according to a preset direction from an initial fault unit in the target fault group, and calculating the step length from the current fault unit to the associated next fault unit until all fault units in the target fault group are completely traversed;

and obtaining the target path of the target fault group according to the direction and the step length of the next fault unit which is searched from the current fault unit and is associated with the current fault unit.

9. The method of claim 1, wherein obtaining the target repair for the target failure group based on the target path comprises:

obtaining a matching library, wherein the matching library comprises candidate paths and candidate repairing modes corresponding to the candidate paths;

and searching the candidate paths according to the target path, and determining the target repairing mode from the candidate repairing modes.

10. The method of claim 9, wherein the target paths include a first target path that does not match the candidate paths, and wherein the first target path corresponds to a first target failure group, and wherein the target failure group includes the first target failure group;

obtaining a target repair mode of the target fault group according to the target path, further comprising:

acquiring the number m 'of fault rows and the number n' of fault columns of the first target fault group, wherein m 'and n' are positive integers;

if the number of the fault columns of the first target fault group is larger than the number of the fault rows, repairing the fault columns in the first target fault group by using the spare columns in the spare resources, wherein the number of the spare columns is decreased from n' to 0 according to the repairing times, and after repairing by using the spare columns every time, repairing the residual fault units in the first target fault group which are not repaired by the spare columns by using the spare rows in the spare resources.

11. The method of claim 2, wherein the target failure groups include a first target failure group and a second target failure group, wherein the target repair style of the first target failure group includes a first level target repair style, and wherein the repair style of the second target failure group includes a second level target repair style;

the number of the required standby resources in the first-stage target repair mode is the same, and the number of the required standby resources in the second-stage target repair mode is the same;

obtaining a target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group, wherein the step of obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group comprises the following steps:

combining the first-stage target repairing mode and the second-stage target repairing mode to obtain the first required spare row resource quantity and the first required spare column resource quantity of the chip to be repaired;

obtaining the quantity of the remaining standby row resources and the quantity of the remaining column resources in the remaining standby resources;

if the number of the first required spare row resources is less than or equal to the number of the remaining spare row resources and the number of the first required spare column resources is less than or equal to the number of the remaining spare column resources, determining that the target repair mode comprises the first-level target repair mode and the second-level target repair mode.

12. The method of claim 11, wherein the first target failure group further comprises a third level target repair mode, wherein the number of standby resources required in the third level target repair mode is the same, and wherein the required standby resources in the third level target repair mode are larger than the required standby resources in the first level target repair mode;

wherein, obtaining the target repairing mode of the chip to be repaired according to the target repairing mode of the target fault group further comprises:

if the number of the first required spare row resources is larger than the number of the remaining spare row resources, or the number of the first required spare column resources is larger than the number of the remaining spare column resources, combining the third-stage target repair mode and the second-stage target repair mode to obtain the number of the second required spare row resources and the number of the second required spare column resources of the chip to be repaired;

and if the number of the second required spare row resources is less than or equal to the number of the remaining spare row resources and the number of the second required spare column resources is less than or equal to the number of the remaining spare column resources, determining that the target repair mode comprises the third-stage target repair mode and the second-stage target repair mode.

13. An apparatus for chip repair, comprising:

the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining target fault groups in a chip to be repaired, and each target fault group comprises at least one fault unit;

the processing module is used for obtaining a target path of the target fault group;

the processing module is further configured to obtain a target repair mode of the target fault group according to the target path;

the processing module is further configured to obtain a target repair mode of the chip to be repaired according to the target repair mode of the target fault group.

14. A computer device comprising a processor, a memory, an input output interface;

the processor is connected to the memory and the input/output interface, respectively, wherein the input/output interface is configured to receive data and output data, the memory is configured to store a computer program, and the processor is configured to call the computer program to enable the computer device to perform the method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that it stores a computer program adapted to be loaded and executed by a processor to cause a computer device having said processor to perform the method of any of claims 1 to 12.

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