CN115762417A

CN115762417A - Display panel and display device

Info

Publication number: CN115762417A
Application number: CN202211491932.1A
Authority: CN
Inventors: 王炜
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-11-25
Filing date: 2022-11-25
Publication date: 2023-03-07

Abstract

The embodiment of the invention discloses a display panel and a display device, comprising a first cathode power line and a second cathode power line, wherein the first cathode power line transmits a first cathode power voltage, and the second cathode power line transmits a second cathode power voltage; the first cathode power line includes at least one first main power supply portion and at least one first connection portion electrically connected; the second cathode power supply line includes at least one second main power supply portion, at least one second connection portion, and at least one first wiring that are electrically connected; the first non-display area includes a first main power supply portion and a second main power supply portion, at least one of the third non-display area and the fourth non-display area includes a first connection portion, the display area includes a first wiring, and the second non-display area includes a second connection portion. The invention can improve the problem of uneven brightness of the display panel.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display technology, display devices have been gradually spread throughout the lives of people. Among them, the Organic Light-Emitting Diode (OLED) display panel is widely applied to intelligent products such as mobile phones, televisions, notebook computers, etc. because it has the advantages of self-luminescence, low power consumption, wide viewing angle, fast response speed, high contrast, etc. Generally, an anode of the organic light emitting diode receives an anode power voltage and a cathode receives a cathode power voltage, however, since the IC supplies a voltage from the bottom of the display panel, the cathode power voltage drops due to the influence of impedance and coupling capacitance, which results in poor brightness uniformity of the display panel when the display panel displays different brightness pictures.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device, which can solve the problem of uneven brightness of the display panel.

In one aspect, the present invention provides a display panel comprising:

a substrate;

the display device comprises a display area and a non-display area, wherein the non-display area surrounds the display area and comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area; the first non-display area and the second non-display area are positioned on two sides of the display area along a first direction, the third non-display area and the fourth non-display area are positioned on two sides of the display area along a second direction, and the first direction is intersected with the second direction;

a first cathode power line and a second cathode power line, the first cathode power line transmitting a first cathode power voltage, the second cathode power line transmitting a second cathode power voltage;

the first cathode power line includes at least one first main power supply part and at least one first connection part electrically connected; the second cathode power supply line includes at least one second main power supply portion, at least one second connection portion, and at least one first wiring electrically connected;

the first non-display area includes the first main power supply portion and the second main power supply portion, at least one of the third non-display area and the fourth non-display area includes the first connection portion, the display area includes the first wiring, and the second non-display area includes the second connection portion.

In another aspect, the present invention also provides a display device, including:

the display panel according to the first aspect.

Compared with the prior art, the display panel and the display device provided by the invention have the following beneficial effects that: through setting up first cathode power cord and second cathode power cord, first cathode power cord transmits first cathode power supply voltage, second cathode power cord transmits second cathode power supply voltage, and first cathode power cord includes at least one first main power source portion and at least one first connecting portion of electricity connection, second cathode power cord includes at least one second main power source portion of electricity connection, at least one second connecting portion and at least one first wiring, can provide cathode power supply voltage to the display area through first cathode power cord and the second cathode power supply line of laying in the different positions of display panel, thereby improve the uneven problem of display panel luminance.

Drawings

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another display panel provided in an embodiment of the invention;

FIG. 3 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of a pixel according to an embodiment of the present invention;

fig. 6 is a driving timing diagram corresponding to the pixel circuit of fig. 5;

FIG. 7 is an enlarged view of a portion of region Q1 of FIG. 4;

FIG. 8 is another enlarged partial view of the area Q1 in FIG. 4;

FIG. 9 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating a display panel according to another embodiment of the present invention;

FIG. 11 is a diagram of another display panel according to an embodiment of the present invention;

fig. 12 is a partial enlarged view of a region Q2 in fig. 11;

fig. 13-17 are exploded views of the layers of the pixel circuit portion of fig. 12;

FIG. 18 is a cross-sectional view taken along lines BB' of FIG. 12;

fig. 19 is a partial cross-sectional view of a pixel provided by an embodiment of the invention;

FIG. 20 is a cross-sectional view taken along line CC' of FIG. 11;

FIG. 21 is a cross-sectional view taken along line DD' of FIG. 11;

FIG. 22 is a diagram illustrating a display panel according to another embodiment of the present invention;

fig. 23 is a schematic diagram of a display device according to an embodiment of the present invention.

Detailed Description

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict. Also, the shapes and sizes of the various elements in the drawings are not to scale, but are merely illustrative of the present invention.

In order to better understand the technical solutions of the present invention, the technical solutions of the present invention are described in detail below with reference to the drawings and the specific embodiments, and it should be understood that the specific features in the embodiments and the embodiments of the present invention are detailed descriptions of the technical solutions of the present invention, and are not limitations of the technical solutions of the present invention, and the technical features in the embodiments and the embodiments of the present invention may be combined with each other without conflict.

Referring to fig. 1 to 4, fig. 1 is a schematic view of a display panel according to an embodiment of the present invention, fig. 2 is a schematic view of another display panel according to an embodiment of the present invention, fig. 3 is a schematic view of another display panel according to an embodiment of the present invention, and fig. 4 is a schematic view of another display panel according to an embodiment of the present invention. The display panel 100 includes: a substrate 00; a display area AA and a non-display area NA, the non-display area NA surrounding the display area AA, the non-display area NA including a first non-display area NA1, a second non-display area NA2, a third non-display area NA3 and a fourth non-display area NA4; along the first direction X, the first non-display area NA1 and the second non-display area NA2 are located on both sides of the display area AA, along the second direction Y, the third non-display area NA3 and the fourth non-display area NA4 are located on both sides of the display area AA, and the first direction X intersects with the second direction Y; a first cathode power line 10 and a second cathode power line 20, the first cathode power line 10 transmitting a first cathode power voltage, the second cathode power line 20 transmitting a second cathode power voltage; the first cathode power supply line 10 includes at least one first main power supply portion 11 and at least one first connection portion 12 electrically connected; the second cathode power supply line 20 includes at least one second main power supply portion 21, at least one second connection portion 22, and at least one first wiring 23 that are electrically connected; the first non-display area NA1 includes a first main power supply part 11 and a second main power supply part 21, at least one of the third non-display area NA3 and the fourth non-display area NA4 includes a first connection part 12, the display area AA includes a first wiring 23, and the second non-display area NA2 includes a second connection part 22.

In some possible embodiments, the first main power supply portion 11, the second main power supply portion 21 and the second connection portion 22 may extend substantially along the second direction Y, and the first connection portion 12 may extend substantially along the first direction X. The first wiring 23 may also extend substantially in the first direction X.

Substrate 00 can comprise a variety of materials such as glass, metal, or plastic. In exemplary embodiments, for example, substrate 00 can be a flexible substrate comprising a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

The display panel 100 may be rectangular, rounded rectangular, circular, or a display panel with a hole cut at the edge or in the middle of the display area, and the shape of the display panel is not particularly limited in the present invention.

The display panel 100 generally includes a plurality of pixels (not shown in the drawings), and one pixel may emit, for example, red, green, blue, or white light. The display area AA provides a predetermined image by using light emitted from the pixels, and defines a display area AA. The non-display area NA is disposed outside the display area AA. For example, the non-display area NA may surround the display area AA. The non-display area NA is an area in which pixels are not arranged, and thus an image is not provided.

Further, each pixel may further include a pixel circuit and a light emitting element. Referring to fig. 5 and 6, fig. 5 is a diagram of a pixel circuit according to an embodiment of the present invention, and fig. 6 is a driving timing diagram corresponding to the pixel circuit in fig. 5. The pixel circuit in fig. 5 is illustrated by taking a pixel circuit of 7T1C (7 transistors and 1 capacitor) as an example, but the structure of the pixel circuit in the present invention is not limited, and in some other embodiments of the present invention, the pixel circuit may also be embodied as a structure of 8T1C (8 transistors and one capacitor). The pixel circuit includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Two poles of the fifth transistor T5 are respectively connected to the reset signal line Vref and the first node N1, and a gate of the fifth transistor T5 is connected to the first Scan line Scan1. The two poles of the second transistor T2 are respectively connected to the Data line Data and the second node N2, and the gate of the second transistor T2 is connected to the second Scan line Scan2. The first transistor T1 has two electrodes connected to the power supply signal line PVDD and the second node N2, respectively, and a gate connected to the emission control line Emit. The seventh transistor T7 has its both electrodes connected to the reset signal line Vref and a fourth node N4, respectively, and the fourth node N4 is connected to the anode of the light emitting element D0. In the driving circuit of the present embodiment, each transistor is a P-type transistor only for example, but the type of the transistor is not limited. In one frame time, the display panel performs a first reset period T1, a data writing period T2 and a light emitting period T3, in the first reset period T1, the first Scan line Scan1 provides a low level signal to the fifth transistor T5, the fifth transistor T5 is turned on, and the reset signal is transmitted to the driving transistor T3 for resetting the gate of the driving transistor T3. In the data writing phase T2, the second Scan line Scan2 provides a low level signal to the second transistor T2 and the fourth transistor T4, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal is written into the gate of the driving transistor T3 (or referred to as threshold capture of the driving transistor T3). In the light emitting period T3, the light emitting control line Emit supplies a low level signal to the first transistor T1 and the sixth transistor T6, the first transistor T1 and the sixth transistor T6 are turned on, the signal on the anode signal line PVDD is transmitted to the driving transistor T3, and the light emitting element D0 emits light in response to the driving signal of the driving transistor T3. It should be noted that the gate of the seventh transistor T7 may be connected to the first Scan line Scan1, and may also be connected to the second Scan line Scan2; the fifth transistor T5 and the seventh transistor T7 may be connected to the same reset signal line Vref, or may be connected to different reset signal lines, thereby transmitting different reset voltages; the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 may be single-gate transistors or double-gate transistors.

The cathode connection cathode power supply line PVEE of the light emitting element D0 shown in fig. 5 receives a cathode power supply voltage, specifically, a first cathode power supply voltage transmitted through the first cathode power supply line 10, or a second cathode power supply voltage transmitted through the second cathode power supply line 12, which is determined according to the position of the light emitting element D0.

In addition, the first direction X may be a row direction, such as parallel to an extending direction of a scan line in the display panel, and the second direction Y may be a column direction, such as parallel to an extending direction of a data line in the display panel. Of course, the first direction X may also be a column direction, such as parallel to the extending direction of the data lines in the display panel, and the second direction X may also be a row direction, such as parallel to the extending direction of the scan lines in the display panel.

It should be noted that fig. 1 only illustrates that the first cathode power supply line 10 includes one first main power supply portion 11 and one first connection portion 12 that are electrically connected, and the second cathode power supply line 20 includes two second main power supply portions 21, one second connection portion 22, and six first wirings 23 that are electrically connected; fig. 2 only illustrates that the first cathode power supply line 10 includes two first main power supply portions 11 and two first connection portions 12 which are electrically connected, and the second cathode power supply line 20 includes one second main power supply portion 21, one second connection portion 22 and nine first wirings 23 which are electrically connected; fig. 3 only illustrates that the first cathode power supply line 10 includes two first main power supply portions 11 and two first connection portions 12 which are electrically connected, and the second cathode power supply line 20 includes two second main power supply portions 21, one second connection portion 22, and eight first wirings 23 which are electrically connected; fig. 4 only illustrates that the first cathode power supply line 10 includes two first main power supply portions 11 and two first connection portions 12 which are electrically connected, and the second cathode power supply line 20 includes two second main power supply portions 21, one second connection portion 22 and nine first wirings 23 which are electrically connected. The numbers of the first main power supply portion 11, the first connection portion 12, the second main power supply portion 21, the second connection portion 22, and the first wiring 23 shown in fig. 1 to 4 above are merely illustrative, and are not intended to be specific limitations on the numbers thereof.

The inventors of the present invention found through research that the luminance of the light emitting element D0 is related to the cathode power supply voltage it receives, and specifically, the more the cathode power supply voltage drops due to transmission, the more the luminance of the light emitting element D0 decreases. In general, the driving chip supplies a cathode power voltage from the bottom of the display panel, and the internal wiring of the display panel has impedance. According to voltage = current × resistance, if the current is larger, the divided voltage on the internal wiring of the display panel is larger, so that the difference between the cathode power supply voltage at the bottom and the cathode power supply voltage at the top of the display panel is larger, the difference between the pixel current at the upper and lower parts of the display panel is also larger, and the luminance and the pixel current are positively correlated, so that the luminance at the upper and lower parts of the display panel is inconsistent, and the luminance uniformity is deteriorated. That is, the required current is different in magnitude and uniformity when the image displays different brightness. Generally, the higher the brightness, the higher the current, and the less uniform the display panel.

Specifically, in the embodiment of the present invention, the first cathode power line 10 transmits the first cathode power voltage and includes at least one first main power supply portion 11 and at least one first connection portion 12 which are electrically connected, and at least one of the third non-display area NA3 and the fourth non-display area NA4 includes the first connection portion 12, that is, the first cathode power voltage is transmitted to the light emitting element D0 of the display area through the first connection portion 12, and the transmission direction of the first cathode power voltage is two-dimensional planar transmission, which is transmitted from the third non-display area NA3 and/or the fourth non-display area NA4 to the middle of the display panel. The second cathode power line 20 transmits a second cathode power voltage, and includes at least one second main power source 21, at least one second connecting portion 22, and at least one first wire 23, which are electrically connected, the display area AA includes the first wire 23, and the second non-display area NA2 includes the second connecting portion 22, that is, the second cathode power voltage is transmitted to the light emitting element D0 of the display area through the first wire 23 and the second connecting portion 22, and the transmission direction of the second cathode power voltage is also two-dimensional planar transmission, and is transmitted from the second non-display area NA2 to the middle of the display panel, that is, the second cathode power voltage is transmitted from the top of the display panel downward. Therefore, the second cathode power line 20 can precisely control the input of the top cathode power voltage under each luminance according to different luminance requirements, and improve the voltage drop of the cathode power voltage caused by transmission, thereby improving the problem of uneven luminance of the display panel.

Also, in some usage scenarios (e.g., outdoors), in order to achieve a brighter screen display, it is necessary to increase the brightness level of the display panel, and thus it may be necessary to increase the amount of current flowing through the light emitting elements. Therefore, it may be necessary to increase the amount of current flowing through the cathode power supply line. In the prior art, when the cathode power line extends to a corner part (R angle), the width of the cathode power line is greatly changed from the part, so that the heat generated by the part is likely to be higher, and the display panel is easy to generate burn. In the invention, the cathode power voltage in the display panel can be transmitted through the first cathode power line 10 and the second cathode power line 20 respectively, so that the risk of burning of the display panel is not increased, the width of the first cathode power line 10 can be reduced to realize a narrow frame of the display panel, and the user experience is improved.

In some alternative embodiments, with continued reference to fig. 1 to 4, the first non-display area NA1 includes at least one first pad 31 and at least one second pad 32; the first cathode power supply line 10 is electrically connected to the first pad 31, and the second cathode power supply line 20 is electrically connected to the second pad 32.

The first non-display area NA1 is provided with a plurality of pads 30, the pads 30 including at least one first pad 31 and at least one second pad 32, and the pads 30 are not covered by an insulating layer and are exposed, and thus, may be electrically connected with a flexible printed circuit board or a controller (not shown) such as a driving chip. The controller may transmit the first and second cathode power voltages to the first and second

cathode power lines

10 and 20 through the first and

second pads

31 and 32, respectively.

One first main power supply portion 11 may be electrically connected to one or two or more first pads 31, and one second main power supply portion 21 may be electrically connected to one or two or more second pads 32, which are shown in fig. 1 to 4 as just some possible options, and are not specifically limited thereto.

Specifically, the first cathode power line 10 and the second cathode power line 20 are electrically connected to different pads, respectively, and their respective cathode power voltages transmitted are given according to actual tests, and the overall goal is to make the pixel brightness of the upper and lower portions of the display panel as uniform as possible. When displaying images with different brightness, the driving chip transmits a first cathode power voltage to the first cathode power line 10 and a second cathode power voltage to the second cathode power line 20 through the first pad 31 and the second pad 32, respectively, and the transmission of the first cathode power voltage and the transmission of the second cathode power voltage are performed simultaneously. At some high brightness levels, the first cathode power voltage and the second cathode power voltage are not equal in value because the voltage drop of the cathode power voltage is severe. Such as: under 1000nit, the first cathode power supply voltage is 4.0V, and the second cathode power supply voltage is 4.7V; at 500nit, the first cathode supply voltage was 2.3V and the second cathode supply voltage was 2.7V. At some low brightness levels, the first cathode power supply voltage may be equal to the second cathode power supply voltage due to the lower brightness of the display panel.

In the present invention, the first pad 31 electrically connected to the first cathode power line 10 and the second pad 32 electrically connected to the second cathode power line 20 are disposed in the first non-display area NA1, so that the first cathode power voltage and the second cathode power voltage can be respectively transmitted according to the display requirements of different brightness, thereby improving the problem of uneven brightness of the display panel.

In some alternative embodiments, the display panel 100 further includes a cathode layer (not shown), the first cathode power line 10 is electrically connected to the cathode layer, and the second cathode power line 20 is electrically connected to the cathode layer.

The light emitting element D0 generally includes an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode may include a transparent electrode or a reflective electrode. In the case where the anode includes a transparent electrode, a transparent conductive layer may be included. Such as at least one of indium tin oxide, indium zinc oxide, indium gallium oxide, and aluminum zinc oxide. In this case, the anode may include a semi-transmissive layer configured to improve light efficiency, in addition to the transparent conductive layer. In an exemplary embodiment, the semi-transmissive layer may include a thin layer ranging from several nanometers to several tens of nm and including at least one of Ag, mg, al, pt, pd, au, ni, nd, ir, cr, li, ca, and Yb. In the case where the anode includes a reflective electrode, the anode may include a reflective layer including at least one of Ag, mg, al, pt, pd, au, ni, nd, ir, cr, and a mixture thereof, and a transparent conductive layer disposed on and/or under the reflective layer. In an exemplary embodiment, the transparent conductive layer may include at least one of ITO, IZO, znO, in2O3, IGO, and AZO. The organic light emitting layer may include a structure in which a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, an electron injection layer, and the like are stacked in a single structure or a composite structure. The cathode may include a transparent electrode or a reflective electrode. In case the cathode comprises a transparent electrode, such as: the cathode may include at least one of Ag, al, mg, li, ca, cu, liF/Ca, liF/Al, mgAg, and CaAg, and may include a thin layer having a thickness ranging from several nm to several tens of nm. In case the cathode comprises a reflective electrode, such as: the cathode may include at least one of Ag, al, mg, li, ca, cu, liF/Ca, liF/Al, mgAg, and CaAg.

And the cathode layer may be disposed throughout the display area AA and may cover the display area AA. That is, the cathodes of the plurality of light emitting elements D0 are integrally provided to form a cathode layer, so that the cathode layer can correspond to the plurality of anodes.

In the embodiment of the present invention, the cathode layer is electrically connected to the first cathode power line 10 and the second cathode power line 20 disposed at different positions of the display panel, so that the cathodes of the light emitting elements D0 at different positions receive different cathode power voltages (the first cathode power voltage and the second cathode power voltage) respectively and simultaneously, thereby improving the problem of uneven brightness of the display panel.

In some alternative embodiments, referring to fig. 2 to 4, the first cathode power line 10 includes two first connection portions 12, and the third and fourth non-display areas NA1 and NA2 include one first connection portion 12, respectively.

Specifically, the first connecting portion 12 is disposed on both sides of the display area AA along the second direction Y, that is, the third non-display area NA1 and the fourth non-display area NA2, so that the first cathode power voltage can be provided to both sides of the display area at the same time, thereby reducing the voltage drop of the first cathode power voltage, making the luminance of the display areas on both sides of the display panel 100 consistent, and avoiding the occurrence of luminance difference. Meanwhile, the first cathode power voltage can be transmitted to the display area through the first connecting portions 12 on the left and right sides via two paths, so that the problem of inconsistency of frames on two sides of the display panel can be avoided, and user experience is improved.

In some alternative embodiments, with continued reference to fig. 2 to 4, the second cathode power line 20 further includes a third connection part 24, and the first non-display area NA1 includes the third connection part 24. The second cathode power supply line 20 includes a plurality of first wirings 23, and one ends of the plurality of first wirings 23 are electrically connected to the second connection portion 22 and the other ends are electrically connected to the third connection portion 24.

The third connection portion 24 may extend in the second direction Y. In some embodiments, the third connection part 24 may extend along a length less than the length along which the display area AA extends. When the four corners of the display area AA of the display panel 100 are non-right angles (e.g., R corners), the third connection part 24 may not be disposed around the corner part. The third connection portion 24 is electrically connected directly to the second main power supply portion 21 and the first wiring 23, and further electrically connected to the cathode layer through the first wiring 23 and the second connection portion 22.

The third connection portion 24 may electrically connect the plurality of first wirings 23 together in the first non-display area NA1, so that more first wirings 23 may be provided accordingly; in other words, more first wires 23 can be distributed in the display area through the third connection portion 24, so as to transmit the second cathode power voltage, thereby reducing the voltage drop of the second cathode power voltage in the transmission process and improving the problem of uneven brightness of the display panel.

In some alternative embodiments, referring to fig. 7 and 8, fig. 7 is an enlarged view of a portion of region Q1 of fig. 4; fig. 8 is another partial enlarged view of the region Q1 in fig. 4. The display panel 100 includes a plurality of data lines DL extending in a first direction X and arranged in a second direction Y; the orthographic projection of the first wiring 23 on the substrate 00 is a first projection, the orthographic projection of the data line DL on the substrate 00 is a second projection, N second projections are arranged between two adjacent first projections, and N is not less than 1 and is an integer.

In the drawings, the data line DL and the first wiring 23 are illustrated as lines having different widths, which are only for convenience of explanation and are not intended to limit the widths thereof.

Specifically, the display panel 100 includes a plurality of pixels P arranged in a matrix along a first direction X and a second direction Y, the plurality of pixels P forming pixel columns along the first direction X, and the plurality of pixels P forming pixel rows along the second direction Y. One data line DL may be disposed in one pixel column, and the first wiring 23 and the data line DL may be located in the same film layer or different film layers. The data line DL and the first wiring 23 may or may not overlap, may partially overlap or completely overlap in a direction perpendicular to the plane of the substrate 00. Taking the case that the data line DL and the first wiring 23 are not overlapped, the orthographic projection of the first wiring 23 on the substrate 00 is a first projection, the orthographic projection of the data line DL on the substrate 00 is a second projection, N second projections are arranged between two adjacent first projections, and N is not less than 1 and is an integer. The number of the first wirings 23 may be equal to the number of the data lines DL, that is, the first wirings 23 are disposed in one-to-one correspondence with the pixel columns, as shown in fig. 7, there are 1 second projection between two adjacent first projections; the number of the first wirings 23 may be smaller than the number of the data lines DL, and one first wiring 23 is disposed at intervals of two columns of the pixels, as shown in fig. 8, and there are 2 second projections between two adjacent first projections. Of course, N may have other values, and one first wiring 23 may be provided at intervals of a plurality of pixel columns. Alternatively, a plurality of first wirings 23 may be provided between two adjacent columns of data lines. The larger the number of the first wirings 23, the better the voltage drop improvement effect on the second cathode power supply voltage. However, since the transmittance or the aperture ratio of the display panel may be affected, the arrangement density of the first wires 23 needs to be set according to actual requirements in order to improve the luminance unevenness of the display panel and not affect the transmittance or the aperture ratio of the display panel.

In some alternative embodiments, referring to fig. 9, fig. 9 is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel 100 further includes an anode power line 40, the anode power line 40 including at least one third main power supply part 41, at least one fourth connection part 42, and at least one second wiring 43 electrically connected; the first non-display area NA1 includes a third main power supply part 41 and a fourth connection part 42, and the display area AA includes a second wiring 43.

It is understood that, in the first non-display area NA1 of the display panel 100, the pad 30 further includes a third pad 33, and the controller may transmit the anode power voltage to the anode power line 40 and thus to the anode of the pixel through the third pad 33. The number of the third main power supply part 41, the fourth connection part 42 and the second wiring 43 included in the anode power supply line 40 can be designed according to actual requirements, and is only one possible illustration in fig. 9. The third main power supply portion 41 may extend substantially in the first direction X, the fourth connection portion 42 may extend substantially in the second direction, and the second wiring 43 may extend substantially in the first direction X. The fourth connection part 42 may extend in the first direction X by a length less than that of the display area AA. When the four corners of the display area AA of the display panel 100 are non-right angles (e.g., R corners), the fourth connection part 42 may not be disposed around the corner portion. Since the driving voltage line that may be electrically connected to the fourth connection part 42 includes a mesh structure of the second wiring 43 and the third wiring (not shown in the drawings) that may intersect the second wiring 43, even if the fourth connection part 42 is not disposed around the corner part, the anode voltage may be supplied to all pixels within the display panel, thereby driving the pixels to emit light.

In some alternative embodiments, referring to fig. 10 and 11, fig. 10 is a schematic diagram of another display panel provided in the embodiment of the present invention, and fig. 11 is a schematic diagram of another display panel provided in the embodiment of the present invention. The fourth connection portion 42 and the third connection portion 24 at least partially overlap in a direction perpendicular to the plane of the substrate 00.

In fig. 10, the fourth connection portion 42 and the third connection portion 24 partially overlap in the first direction X. In fig. 11, the four connection portions 42 and the third connection portion 24 completely overlap in the first direction X; that is, the fourth connection portion 42 and the third connection portion 24 have the same width along the first direction X, and boundary projections extending along the second direction Y overlap.

It should be noted that, first non-display area NA1 can include the bending area, and the part in first non-display area NA1 can be along with the bending of bending area and turn over to the non-light-emitting side of display panel, avoids occuping the positive space of display panel, therefore is favorable to realizing display panel's narrow frame design, promotes the screen of display product and accounts for than, and then is favorable to promoting user's use experience effect. And the fourth connection portion 42 and the third connection portion 24 are located in the first non-display area NA1, and by setting the fourth connection portion 42 and the third connection portion 24 to be at least partially overlapped, the width of the first non-display area NA1 on the front surface of the display panel can be further reduced, thereby implementing a narrow bezel of the display panel.

In some alternative embodiments, referring to fig. 11 to 18, fig. 12 is a partially enlarged view of a region Q2 in fig. 11, fig. 13 to 17 are exploded views of a film layer of a pixel circuit portion in fig. 12, and fig. 18 is a cross-sectional view along BB' in fig. 12. The first wiring 23 and the second wiring 43 at least partially overlap in a direction perpendicular to the plane of the substrate 00. The display panel 100 includes a semiconductor layer 51, a first metal layer 52, a capacitor metal layer 53, a second metal layer 54, a third metal layer 55, and an anode layer 56, which are located on one side of the substrate 00 and arranged in a direction away from the substrate 00; the first wiring 23 is located in the third metal layer 55.

It is understood that the first wiring 23 and the second wiring 43 at least partially overlap, and specifically, the first wiring 23 and the second wiring 43 only partially overlap, or the first wiring 23 and the second wiring 43 completely overlap in the display area AA.

In understanding fig. 12, reference may be made to the description above with respect to fig. 5 and 6. The display panel 100 includes a semiconductor layer 51, a first metal layer 52, a capacitor metal layer 53, a second metal layer 54, a third metal layer 55, an anode layer 56 (including a plurality of anode REs), and an insulating layer between adjacent conductive layers, on the substrate 00 side and in a direction away from the substrate 00, and further includes a light emitting layer 57, a cathode layer 58, and an encapsulation layer 59. In fig. 11, the third metal layer 55 is not used for the via from the anode layer 56 down to the semiconductor layer 51, but in some other embodiments, the third metal layer 55 may be used for the via, and the invention is not provided in the accompanying drawings.

Specifically, by overlapping the first wiring 23 and the second wiring 43 at least partially in a direction perpendicular to the plane of the substrate 00, the influence on the aperture ratio of the display panel due to the provision of the first wiring 23 can be avoided. And the first wiring 23 and the second wiring 43 transmit the second cathode power voltage and the anode power voltage, respectively, and the second cathode power voltage and the anode power voltage are generally constant voltages or are both constant voltages for a long time (may be non-constant voltages in some specific cases or change voltage values), so that interference of the second cathode power voltage and the anode power voltage to other signals in the transmission process can be avoided, and the display effect of the display panel is ensured.

In some alternative embodiments, with continued reference to fig. 11-18, the first wire 23 is located on a side of the second wire 43 away from the substrate.

Since the first wiring 23 is electrically connected to the cathode layer 58 through the second connection portion 22, the first wiring 23 can be positioned on the side of the second wiring 43 away from the substrate, so that the first wiring 23 can be closer to the cathode layer 58, thereby reducing the difficulty of the subsequent processes and improving the yield of the display panel.

In some alternative embodiments, referring to fig. 18, the data line DL may be in the same layer as the second wiring 43 or in the same layer as the first wiring 23, and the present invention is not limited in particular. Alternatively, the first wiring 23 is provided in the second metal layer 54, and the second wiring 43 and the data line DL are provided in any film layer of the second metal layer 54 and the third metal layer 55. Of course, the first wiring 23 may be provided in the same layer as the second wiring 43 and the data line DL instead of separately providing the third metal layer 55.

In some alternative embodiments, referring to fig. 18 and 19, fig. 19 is a partial cross-sectional view of a pixel provided by an embodiment of the invention. The display panel 100 includes a semiconductor layer 51, a first metal layer 52, a capacitor metal layer 53, a second metal layer 54, a third metal layer 55, a fourth metal layer 60, and an anode layer 56, which are located on one side of the substrate 00 and are disposed in a direction away from the substrate 00; the first wiring 23 is located in at least one of the second metal layer 54, the third metal layer 55, and the fourth metal layer 60.

In fig. 18, the first wiring 23 is described as being located in the third metal layer 55. In fig. 20, the first wiring 23 is described as being located in the third metal layer 55 and the fourth metal layer 60.

It is understood that the second wiring 43 and the data line DL may be selectively disposed in at least one of the second metal layer 54, the third metal layer 55 and the fourth metal layer 60 according to actual requirements, for example, the second wiring 43 may be disposed in both the second metal layer 54 and the third metal layer 55; the two layers may be different layers, for example, the second wiring 43 is located in the second metal layer 54, and the data line DL is located in the third metal layer 55, or the second wiring 43 is located in the second metal layer 54 and the third metal layer 55, and the data line DL is located in the third metal layer 55, which is not limited in this embodiment.

Specifically, in the present invention, the first wire 23 is disposed on at least one of the second metal layer 54, the third metal layer 55 and the fourth metal layer 60, so that the metal film layer of the display panel can be fully utilized to reduce the transmission impedance of the second cathode power voltage in the first wire 23, thereby improving the uneven brightness of the display panel.

In some alternative embodiments, referring to fig. 11 and 20, 21, fig. 20 is a cross-sectional view taken along CC 'in fig. 11, and fig. 21 is a cross-sectional view taken along DD' in fig. 11. The first connection portion 12 is located in at least one of the second metal layer 54, the third metal layer 55, and the anode layer 56; the second connection 22 is at least partially located at the anode layer 56.

Specifically, when the display panel 100 includes the semiconductor layer 51, the first metal layer 52, the capacitor metal layer 53, the second metal layer 54, the third metal layer 55, and the anode layer 56 on the substrate 00 side and arranged in a direction away from the substrate 00, the first connection portion 12 may be located at least one of the second metal layer 54, the third metal layer 55, and the anode layer 56; the second connection 22 is at least partially located at the anode layer 56. For example, the first connection portion 12 may be arranged by using one or both of the second metal layer 54, the third metal layer 55 and the anode layer 56, and as shown in fig. 20, the first connection portion 12 may include a first branch portion 121 located in the second metal layer 54, a second branch portion 122 located in the third metal layer 55 and a third branch portion 123 located in the anode layer 56. The second connecting portion 22 is at least located on the anode layer 56, such as the fourth branch portion 222, and may further include a fifth branch portion 221 located on the third metal layer 55. The specific setting mode can be reasonably set according to the film layer of the display panel.

It is understood that, referring to fig. 20, the third non-display area NA3 further includes a driving circuit DC, and the driving circuit DC may at least partially overlap the first connection part 12. The present invention is not particularly limited in this regard.

Alternatively, when the display panel 100 includes the semiconductor layer 51, the first metal layer 52, the capacitor metal layer 53, the second metal layer 54, the third metal layer 55, the fourth metal layer 60, and the anode layer 56, which are located on one side of the substrate 00 and are disposed in a direction away from the substrate 00, the first connection portion 12 may be located on at least one of the second metal layer 54, the third metal layer 55, the fourth metal layer 60, and the anode layer 56; the second connection 22 is at least partially located at the anode layer 56.

Specifically, the first connection portion 12 may be arranged with any film layer of the second metal layer 54, the third metal layer 55, the fourth metal layer 60, the anode layer 56; the second connection portion 22 is at least located at the anode layer 56, and may be further disposed by using a film layer such as a third metal layer 55 and a fourth metal layer 60.

In some optional embodiments, the first main power supply part 11 is located in at least one of the second metal layer 54 and the third metal layer 55; the second main power supply portion 21 is located in at least one of the second metal layer 54 and the third metal layer 55.

Specifically, the first main power supply portion may be disposed with any film layer of the second metal layer 54 and the third metal layer 55, and the second main power supply portion 21 may also be disposed with any film layer of the second metal layer 54 and the third metal layer 55. The first main power supply part 11 and the second main power supply part 21 may or may not overlap in a direction perpendicular to the plane of the substrate, and those skilled in the art can set them according to actual needs.

It is understood that the film of the third connection portion 24 may also be selectively disposed in the first metal layer 52 to the third metal layer 55 or the first metal layer 52 to the fourth metal layer 60, which is not described herein again.

Set up first connecting portion 12 and second connecting portion 22 through the relevant metal film layer in the rational utilization display panel, can transmit first cathode power supply voltage and second cathode power supply voltage to cathode layer 58 in the display panel, simultaneously, can reduce the impedance of first cathode power supply line 10 and second cathode power supply voltage line through rete overlap or multiplexing mode, improve the uneven problem of display panel luminance.

In some alternative embodiments, referring to fig. 22, fig. 22 is a schematic view of another display panel provided in the embodiments of the present invention. The second cathode power line 20 further includes at least one fifth connection part 25 electrically connected to the second connection part 22, and at least one of the third non-display area NA3 and the fourth non-display area NA4 includes the fifth connection part 25; the first connection portion 12 and the fifth connection portion 25 have a gap in a direction perpendicular to the plane of the substrate 00.

It should be noted that, the first connection portion 12 and the fifth connection portion 25 have a gap, which means that, in a direction perpendicular to the plane of the substrate 00, the first connection portion 12 and the fifth connection portion 25 do not overlap; alternatively, if the first connection portion 12 and the fifth connection portion 25 are made of the same film layer, they are not connected to each other in the film layer. In fig. 22, only the fifth connecting portion 25 is disposed in both the third non-display area NA3 and the fourth non-display area NA 4.

Specifically, in this embodiment, by providing the fifth connection portion 25 in at least one of the third non-display area NA3 and the fourth non-display area NA4, the transmission range of the first cathode power voltage can be further increased in the upper portion of the display panel 100, thereby further improving the problem of uneven brightness of the display panel.

It should be noted that, in the embodiments of the display panel provided by the present invention, the technical features can be freely combined without conflict, and the present invention is not exhaustive.

An embodiment of the present invention further provides a display device, as shown in fig. 23, fig. 23 is a schematic diagram of a display device provided in an embodiment of the present invention, and the display device includes the display panel. The specific structure of the display panel has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 23 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.

The display panel and the display device provided by the embodiment of the invention are described in detail, and the principle and the embodiment of the invention are explained by applying a specific example, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A display panel, comprising:

a substrate;

a first cathode power line and a second cathode power line, the first cathode power line transmitting a first cathode power voltage and the second cathode power line transmitting a second cathode power voltage;

2. The display panel according to claim 1, wherein the first non-display region comprises at least one first pad and at least one second pad;

the first cathode power line is electrically connected to the first pad, and the second cathode power line is electrically connected to the second pad.

3. The display panel of claim 1, further comprising a cathode layer, wherein the first cathode power line is electrically connected to the cathode layer, and wherein the second cathode power line is electrically connected to the cathode layer.

4. The display panel according to claim 1, wherein the first cathode power supply line includes two of the first connection portions, and wherein the third non-display region and the fourth non-display region respectively include one of the first connection portions.

5. The display panel according to claim 1, wherein the second cathode power supply line further includes a third connection portion, and the first non-display region includes the third connection portion.

6. The display panel according to claim 5, wherein the second cathode power supply line includes a plurality of the first wirings, one end of each of the plurality of the first wirings is electrically connected to the second connection portion, and the other end is electrically connected to the third connection portion.

7. The display panel according to claim 1, wherein the display panel includes a plurality of data lines extending in the first direction and arranged in the second direction;

the orthographic projection of the first wiring on the substrate is a first projection, the orthographic projection of the data line on the substrate is a second projection, N second projections are arranged between every two adjacent first projections, and N is not less than 1 and is an integer.

8. The display panel according to claim 1, characterized by further comprising an anode power supply line including at least one third main power supply portion, at least one fourth connection portion, and at least one second wiring which are electrically connected;

the first non-display area includes the third main power supply portion and the fourth connection portion, and the display area includes the second wiring.

9. The display panel according to claim 8, wherein the fourth connection portion and the third connection portion at least partially overlap in a direction perpendicular to a plane in which the substrate is located.

10. The display panel according to claim 8, wherein the first wiring and the second wiring at least partially overlap in a direction perpendicular to a plane in which the substrate is present.

11. The display panel according to claim 8, wherein the first wiring is located on a side of the second wiring which is away from the substrate.

12. The display panel according to claim 8, wherein the display panel comprises a semiconductor layer, a first metal layer, a capacitor metal layer, a second metal layer, a third metal layer, and an anode layer on a side of the substrate and arranged in a direction away from the substrate;

the first wiring is located in at least one of the second metal layer and the third metal layer.

13. The display panel according to claim 12,

the first connecting part is positioned in at least one of the second metal layer, the third metal layer and the anode layer;

the second connection portion is at least partially located at the anode layer.

14. The display panel according to claim 8, wherein the display panel comprises a semiconductor layer, a first metal layer, a capacitor metal layer, a second metal layer, a third metal layer, a fourth metal layer, and an anode layer which are provided on a side of the substrate in a direction away from the substrate;

the first wiring is located in at least one of the second metal layer, the third metal layer and the fourth metal layer.

15. The display panel according to claim 14,

the first connecting part is positioned in at least one of the second metal layer, the third metal layer, the fourth metal layer and the anode layer;

the second connection portion is at least partially located at the anode layer.

16. The display panel according to claim 12 or 14,

the first main power supply portion is located in at least one of the second metal layer and the third metal layer;

the second main power supply portion is located in at least one of the second metal layer and the third metal layer.

17. The display panel according to claim 1, wherein the second cathode power supply line further comprises at least one fifth connection portion electrically connected to the second connection portion, and at least one of the third non-display region and the fourth non-display region comprises the fifth connection portion;

the first connecting portion and the fifth connecting portion have a gap in a direction perpendicular to a plane of the substrate.

18. A display device characterized by comprising a display panel according to any one of claims 1 to 17.